CY7C4265V-15ASC
CY7C4265V-15ASC Datasheet
CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V
| Part | Datasheet |
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CY7C4265V-15ASC |
CY7C4265V-15ASC (pdf) |
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| 285V CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V 32K/64Kx18 Low Voltage Deep Sync FIFOs Functional Description • 3.3V operation for low power consumption and easy integration into low-voltage systems • High-speed, low-power, first-in first-out FIFO memories • 8K x 18 CY7C4255V • 16K x 18 CY7C4265V • 32K x 18 CY7C4275V • 64K x 18 CY7C4285V • micron CMOS for optimum speed/power • High-speed 100-MHz operation 10-ns read/write cycle times • Low power ICC = 30 mA ISB = 4 mA • Fully asynchronous and simultaneous read and write operation • Empty, Full, Half Full, and programmable Almost Empty and Almost Full status flags • Retransmit function • Output Enable OE pin • Independent read and write enable pins • Supports free-running 50% duty cycle clock inputs • Width Expansion Capability • Depth Expansion Capability • 64-pin 10x10 STQFP • Pin-compatible density upgrade to CY7C42X5V-ASC families • Pin-compatible 3.3V solutions for CY7C4255/65/75/85 The CY7C4255/65/75/85V are high-speed, low-power, first-in first-out FIFO memories with clocked read and write interfaces. All are 18 bits wide and are pin/functionally compatible to the CY7C42X5V Synchronous FIFO family. The CY7C4255/65/75/85V can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering. These FIFOs have 18-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free-running clock WCLK and a write enable pin WEN . When WEN is asserted, data is written into the FIFO on the rising edge of the WCLK signal. While WEN is held active, data is continually written into the FIFO on each cycle. The output port is controlled in a similar manner by a free-running read clock RCLK and a read enable pin REN . In addition, the CY7C4255/65/75/85V have an output enable pin OE . The read and write clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 67 MHz are achievable. Retransmit and Synchronous Almost Full/Almost Empty flag features are available on these devices. Depth expansion is possible using the cascade input WXI, RXI , cascade output WXO, RXO , and First Load FL pins. The WXO and RXO pins are connected to the WXI and RXI pins of the next device, and the WXO and RXO pins of the last device should be connected to the WXI and RXI pins of the first device. The FL pin of the first device is tied to VSS and the FL pin of all the remaining devices should be tied to VCC. Logic Block Diagram D0 17 INPUT REGISTER WCLK WRITE CONTROL WRITE POINTER High Density Dual-Port RAM Array 8Kx9 16Kx9 32Kx9 64Kx9 FLAG PROGRAM REGISTER FLAG LOGIC READ POINTER FF EF PAF SMODE RESET LOGIC FL/RT WXI WXO/HF RXI RXO EXPANSION LOGIC THREE-ST ATE OUTPUT REGISTER READ CONTROL Q0 17 3901 North First Street • Ordering Information 8Kx18 Low-Voltage Deep Sync FIFO Speed ns Ordering Code CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V Package Name Package Type 64-Lead 10x10 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack Operating Range Commercial Commercial Commercial 16Kx18 Low-Voltage Deep Sync FIFO Speed ns Ordering Code 32Kx18 Low-Voltage Deep Sync FIFO Speed ns Ordering Code 64Kx18 Low-Voltage Deep Sync FIFO Speed ns Ordering Code Package Name Package Type 64-Lead 10x10 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack Package Name Package Type 64-Lead 10x10 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack Package Name Package Type 64-Lead 10x10 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack Operating Range Commercial Operating Range Commercial Operating Range Commercial Industrial Commercial Page 18 of 20 CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V Package Diagrams 64-Pin Thin Plastic Quad Flat Pack 10 x 10 x mm A64 51-85051-A Page 19 of 20 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V Document Title CY7C4255V, CY7C4265V, CY7C4275V, CY7C4285V 32K/64K x 18 Low Voltage Deep Sync FIFOs Document Number 38-06012 ECN NO. Issue Date Orig. of Change Description of Change 106473 09/10/01 SZV Change from Spec number 38-00654 to 38-06012 122264 12/26/02 RBI Power up requirements added to Maximum Ratings Information Page 20 of 20 |
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