AT17LV020-10JI

AT17LV020-10JI Datasheet

The AT17C020 and AT17LV020 high-density AT17 Series FPGA Configuration EEPROMs Configurators provide an easy-to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The AT17 Series is packaged in the popular 20-pin PLCC. The AT17 Series family uses a simple serial-access procedure to configure one or more FPGA devices. The AT17 Series organization supplies enough memory to configure one or multiple smaller FPGAs. The user can select the polarity of the reset function by programming internal EEPROM bytes. These devices also support a system-friendly READY pin, which signifies a “good” power level to the FPGA and can be used to ensure reliable system power-up.

Part	Datasheet
AT17LV020-10JI	AT17LV020-10JI (pdf)

Related Parts	Information
AT17C020-10JI	AT17C020-10JI
AT17LV020-10JC	AT17LV020-10JC
AT17C020-10JC	AT17C020-10JC

PDF Datasheet Preview
• EE Reprogrammable 2,097,152 x 1 bit Serial Memories Designed to Store Configuration Programs for Field Programmable Gate Arrays FPGAs • In-System Programmable via 2-wire Bus • Simple Interface to SRAM FPGAs • Compatible with Atmel AT6000, AT40K FPGAs, Altera Devices, FPGAs, Xilinx XC3000, XC4000, XC5200, FPGAs • Cascadable Read Back to Support Additional Configurations or Future Higher-density Arrays • Low-power CMOS EEPROM Process • Programmable Reset Polarity • Available in PLCC Package Pin Compatible across Product Family • Emulation of Atmel’s AT24CXXX Serial EEPROMs • Available in 3.3V ± 10% LV and 5V ± 5% C Versions • System-friendly READY Pin • Low-power Standby Mode The AT17C020 and AT17LV020 high-density AT17 Series FPGA Configuration EEPROMs Configurators provide an easy-to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The AT17 Series is packaged in the popular 20-pin PLCC. The AT17 Series family uses a simple serial-access procedure to configure one or more FPGA devices. The AT17 Series organization supplies enough memory to configure one or multiple smaller FPGAs. The user can select the polarity of the reset function by programming internal EEPROM bytes. These devices also support a system-friendly READY pin, which signifies a “good” power level to the FPGA and can be used to ensure reliable system power-up. The AT17 Series Configurators can be programmed with industry-standard programmers or Atmel’s ATDH2200E Programming System. 2-megabit FPGA Configuration EEPROM Memory AT17C020 AT17LV020 Pin Configurations PLCC 3 NC 2 DATA 1 NC 20 VCC 19 NC CLK 4 NC 5 RESET/OE 6 NC 7 CE 8 18 NC 17 SER_EN 16 NC 15 READY 14 CEO A2 NC 9 GND 10 NC 11 NC 12 NC 13 Block Diagram CEO A2 FPGA Master Serial Mode Summary The I/O and logic functions of the FPGA and their associated interconnections are established by a configuration program. The program is loaded either automatically upon power-up, or on command, depending on the state of the FPGA mode pins. In Master Mode, the FPGA automatically loads the configuration program from an external memory. The AT17 Serial Configuration EEPROM has been designed for compatibility with the Master Serial Mode. This document discusses the AT40K FPGA interface. For more details or AT6K FPGA applications, please reference “AT40K Series Configuration” or “AT6000 Series Configuration” application notes. Controlling the Highdensity AT17 Series Serial EEPROMs During Configuration Most connections between the FPGA device and the AT17 Serial EEPROM are simple and self-explanatory • The DATA output of the AT17 Series Configurator drives DIN of the FPGA devices. • The master FPGA CCLK output drives the CLK input of the AT17 Series Configurator. • The CEO output of any AT17C/LV020 drives the CE input of the next AT17C/LV020 in a cascade chain of EEPROMs. • SER_EN must be connected to VCC, except during ISP . The READY pin is available as an open-collector indicator of the device’s RESET status it is driven Low while the device is in its POWER-ON RESET cycle and released tri-stated when the cycle is complete. There are two different ways to use the inputs CE and OE. 2 AT17C/LV020 AT17C/LV020 Condition 1 Condition 2 Cascading Serial Configuration EEPROMs AT17 Series Reset Polarity The simplest connection is to have the FPGA CON pin drive both CE and RESET/OE 1 in parallel. Due to its simplicity, however, this method will fail if the FPGA receives an external reset condition during the configuration cycle. If a system reset is applied to the FPGA, it will abort the original configuration and then reset itself for a new configuration, as intended. Of course, the AT17 Series Configurator does not see the external reset signal and will not reset its internal address counters and, consequently, will remain out of sync with the FPGA for the remainder of the configuration cycle. Note For this condition, the reset polarity of the EEPROM must be set active High. Figure Condition 2 Connection AT40K RESET RESET M2 M1 M0 D<0> CCLK CON Ordering Information - 5V Devices Memory Size 2Mb Ordering Code AT17C020-10JC AT17C020-10JI Ordering Information - 3.3V Devices Memory Size Ordering Code AT17LV020-10JC AT17LV020-10JI Package 20J Package 20J Operation Range Commercial 0°C to 70°C Industrial -40°C to 85°C Operation Range Commercial 0°C to 70°C Industrial -40°C to 85°C Package Type 20-lead, Plastic J-leaded Chip Carrier PLCC 10 AT17C/LV020 Packaging Information 20J, 20-lead, Plastic J-leaded Chip Carrier PLCC Dimensions in Inches and Millimeters AT17C/LV020 Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL 408 441-0311 FAX 408 487-2600 Europe Atmel SarL Route des Arsenaux 41 Casa Postale 80 CH-1705 Fribourg Switzerland TEL 41 26-426-5555 FAX 41 26-426-5500 Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL 852 2721-9778 FAX 852 2722-1369 Japan Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL 81 3-3523-3551 FAX 81 3-3523-7581 Atmel Configurator Hotline 408 436-4118 Atmel Configurator e-mail FAQ Available on web site Atmel Operations Atmel Colorado Springs 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 719 576-3300 FAX 719 540-1759 Atmel Rousset Zone Industrielle 13106 Rousset Cedex France TEL 33 4-4253-6000 FAX 33 4-4253-6001 Atmel Smart Card ICs Scottish Enterprise Technology Park East Kilbride, Scotland G75 0QR TEL 44 1355-357-000 FAX 44 1355-242-743 Atmel Grenoble Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex France TEL 33 4-7658-3000 FAX 33 4-7658-3480 Fax-on-Demand North America 1- 800 292-8635 International 1- 408 441-0732 e-mail Web Site BBS 1- 408 436-4309 Atmel Corporation Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. FLEX is the registered trademark of Altera Corporation. ORCA is the registered trademark of Lucent Technologies, Inc. Spartan and Virtex are the registered trademarks of Xilinx, Inc. Other terms and product names in this document may be trademarks of others. Printed on recycled paper.

PDF Datasheet Preview

• EE Reprogrammable 2,097,152 x 1 bit Serial Memories Designed to Store Configuration Programs for Field Programmable Gate Arrays FPGAs
• In-System Programmable via 2-wire Bus
• Simple Interface to SRAM FPGAs
• Compatible with Atmel AT6000, AT40K FPGAs, Altera Devices,

FPGAs, Xilinx XC3000, XC4000, XC5200, FPGAs
• Cascadable Read Back to Support Additional Configurations or

Future Higher-density Arrays
• Low-power CMOS EEPROM Process
• Programmable Reset Polarity
• Available in PLCC Package Pin Compatible across Product Family
• Emulation of Atmel’s AT24CXXX Serial EEPROMs
• Available in 3.3V ± 10% LV and 5V ± 5% C Versions
• System-friendly READY Pin
• Low-power Standby Mode

The AT17C020 and AT17LV020 high-density AT17 Series FPGA Configuration EEPROMs Configurators provide an easy-to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The AT17 Series is packaged in the popular 20-pin PLCC. The AT17 Series family uses a simple serial-access procedure to configure one or more FPGA devices. The AT17 Series organization supplies enough memory to configure one or multiple smaller FPGAs. The user can select the polarity of the reset function by programming internal EEPROM bytes. These devices also support a system-friendly READY pin, which signifies a “good” power level to the FPGA and can be used to ensure reliable system power-up.

The AT17 Series Configurators can be programmed with industry-standard programmers or Atmel’s ATDH2200E Programming System.
2-megabit FPGA Configuration EEPROM Memory

AT17C020 AT17LV020

Pin Configurations

PLCC
3 NC 2 DATA 1 NC 20 VCC 19 NC

CLK 4 NC 5

RESET/OE 6 NC 7 CE 8
18 NC 17 SER_EN 16 NC 15 READY 14 CEO A2

NC 9 GND 10

NC 11 NC 12 NC 13

Block Diagram

CEO A2

FPGA Master Serial Mode Summary

The I/O and logic functions of the FPGA and their associated interconnections are established by a configuration program. The program is loaded either automatically upon power-up, or on command, depending on the state of the FPGA mode pins. In Master Mode, the FPGA automatically loads the configuration program from an external memory. The AT17 Serial Configuration EEPROM has been designed for compatibility with the Master Serial Mode.

This document discusses the AT40K FPGA interface. For more details or AT6K FPGA applications, please reference “AT40K Series Configuration” or “AT6000 Series Configuration” application notes.

Controlling the Highdensity AT17 Series Serial EEPROMs During Configuration

Most connections between the FPGA device and the AT17 Serial EEPROM are simple and self-explanatory
• The DATA output of the AT17 Series Configurator drives DIN of the FPGA devices.
• The master FPGA CCLK output drives the CLK input of the AT17 Series

Configurator.
• The CEO output of any AT17C/LV020 drives the CE input of the next AT17C/LV020
in a cascade chain of EEPROMs.
• SER_EN must be connected to VCC, except during ISP .

The READY pin is available as an open-collector indicator of the device’s RESET status it is driven Low while the device is in its POWER-ON RESET cycle and released tri-stated when the cycle is complete.

There are two different ways to use the inputs CE and OE.
2 AT17C/LV020

AT17C/LV020

Condition 1

Condition 2

Cascading Serial Configuration EEPROMs

AT17 Series Reset Polarity

The simplest connection is to have the FPGA CON pin drive both CE and RESET/OE 1 in parallel. Due to its simplicity, however, this method will fail if the FPGA receives an external reset condition during the configuration cycle. If a system reset is applied to the FPGA, it will abort the original configuration and then reset itself for a new configuration, as intended. Of course, the AT17 Series Configurator does not see the external reset signal and will not reset its internal address counters and, consequently, will remain out of sync with the FPGA for the remainder of the configuration cycle.

Note For this condition, the reset polarity of the EEPROM must be set active High.

Figure Condition 2 Connection

AT40K

RESET

RESET

M2 M1 M0

D<0> CCLK CON
Ordering Information - 5V Devices

Memory Size 2Mb
Ordering Code AT17C020-10JC

AT17C020-10JI
Ordering Information - 3.3V Devices

Memory Size
Ordering Code

AT17LV020-10JC

AT17LV020-10JI

Package 20J

Package 20J

Operation Range Commercial 0°C to 70°C Industrial
-40°C to 85°C

Operation Range Commercial 0°C to 70°C Industrial
-40°C to 85°C

Package Type
20-lead, Plastic J-leaded Chip Carrier PLCC
10 AT17C/LV020

Packaging Information
20J, 20-lead, Plastic J-leaded Chip Carrier PLCC Dimensions in Inches and Millimeters

AT17C/LV020

Atmel Headquarters

Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL 408 441-0311 FAX 408 487-2600

Europe Atmel SarL Route des Arsenaux 41 Casa Postale 80 CH-1705 Fribourg Switzerland TEL 41 26-426-5555 FAX 41 26-426-5500

Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL 852 2721-9778 FAX 852 2722-1369

Japan Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL 81 3-3523-3551 FAX 81 3-3523-7581

Atmel Configurator Hotline 408 436-4118

Atmel Configurator e-mail

FAQ Available on web site

Atmel Operations

Atmel Colorado Springs 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 719 576-3300 FAX 719 540-1759

Atmel Rousset Zone Industrielle 13106 Rousset Cedex France TEL 33 4-4253-6000 FAX 33 4-4253-6001

Atmel Smart Card ICs Scottish Enterprise Technology Park East Kilbride, Scotland G75 0QR TEL 44 1355-357-000 FAX 44 1355-242-743

Atmel Grenoble Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex France TEL 33 4-7658-3000 FAX 33 4-7658-3480

Fax-on-Demand North America 1- 800 292-8635 International 1- 408 441-0732
e-mail

Web Site

BBS 1- 408 436-4309

Atmel Corporation Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems.

FLEX is the registered trademark of Altera Corporation.

ORCA is the registered trademark of Lucent Technologies, Inc.

Spartan and Virtex are the registered trademarks of Xilinx, Inc.

Other terms and product names in this document may be trademarks of others.

Printed on recycled paper.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived AT17LV020-10JI Datasheet file may be downloaded here without warranties.

Datasheet ID: AT17LV020-10JI 518853