CY7C1306CV25-167BZC

CY7C1306CV25-167BZC Datasheet

CY7C1303CV25 CY7C1306CV25

Part	Datasheet
CY7C1306CV25-167BZC	CY7C1306CV25-167BZC (pdf)

PDF Datasheet Preview
CY7C1303CV25 CY7C1306CV25 18-Mbit Burst of 2 Pipelined SRAM with QDR Architecture • Separate independent read and write data ports Supports concurrent transactions • 167 MHz clock for high bandwidth ns Clock-to-Valid access time • 2-word burst on all accesses • Double Data Rate DDR interfaces on both read and write ports data transferred at 333 MHz at 167 MHz • Two input clocks K and K for precise DDR timing SRAM uses rising edges only • Two input clocks for output data C and C to minimize clock skew and flight time mismatches • Single multiplexed address input bus latches address inputs for both read and write ports • Separate port selects for depth expansion • Synchronous internally self-timed writes • 2.5V core power supply with HSTL inputs and outputs • Available in 165-Ball FBGA package 13 x 15 x mm • Variable drive HSTL output buffers • Expanded HSTL output voltage • JTAG interface • Variable Impedance HSTL Configurations CY7C1303CV25 1M x 18 CY7C1306CV25 512K x 36 Functional Description The CY7C1303CV25 and CY7C1306CV25 are 2.5V Synchronous Pipelined SRAMs, equipped with QDR architecture. QDR architecture consists of two separate ports the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. QDR architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. The read address is latched on the rising edge of the K clock and the write address is latched on the rising edge of the K clock. Accesses to the QDR read and write ports are completely independent of one another. All accesses are initiated synchronously on the rising edge of the positive input clock K . To maximize data throughput, both read and write ports are provided with DDR interfaces. Therefore, data can be transferred into the device on every rising edge of both input clocks K and K and out of the device on every rising edge of the output clock C and C, or K and K when in single clock mode thereby maximizing performance while simplifying system design. Each address location is associated with two 18-bit words CY7C1303CV25 , or 36-bit words CY7C1306CV25 that burst sequentially into or out of the device. Depth expansion is accomplished with port selects, which enables each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C or K/K in a single clock domain input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. Selection Guide Maximum Operating Frequency Maximum Operating Current 167 MHz 167 500 Unit MHz mA • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback Logic Block Diagram CY7C1303CV25 CY7C1303CV25 CY7C1306CV25 D[17:0] A 18:0 19 Address Register CLK Gen. VREF WPS BWS[1:0] Control Logic Write Add. Decode Read Add. Decode Write Reg Write Reg Address Register A 18:0 512K x 18 Array 512K x 18 Array Read Data Reg. 36 18 Control Logic Reg. Reg. 18 Reg. Q[17:0] Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered. Speed MHz Ordering Code Package Diagram Package Type Operating Range 167 CY7C1303CV25-167BZC 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Commercial CY7C1306CV25-167BZC CY7C1303CV25-167BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free CY7C1306CV25-167BZXC CY7C1303CV25-167BZI 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Industrial CY7C1306CV25-167BZI CY7C1303CV25-167BZXI 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free CY7C1306CV25-167BZXI Package Diagram Figure 165-Ball FBGA 13 x 15 x mm TOP VIEW PIN 1 CORNER 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P R SEATING PLANE C MAX. C BOTTOM VIEW PIN 1 CORNER M C M C A B - 01.0665X 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R 0.15 4X NOTES SOLDER PAD TYPE NON-SOLDER MASK DEFINED NSMD PACKAGE WEIGHT 0.475g JEDEC REFERENCE MO-216 / DESIGN 4.6C PACKAGE CODE BB0AC 51-85180 *A Page 20 of 21 [+] Feedback CY7C1303CV25 CY7C1306CV25 Document History Page Document Title CY7C1303CV25/CY7C1306CV25, 18-Mbit Burst of 2 Pipelined SRAM with QDR Architecture Document Number 001-44701 ECN No. Submission Date Orig. of Change Description of Change

PDF Datasheet Preview

CY7C1303CV25 CY7C1306CV25
18-Mbit Burst of 2 Pipelined SRAM with QDR Architecture
• Separate independent read and write data ports Supports concurrent transactions
• 167 MHz clock for high bandwidth ns Clock-to-Valid access time
• 2-word burst on all accesses
• Double Data Rate DDR interfaces on both read and write ports
data transferred at 333 MHz at 167 MHz
• Two input clocks K and K for precise DDR timing

SRAM uses rising edges only
• Two input clocks for output data C and C to minimize clock
skew and flight time mismatches
• Single multiplexed address input bus latches address inputs
for both read and write ports
• Separate port selects for depth expansion
• Synchronous internally self-timed writes
• 2.5V core power supply with HSTL inputs and outputs
• Available in 165-Ball FBGA package 13 x 15 x mm
• Variable drive HSTL output buffers
• Expanded HSTL output voltage
• JTAG interface
• Variable Impedance HSTL

Configurations

CY7C1303CV25 1M x 18 CY7C1306CV25 512K x 36

Functional Description

The CY7C1303CV25 and CY7C1306CV25 are 2.5V Synchronous Pipelined SRAMs, equipped with QDR architecture. QDR architecture consists of two separate ports the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. QDR architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. The read address is latched on the rising edge of the K clock and the write address is latched on the rising edge of the K clock. Accesses to the QDR read and write ports are completely independent of one another. All accesses are initiated synchronously on the rising edge of the positive input clock K . To maximize data throughput, both read and write ports are provided with DDR interfaces. Therefore, data can be transferred into the device on every rising edge of both input clocks K and K and out of the device on every rising edge of the output clock C and C, or K and K when in single clock mode thereby maximizing performance while simplifying system design. Each address location is associated with two 18-bit words CY7C1303CV25 , or 36-bit words CY7C1306CV25 that burst sequentially into or out of the device.

Depth expansion is accomplished with port selects, which enables each port to operate independently.

All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C or K/K in a single clock domain input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

Selection Guide

Maximum Operating Frequency Maximum Operating Current
167 MHz 167 500

Unit MHz mA
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

Logic Block Diagram CY7C1303CV25

CY7C1303CV25 CY7C1306CV25

D[17:0]

A 18:0 19

Address Register

CLK Gen.

VREF WPS BWS[1:0]

Control Logic

Write Add. Decode Read Add. Decode

Write Reg

Write Reg

Address Register

A 18:0
512K x 18 Array 512K x 18 Array

Read Data Reg. 36 18

Control Logic

Reg.

Reg. 18

Reg.

Q[17:0]
Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered.

Speed MHz
Ordering Code

Package Diagram

Package Type

Operating Range
167 CY7C1303CV25-167BZC
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Commercial

CY7C1306CV25-167BZC

CY7C1303CV25-167BZXC
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free

CY7C1306CV25-167BZXC

CY7C1303CV25-167BZI
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Industrial

CY7C1306CV25-167BZI

CY7C1303CV25-167BZXI
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free

CY7C1306CV25-167BZXI

Package Diagram

Figure 165-Ball FBGA 13 x 15 x mm

TOP VIEW

PIN 1 CORNER
1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P R

SEATING PLANE C

MAX. C

BOTTOM VIEW

PIN 1 CORNER

M C M C A B - 01.0665X
11 10 9 8 7 6 5 4 3 2 1

A B C D E F G H J K L M N P R
0.15 4X

NOTES SOLDER PAD TYPE NON-SOLDER MASK DEFINED NSMD PACKAGE WEIGHT 0.475g JEDEC REFERENCE MO-216 / DESIGN 4.6C PACKAGE CODE BB0AC
51-85180 *A

Page 20 of 21 [+] Feedback

CY7C1303CV25 CY7C1306CV25

Document History Page

Document Title CY7C1303CV25/CY7C1306CV25, 18-Mbit Burst of 2 Pipelined SRAM with QDR Architecture Document Number 001-44701

ECN No.

Submission Date

Orig. of Change

Description of Change

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C1306CV25-167BZC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C1306CV25-167BZC 507946