STDP4020AD

STDP4020AD Datasheet

STDP4020, STDP4010 DisplayPort receiver

Part	Datasheet
STDP4020AD	STDP4020AD (pdf)

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STDP4020, STDP4010 DisplayPort receiver Datasheet MegaChips’ Proprietary Information MegaChips reserves the right to make any change herein at any time without prior notice. MegaChips does not assume any responsibility or liability arising out of application or use of any product or service described herein except as explicitly agreed upon. MegaChips’ Proprietary Information Page 1 of 43 STDP4020, STDP4010 • Enhanced DP receiver DP 1.1a compliant Embedded DisplayPort eDP compliant 1, 2, or 4 lanes • Higher bandwidth “Turbo mode” Gbps per lane , supports 1920 x 1080 FHD 120 Hz/10-bit color video standard timings and Ch audio 2560 x 1600 WQXGA , 2560 x 2048 QSXGA 60 Hz/10-bit color graphics and Ch audio • Interface compatibility with wide range of display controller ICs LVTTL 60 wide and LVDS quad bus video interface 8-Ch I2S and SPDIF audio interface • Robust AUX channel Link service, maintenance I2C-over-AUX MCCS, DDC IR, full duplex UART protocol • Configurable through I2C host interface • Supports HDCP with on-chip keys • HDCP repeater capability Acts as upstream receiver • AUX to I2C bridge for EDID, MCCS pass through • Spread spectrum on DisplayPort, LVDS, and TTL interfaces for EMI reduction • Supports deep color and color format conversion RGB/YUV 4:4:4 10-bit color YUV 4:2:2/4:2:0 12-bit color RGB 4:4:4 to YUV 4:4:4 conversion and vice-versa • Supports HBR/“Turbo” speed over HBR/RBRrated long cables 15 m and more • Package 164 LFBGA 12 x 12 mm / mm • Power supply voltages V I/O V core • Digital TV, LCD monitor, mobile display, projector, etc DP Input DisplayPort Receiver Bus Formatter LVDS/TTL Outputs I2S/SPDIF Transmitter I2C Host Interface Crystal Oscillator Optional GPIO I2C Master Q-LVDS/ TTL Video I2S/SPDIF Audio C4020-DAT-01p MegaChips’ Proprietary Information Page 2 of 43 Contents STDP4020, STDP4010 Description 6 Application overview 8 Feature attributes 9 BGA footprint and pin lists 10 Ball grid array diagram 10 Ordering information 41 C4020-DAT-01p MegaChips’ Proprietary Information Page 3 of 43 List of Tables STDP4020, STDP4010 Table C4020-DAT-01p MegaChips’ Proprietary Information Page 4 of 43 List of Figures STDP4020, STDP4010 Figure System interface block diagram 8 Pin diagram. 11 Package specification 28 Marking template 29 Display output port timing 35 LVDS transmitter switching characteristics. 36 I2C Timing 38 SPI output or serial interface SPI ROM input timing 39 SPI input or serial interface SPI ROM output timing 40 C4020-DAT-01p MegaChips’ Proprietary Information Page 5 of 43 STDP4020, STDP4010 The STDP4020 is a DisplayPort receiver IC for the reception of secure, high-bandwidth uncompressed digital audio-video signals targeted for applications such as DTV, LCD monitor, projector, and other types of display systems. STDP4020 is a VESA DP 1.1a and eDP compliant device, implementing a single link DisplayPort input port comprising four main lanes, auxiliary channel, and HPD. In addition to the standard HBR Gbps and RBR Gbps speeds, this device supports turbo speed of Gbps per lane with a total link bandwidth of Gbps. The higher bandwidth provides unique benefits to users over other commercial DP receivers for embedded applications by offering additional margin to support higher color depth, resolution, and refresh rate. For example, STDP4020 supports FHD nonreduced blanking video 1080p 30-bit color per pixel at 120 Hz, plus Ch audio for two-box TV applications.The advanced equalizer built in this device offers guaranteed performance over long reach cables. The auxiliary channel in STDP4020 acts as a bidirectional communication link, supporting application-specific protocols such as MCCS, DDC, UART, IR, as well as the dedicated DisplayPort link training and device management functions. The STDP4020 supports RGB and YUV video color formats with color depth of 12 YUV 4:2:2 only , 10, and 8 bits. This device offers LVDS and LVTTL output interfaces configurable to map a wide range of display controller products. The Quad LVDS interface supports video signals up to 400 MHz pixel rate with flexible channel and lane swapping options. The 60-bit LVTTL output ports can be mapped to transfer video data either in two pixels per clock or single pixel per clock up to 330 MHz pixel rate, which opens up possibilities for 3D applications. The STDP4020 also supports both compressed and uncompressed audio formats. The extracted audio signal is transferred on a digital audio output bus. This device comprises four I2S audio output, supporting up to 8 channel LPCM audio and a single wire S/PDIF output for encoded audio. The STDP4020 features the HDCP content protection scheme with an embedded key option for secure reception of digital audio-video content. In addition, it also supports the HDCP repeater function and, thus acts as an upstream receiver suitable for two-box TV and HDMI/DVI converter applications. The STDP4020 is configurable from an external host controller through I2C host interface. This IC also includes general-purpose inputs/outputs for controlling system components. The STDP4020 features a color space converter RGB to YUV and YUV to RGB for flexible interface with external video processing devices. C4020-DAT-01p MegaChips’ Proprietary Information Page 6 of 43 STDP4020, STDP4010 STDP4020 family product includes the following part numbers: Part number STDP4020 STDP4010 Video input 4 lanes DisplayPort 2 lanes DisplayPort Video output 4 Ch LVDS/60 LVTTL 2 Ch LVDS/30 LVTTL Max video resolution WQXGA/FHD 120 Hz WUXGA/FHD 60 Hz C4020-DAT-01p MegaChips’ Proprietary Information Page 7 of 43 STDP4020, STDP4010 Application overview The STDP4020 is designed as a DisplayPort front-end capture device for display applications. Typical display design has a display controller scaler that acts as system master host . The host controller configures STDP4020 through a 2-wire host interface. The host and STDP4020 also use interrupt mechanism whenever the slave needs attention. The STDP4020 may require an external SPI Flash to store firmware for supporting custom specific applications. The audio and video output from STDP4020 can directly interface to the host display controller for further processing. The AUX I2C bypass channel handles the I2C traffic between STDP4020 and host controller, as shown in the figure below. DP Connector Main Link AUX CH HPD_out Figure System interface block diagram Ordering information STDP4020-AD STDP4010-AD Table Order codes Description 164 LFBGA 12 x 12 mm 164 LFBGA 12 x 12 mm C4020-DAT-01p MegaChips’ Proprietary Information Page 41 of 43 STDP4020, STDP4010 Date 03-Mar-2016 Changes Initial release. C4020-DAT-01p MegaChips’ Proprietary Information Page 42 of 43 STDP4020, STDP4010 Notice Semiconductor products may possibly experience breakdown or malfunction. Adequate care should be taken with respect to the safety design of equipment in order to prevent the occurrence of human injury, fire or social loss in the event of breakdown or malfunction of semiconductor products The overview of operations and illustration of applications described in this document indicate the conceptual method of use of the semiconductor product and do not guarantee operability in equipment in which the product is actually used. The names of companies and trademarks stated in this document are registered trademarks of the relevant companies. MegaChips Co. provides no guarantees nor grants any implementation rights with respect to industrial property rights, intellectual property rights and other such rights belonging to third parties or/and MegaChips Co. in the use of products and of technical information including information on the overview of operations and the circuit diagrams that are described in this document. The product described in this document may possibly be considered goods or technology regulated by the Foreign Currency and Foreign Trade Control Law. In the event such law applies, export license will be required under said law when exporting the product. This regulation shall be valid in Japan domestic. In the event the intention is to use the product described in this document in applications that require an extremely high standard of reliability such as nuclear systems, aerospace equipment or medical equipment for life support, please contact the sales department of MegaChips Co. in advance. All information contained in this document is subject to change without notice. Copyright 2016 MegaChips Corporation All rights reserved MegaChips Corporation Head Quarters 1-1-1 Miyahara, Yodogawa-ku Osaka 532-0003, Japan TEL +81-6-6399-2884 MegaChips Corporation Tokyo Office 17-6 Ichiban-cho, Chiyoda-ku, Tokyo 102-0082, Japan TEL +81-3-3512-5080 MegaChips Corporation Makuhari Office 1-3 Nakase Mihama-ku Chiba 261-8501, Japan TEL +81-43-296-7414 MegaChips Corporation San Jose Office 2033 Gateway Place, Suite 400, San Jose, CA 95110 U.S.A. TEL +1-408-570-0555 MegaChips Corporation India Branch 17th Floor, Concorde Block UB City, Vittal Mallya Road, Bangalore 560-001, India TEL +91-80-4041-3999 MegaChips Corporation Taiwan Branch RM. B 2F, Worldwide House, No.129, Min Sheng E. Rd., Sec. 3, Taipei 105, Taiwan TEL +886-2-2547-1297 MegaChips Corporation Tainan Office RM. 2, 8F, No.24, Da Qiao 2 Rd., Yong Kang Dist., Tainan 710, Taiwan TEL +886-6-302-2898 MegaChips Corporation Zhunan Office No.118, Chung-Hua Rd., Chu-Nan, Miao-Li 350, Taiwan TEL +886-37-666-156 MegaChips Corporation Shenzhen Office Room 6307, Office Tower, Shun Hing Square, 5002 Shen Nan Dong Road, Luohu District, Shenzhen 518000, P. R. China TEL +86-755-3664-6990 C4020-DAT-01p MegaChips’ Proprietary Information Page 43 of 43

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STDP4020, STDP4010 DisplayPort receiver

Datasheet

MegaChips’ Proprietary Information

MegaChips reserves the right to make any change herein at any time without prior notice. MegaChips does not assume any responsibility or liability arising out of application or use of any product or service described herein except as explicitly agreed upon.

MegaChips’ Proprietary Information

Page 1 of 43

STDP4020, STDP4010
• Enhanced DP receiver DP 1.1a compliant Embedded DisplayPort eDP compliant 1, 2, or 4 lanes
• Higher bandwidth “Turbo mode” Gbps per lane , supports 1920 x 1080 FHD 120 Hz/10-bit color video standard timings and Ch audio 2560 x 1600 WQXGA , 2560 x 2048 QSXGA 60 Hz/10-bit color graphics and Ch audio
• Interface compatibility with wide range of display controller ICs LVTTL 60 wide and LVDS quad bus video interface 8-Ch I2S and SPDIF audio interface
• Robust AUX channel Link service, maintenance I2C-over-AUX MCCS, DDC IR, full duplex UART protocol
• Configurable through I2C host interface
• Supports HDCP with on-chip keys
• HDCP repeater capability Acts as upstream receiver
• AUX to I2C bridge for EDID, MCCS pass through
• Spread spectrum on DisplayPort, LVDS, and TTL interfaces for EMI reduction
• Supports deep color and color format conversion RGB/YUV 4:4:4 10-bit color YUV 4:2:2/4:2:0 12-bit color RGB 4:4:4 to YUV 4:4:4 conversion and vice-versa
• Supports HBR/“Turbo” speed over HBR/RBRrated long cables 15 m and more
• Package 164 LFBGA 12 x 12 mm / mm
• Power supply voltages V I/O V core
• Digital TV, LCD monitor, mobile display, projector, etc

DP Input

DisplayPort Receiver

Bus Formatter LVDS/TTL Outputs

I2S/SPDIF Transmitter

I2C Host Interface

Crystal Oscillator Optional

GPIO

I2C Master

Q-LVDS/ TTL Video

I2S/SPDIF Audio

C4020-DAT-01p

MegaChips’ Proprietary Information

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Contents

STDP4020, STDP4010

Description 6

Application overview 8

Feature attributes 9

BGA footprint and pin lists 10

Ball grid array diagram 10
Ordering information 41

C4020-DAT-01p

MegaChips’ Proprietary Information

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List of Tables

STDP4020, STDP4010

Table

C4020-DAT-01p

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List of Figures

STDP4020, STDP4010

Figure

System interface block diagram 8 Pin diagram. 11 Package specification 28 Marking template 29 Display output port timing 35 LVDS transmitter switching characteristics. 36 I2C Timing 38 SPI output or serial interface SPI ROM input timing 39 SPI input or serial interface SPI ROM output timing 40

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MegaChips’ Proprietary Information

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STDP4020, STDP4010

The STDP4020 is a DisplayPort receiver IC for the reception of secure, high-bandwidth uncompressed digital audio-video signals targeted for applications such as DTV, LCD monitor, projector, and other types of display systems. STDP4020 is a VESA DP 1.1a and eDP compliant device, implementing a single link DisplayPort input port comprising four main lanes, auxiliary channel, and HPD. In addition to the standard HBR Gbps and RBR Gbps speeds, this device supports turbo speed of Gbps per lane with a total link bandwidth of Gbps. The higher bandwidth provides unique benefits to users over other commercial DP receivers for embedded applications by offering additional margin to support higher color depth, resolution, and refresh rate. For example, STDP4020 supports FHD nonreduced blanking video 1080p 30-bit color per pixel at 120 Hz, plus Ch audio for two-box TV applications.The advanced equalizer built in this device offers guaranteed performance over long reach cables. The auxiliary channel in STDP4020 acts as a bidirectional communication link, supporting application-specific protocols such as MCCS, DDC, UART, IR, as well as the dedicated DisplayPort link training and device management functions.

The STDP4020 supports RGB and YUV video color formats with color depth of 12 YUV 4:2:2 only , 10, and 8 bits. This device offers LVDS and LVTTL output interfaces configurable to map a wide range of display controller products. The Quad LVDS interface supports video signals up to 400 MHz pixel rate with flexible channel and lane swapping options. The 60-bit LVTTL output ports can be mapped to transfer video data either in two pixels per clock or single pixel per clock up to 330 MHz pixel rate, which opens up possibilities for 3D applications. The STDP4020 also supports both compressed and uncompressed audio formats. The extracted audio signal is transferred on a digital audio output bus. This device comprises four I2S audio output, supporting up to 8 channel LPCM audio and a single wire S/PDIF output for encoded audio. The STDP4020 features the HDCP content protection scheme with an embedded key option for secure reception of digital audio-video content. In addition, it also supports the HDCP repeater function and, thus acts as an upstream receiver suitable for two-box TV and HDMI/DVI converter applications.

The STDP4020 is configurable from an external host controller through I2C host interface. This IC also includes general-purpose inputs/outputs for controlling system components. The STDP4020 features a color space converter RGB to YUV and YUV to RGB for flexible interface with external video processing devices.

C4020-DAT-01p

MegaChips’ Proprietary Information

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STDP4020, STDP4010

STDP4020 family product includes the following part numbers:

Part number STDP4020 STDP4010

Video input 4 lanes DisplayPort 2 lanes DisplayPort

Video output 4 Ch LVDS/60 LVTTL 2 Ch LVDS/30 LVTTL

Max video resolution WQXGA/FHD 120 Hz WUXGA/FHD 60 Hz

C4020-DAT-01p

MegaChips’ Proprietary Information

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STDP4020, STDP4010

Application overview

The STDP4020 is designed as a DisplayPort front-end capture device for display applications. Typical display design has a display controller scaler that acts as system master host . The host controller configures STDP4020 through a 2-wire host interface. The host and STDP4020 also use interrupt mechanism whenever the slave needs attention. The STDP4020 may require an external SPI Flash to store firmware for supporting custom specific applications. The audio and video output from STDP4020 can directly interface to the host display controller for further processing. The AUX I2C bypass channel handles the I2C traffic between STDP4020 and host controller, as shown in the figure below.

DP Connector

Main Link

AUX CH

HPD_out

Figure System interface block diagram
Ordering information

STDP4020-AD STDP4010-AD

Table Order codes Description
164 LFBGA 12 x 12 mm 164 LFBGA 12 x 12 mm

C4020-DAT-01p

MegaChips’ Proprietary Information

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STDP4020, STDP4010

Date 03-Mar-2016

Changes

Initial release.

C4020-DAT-01p

MegaChips’ Proprietary Information

Page 42 of 43

STDP4020, STDP4010

Notice

Semiconductor products may possibly experience breakdown or malfunction. Adequate care should be taken with respect to the safety design of equipment in order to prevent the occurrence of human injury, fire or social loss in the event of breakdown or malfunction of semiconductor products

The overview of operations and illustration of applications described in this document indicate the conceptual method of use of the semiconductor product and do not guarantee operability in equipment in which the product is actually used.

The names of companies and trademarks stated in this document are registered trademarks of the relevant companies.

MegaChips Co. provides no guarantees nor grants any implementation rights with respect to industrial property rights, intellectual property rights and other such rights belonging to third parties or/and MegaChips Co. in the use of products and of technical information including information on the overview of operations and the circuit diagrams that are described in this document.

The product described in this document may possibly be considered goods or technology regulated by the Foreign Currency and Foreign Trade Control Law. In the event such law applies, export license will be required under said law when exporting the product. This regulation shall be valid in Japan domestic.

In the event the intention is to use the product described in this document in applications that require an extremely high standard of reliability such as nuclear systems, aerospace equipment or medical equipment for life support, please contact the sales department of MegaChips Co. in advance.

All information contained in this document is subject to change without notice.

Copyright 2016 MegaChips Corporation All rights reserved

MegaChips Corporation Head Quarters 1-1-1 Miyahara, Yodogawa-ku Osaka 532-0003, Japan TEL +81-6-6399-2884

MegaChips Corporation Tokyo Office 17-6 Ichiban-cho, Chiyoda-ku, Tokyo 102-0082, Japan TEL +81-3-3512-5080

MegaChips Corporation Makuhari Office 1-3 Nakase Mihama-ku Chiba 261-8501, Japan TEL +81-43-296-7414

MegaChips Corporation San Jose Office 2033 Gateway Place, Suite 400, San Jose, CA 95110 U.S.A. TEL +1-408-570-0555

MegaChips Corporation India Branch 17th Floor, Concorde Block UB City, Vittal Mallya Road, Bangalore 560-001, India TEL +91-80-4041-3999

MegaChips Corporation Taiwan Branch RM. B 2F, Worldwide House, No.129, Min Sheng E. Rd., Sec. 3, Taipei 105, Taiwan TEL +886-2-2547-1297

MegaChips Corporation Tainan Office RM. 2, 8F, No.24, Da Qiao 2 Rd., Yong Kang Dist., Tainan 710, Taiwan TEL +886-6-302-2898

MegaChips Corporation Zhunan Office No.118, Chung-Hua Rd., Chu-Nan, Miao-Li 350, Taiwan TEL +886-37-666-156

MegaChips Corporation Shenzhen Office Room 6307, Office Tower, Shun Hing Square, 5002 Shen Nan Dong Road, Luohu District, Shenzhen 518000, P. R. China TEL +86-755-3664-6990

C4020-DAT-01p

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Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived STDP4020AD Datasheet file may be downloaded here without warranties.

Datasheet ID: STDP4020AD 647769