PAC-SYSPOWR1220AT8

PAC-SYSPOWR1220AT8 Datasheet

PAC-POWR1220AT8-EV Evaluation Board

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PAC-SYSPOWR1220AT8	PAC-SYSPOWR1220AT8 (pdf)

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PAC-POWR1220AT8-EV Evaluation Board March 2007 Application Note AN6065 Introduction Lattice Semiconductor’s Power Manager II device power supply design by integrating the analog and digital functions of power supply management sequencing, monitoring, trimming/margining, measurement into a single device. This device provides designers with a rich set of features A/D and D/A conversion, precision comparators with a built-in voltage reference, MOSFET drivers with programmable slew rates, an easy-to-use closed-loop power supply voltage trim system, and a programmable logic device PLD for sequencing and supervisory logic functions. All of these blocks can be accessed via I2C for enhanced in systems employing an on-board microcontroller. for all subsystems in the ispPAC-POWR1220AT8 device is stored in non-volatile memory. Programming is performed via the industry-standard JTAG IEEE interface. PAC-POWR1220AT8-EV Evaluation Board The PAC-POWR1220AT8-EV evaluation board Figure 1 allows the designer to quickly and evaluate the ispPAC-POWR1220AT8 device on a fully assembled printed-circuit board. The four-layer board supports a 100-pin TQFP package, pads for user I/O, a JTAG programming cable connector, and a connector for the device's I2C interface. JTAG programming signals can be generated by using an programming cable connected between the evaluation board and a PC’s parallel printer port. Both analog and digital features of the ispPACPOWR1220AT8 device can be easily using software. The actual size of the board is 5” x 4” x 10 cm . The I2C interface includes circuitry to allow the use of either an ispDOWNLOAD cable or standard open collector I2C bus. The I2C software utility that is included in PAC-Designer makes use of the ispDOWNLOAD cable interface to allow designers to evaluate the device’s I2C capabilities without having to buy additional cables or adapters. More information about this software tool can be found in application note AN6067, ispPAC-POWR1220AT8 I2C Hardware Utility Users Guide. Extra pads are provided adjacent to the I2C connector to allow the user to easily access the SDA and SCL signals as well as the regulated volt VCC supply. Connection to a standard I2C bus or cable is done simply by connecting to the SDA, SCL, and GND pins of J5 pin #3 is left Connection to an ispDOWNLOAD cable is done simply by mating the ispDOWNLOAD cable’s connector to the I2C header J5 . Figure PAC-POWR1220AT8-EV Evaluation Board 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The and information herein are subject to change without notice. an6065_01.2 Lattice Semiconductor PAC-POWR1220AT8-EV Evaluation Board Programming Interface Lattice Semiconductor’s ispDOWNLOAD cable can be used to program the ispPAC-POWR1220AT8 device on the evaluation board. This cable plugs into a PC-compatible's parallel port connector, and includes active buffer circuitry inside its DB-25 connector housing. The other end of the ispDOWNLOAD cable terminates in an 8-pin pitch header connector which plugs directly into a mating connector provided on the PAC-POWR1220AT8-EV evaluation board J4 . Power Supply Considerations Input/Output Connections Connectors are provided for key functions and test points on this evaluation board, as shown In Figure Power may be supplied in one of two ways either through two color coded RED = +, BLACK = - banana jacks in the upper right corner of the board or through a 5mm center pin + DC power connector J1 , The JTAG programming cable is connected to a keyed header J4 in the upper right corner of the board. Another header J5 provides access to the device’s I2C port. This header is pinned-out, and associated with interface circuitry so that in addition to providing a standard I2C bus connection with on-board 2K pull-ups to 3.3V , it may also be driven by the Lattice DL2download cable when the “Power Manager I2C Utility” in PAC-Designer is used. Access to a subset of the ispPAC-POWR1220AT8 device’s I/O pins is available along the left edge of the assembly, where a 2x34 block of pads supports the attachment of test probes or a ribbon-cable connector. Pads for accessing the ATDI and TDISEL signals are provided immediately below the JTAG header J4 . An auxiliary connection for OUT5/SMB Alert is provided on a pad below the I2C header J5 . Figure I/O Connections, Controls and Indicators Lattice Semiconductor PAC-POWR1220AT8-EV Evaluation Board Controls and Indicators Two momentary switches, S2 and S3, are provided on the evaluation board. They are connected to IN4 and IN5, respectively. An 8-position dipswitch S1 is provided on the evaluation board for the purpose of setting device inputs. Table 1 shows the options controlled by each switch: Table Switch S1 User Functions Position 1 2 3 4 5 6 7 8 Function when ON VPS1 Voltage Select bit 1 VPS0 Voltage Select bit 0 TDISEL IN1 IN2 IN3 VMON12_POT VMON11_POT Switch positions 1 through 6 control logic inputs. When the switch is turned ON, the corresponding logic input goes HIGH. If a logic input is to be driven from an external signal source, then its associated DIP switch should be set to the OFF position. Switch positions 1 and 2 control Voltage Select pins VPS1 and VPS0, respectively. If the device has been programmed for voltage control via VPS0 and VPS1, then these switches are used to select the active voltage Switch position 3 controls the TDI selector pin, TDISEL. This switch should be in the ON position in order to program the device through J4. Switch positions 4-6 control logic inputs IN1-IN3, respectively. When in the ON position, switches 7 and 8 connect VMON11 and VMON12 to the two linear potentiometers provided on the board. This lets the user interactively apply analog voltages to the VMON11 and VMON12 inputs without the use of additional hardware. Note that the ground-sense pins for VMON11 and VMON12 have been hardwired to ground in order to support this feature. Several red LEDs are also provided on the evaluation board to indicate proper function and as aids to debugging. LED D2 indicates that the on-board 3.3V supply is powered up. LED D3 is connected to the ispPACPOWR1220AT8 device’s TDO line, and will when downloading, indicating that download data has made it to the device. LEDs are also provided on digital outputs OUT5 through OUT20 so that a user may easily monitor the progress of sequence programs run on the evaluation board. Each of these LEDs uses a dual-resistor bias circuit that provides CMOS-3.3V compatible logic levels. Schematics The following four comprise the schematics for the ispPAC-POWR1220AT8-EV evaluation board. Figure 3 shows the on-board power-supply circuitry, Figure 4 shows the LED display and I2C adapter circuitry, Figure 5 shows user control circuits, while Figure 6 shows connections to the device itself. Lattice Semiconductor Figure On-Board Power Supply J3 +5V BANANA GND BANANA J2 BLACK Ordering Information China RoHS Environment-Friendly Ordering Part Number Use Period EFUP ispPAC Power Manager 1220AT8 Design System PAC-SYSPOWR1220AT8 Technical Support Assistance Hotline 1-800-LATTICE North America +1-503-268-8001 Outside North America e-mail Internet: March 2007 Version Change Summary Previous Lattice releases. Corrected silk screen error in the labeling of the VPS0 and VPS1 connections, located on the left side of the board at the 34 dual row set of interconnect holes. VPS1 is on the left and VPS0 is on the right. Added Ordering Information section. 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The and information herein are subject to change without notice.

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PAC-POWR1220AT8-EV Evaluation Board

March 2007

Application Note AN6065

Introduction

Lattice Semiconductor’s Power Manager II device power supply design by integrating the analog and digital functions of power supply management sequencing, monitoring, trimming/margining, measurement into a single device. This device provides designers with a rich set of features A/D and D/A conversion, precision comparators with a built-in voltage reference, MOSFET drivers with programmable slew rates, an easy-to-use closed-loop power supply voltage trim system, and a programmable logic device PLD for sequencing and supervisory logic functions. All of these blocks can be accessed via I2C for enhanced in systems employing an on-board microcontroller. for all subsystems in the ispPAC-POWR1220AT8 device is stored in non-volatile memory. Programming is performed via the industry-standard JTAG IEEE interface.

PAC-POWR1220AT8-EV Evaluation Board

The PAC-POWR1220AT8-EV evaluation board Figure 1 allows the designer to quickly and evaluate the ispPAC-POWR1220AT8 device on a fully assembled printed-circuit board. The four-layer board supports a 100-pin TQFP package, pads for user I/O, a JTAG programming cable connector, and a connector for the device's I2C interface. JTAG programming signals can be generated by using an programming cable connected between the evaluation board and a PC’s parallel printer port. Both analog and digital features of the ispPACPOWR1220AT8 device can be easily using software. The actual size of the board is 5” x 4” x 10 cm .

The I2C interface includes circuitry to allow the use of either an ispDOWNLOAD cable or standard open collector I2C bus. The I2C software utility that is included in PAC-Designer makes use of the ispDOWNLOAD cable interface to allow designers to evaluate the device’s I2C capabilities without having to buy additional cables or adapters. More information about this software tool can be found in application note AN6067, ispPAC-POWR1220AT8 I2C Hardware Utility Users Guide. Extra pads are provided adjacent to the I2C connector to allow the user to easily access the SDA and SCL signals as well as the regulated volt VCC supply. Connection to a standard I2C
bus or cable is done simply by connecting to the SDA, SCL, and GND pins of J5 pin #3 is left Connection to an ispDOWNLOAD cable is done simply by mating the ispDOWNLOAD cable’s connector to the I2C header J5 .

Figure PAC-POWR1220AT8-EV Evaluation Board
2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The and information herein are subject to change without notice.
an6065_01.2

Lattice Semiconductor

PAC-POWR1220AT8-EV Evaluation Board

Programming Interface

Lattice Semiconductor’s ispDOWNLOAD cable can be used to program the ispPAC-POWR1220AT8 device on the evaluation board. This cable plugs into a PC-compatible's parallel port connector, and includes active buffer circuitry inside its DB-25 connector housing. The other end of the ispDOWNLOAD cable terminates in an 8-pin pitch header connector which plugs directly into a mating connector provided on the PAC-POWR1220AT8-EV evaluation board J4 .

Power Supply Considerations

Input/Output Connections

Connectors are provided for key functions and test points on this evaluation board, as shown In Figure Power may be supplied in one of two ways either through two color coded RED = +, BLACK = - banana jacks in the upper right corner of the board or through a 5mm center pin + DC power connector J1 , The JTAG programming cable is connected to a keyed header J4 in the upper right corner of the board. Another header J5 provides access to the device’s I2C port. This header is pinned-out, and associated with interface circuitry so that in addition to providing a standard I2C bus connection with on-board 2K pull-ups to 3.3V , it may also be driven by the Lattice DL2download cable when the “Power Manager I2C Utility” in PAC-Designer is used.

Access to a subset of the ispPAC-POWR1220AT8 device’s I/O pins is available along the left edge of the assembly, where a 2x34 block of pads supports the attachment of test probes or a ribbon-cable connector. Pads for accessing the ATDI and TDISEL signals are provided immediately below the JTAG header J4 . An auxiliary connection for OUT5/SMB Alert is provided on a pad below the I2C header J5 .

Figure I/O Connections, Controls and Indicators

Lattice Semiconductor

PAC-POWR1220AT8-EV Evaluation Board

Controls and Indicators

Two momentary switches, S2 and S3, are provided on the evaluation board. They are connected to IN4 and IN5, respectively. An 8-position dipswitch S1 is provided on the evaluation board for the purpose of setting device inputs. Table 1 shows the options controlled by each switch:

Table Switch S1 User Functions

Position 1 2 3 4 5 6 7 8

Function when ON VPS1 Voltage Select bit 1 VPS0 Voltage Select bit 0 TDISEL IN1 IN2 IN3 VMON12_POT VMON11_POT

Switch positions 1 through 6 control logic inputs. When the switch is turned ON, the corresponding logic input goes HIGH. If a logic input is to be driven from an external signal source, then its associated DIP switch should be set to the OFF position.

Switch positions 1 and 2 control Voltage Select pins VPS1 and VPS0, respectively. If the device has been programmed for voltage control via VPS0 and VPS1, then these switches are used to select the active voltage

Switch position 3 controls the TDI selector pin, TDISEL. This switch should be in the ON position in order to program the device through J4.

Switch positions 4-6 control logic inputs IN1-IN3, respectively.

When in the ON position, switches 7 and 8 connect VMON11 and VMON12 to the two linear potentiometers provided on the board. This lets the user interactively apply analog voltages to the VMON11 and VMON12 inputs without the use of additional hardware. Note that the ground-sense pins for VMON11 and VMON12 have been hardwired to ground in order to support this feature.

Several red LEDs are also provided on the evaluation board to indicate proper function and as aids to debugging. LED D2 indicates that the on-board 3.3V supply is powered up. LED D3 is connected to the ispPACPOWR1220AT8 device’s TDO line, and will when downloading, indicating that download data has made it to the device.

LEDs are also provided on digital outputs OUT5 through OUT20 so that a user may easily monitor the progress of sequence programs run on the evaluation board. Each of these LEDs uses a dual-resistor bias circuit that provides CMOS-3.3V compatible logic levels.

Schematics

The following four comprise the schematics for the ispPAC-POWR1220AT8-EV evaluation board. Figure 3 shows the on-board power-supply circuitry, Figure 4 shows the LED display and I2C adapter circuitry, Figure 5 shows user control circuits, while Figure 6 shows connections to the device itself.

Lattice Semiconductor

Figure On-Board Power Supply

J3 +5V BANANA

GND BANANA J2 BLACK
Ordering Information

China RoHS Environment-Friendly
Ordering Part Number

Use Period EFUP
ispPAC Power Manager 1220AT8 Design System

PAC-SYSPOWR1220AT8

Technical Support Assistance

Hotline 1-800-LATTICE North America +1-503-268-8001 Outside North America
e-mail Internet:

March 2007

Version

Change Summary

Previous Lattice releases.

Corrected silk screen error in the labeling of the VPS0 and VPS1 connections, located on the left side of the board at the 34 dual row set of interconnect holes. VPS1 is on the left and VPS0 is on the right.
Added Ordering Information section.
2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The and information herein are subject to change without notice.

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Datasheet ID: PAC-SYSPOWR1220AT8 645497