MM74C32N

MM74C32N Datasheet

MM74C32 Quad 2-Input OR Gate

Part	Datasheet
MM74C32N	MM74C32N (pdf)

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MM74C32 Quad 2-Input OR Gate MM74C32 Quad 2-Input OR Gate The MM74C32 employs complementary MOS CMOS transistors to achieve low power and high noise margin, these gates provide the basic functions used in the implementation of digital integrated circuit systems. The N- and P-channel enhancement mode transistors provide a symmetrical circuit with output swings essentially equal to the supply voltage. This results in high noise immunity over a wide supply voltage range. No DC power other than that caused by leakage current is consumed during static conditions. All inputs are protected against static discharge damage. s Wide supply voltage range 3.0V to 15V s Guaranteed noise margin 1.0V s High noise immunity 0.45V VCC typ. s Low power TTL compatibility fan out of 2 driving 74L Ordering Code: Order Number Package Number Package Description MM74C32N N14A 14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Connection Diagram Top View 2004 Fairchild Semiconductor Corporation DS005881 MM74C32 Absolute Maximum Ratings Note 1 Voltage at Any Pin Operating Temperature Range Storage Temperature Range Power Dissipation PD Dual-In-Line Small Outline Operating VCC Range −0.3V to VCC + 0.3V −55°C to +125°C −65°C to +150°C 700 mW 500 mW 3.0V to 15V Absolute Maximum VCC Lead Temperature Soldering, 10 seconds 260°C Note 1 “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The Electrical Characteristics table provides conditions for actual device operation. DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise noted Parameter Conditions CMOS TO CMOS VIN 1 Logical “1” Input Voltage VIN 0 Logical “0” Input Voltage VOUT 1 Logical “1” Output Voltage VOUT 0 Logical “0” Output Voltage IIN 1 Logical “1” Input Current IIN 0 Logical “0” Input Current Supply Current CMOS/LPTTL INTERFACE VCC = 5.0V VCC = 10V VCC = 5.0V VCC = 10V VCC = 5.0V, IO = −10 µA VCC = 10V, IO = −10 µA VCC = 5.0V, IO = 10 µA VCC = 10V, IO = 10 µA VCC = 15V, VIN = 15V VCC = 15V, VIN = 0V VCC = 15V VIN 1 VIN 0 VOUT 1 VOUT 0

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MM74C32 Quad 2-Input OR Gate

MM74C32 Quad 2-Input OR Gate

The MM74C32 employs complementary MOS CMOS transistors to achieve low power and high noise margin, these gates provide the basic functions used in the implementation of digital integrated circuit systems. The N- and P-channel enhancement mode transistors provide a symmetrical circuit with output swings essentially equal to the supply voltage. This results in high noise immunity over a wide supply voltage range. No DC power other than that caused by leakage current is consumed during static conditions. All inputs are protected against static discharge damage.
s Wide supply voltage range 3.0V to 15V s Guaranteed noise margin 1.0V s High noise immunity 0.45V VCC typ. s Low power TTL compatibility fan out of 2 driving 74L
Ordering Code:

Order Number Package Number

Package Description

MM74C32N

N14A
14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide

Connection Diagram

Top View
2004 Fairchild Semiconductor Corporation DS005881

MM74C32

Absolute Maximum Ratings Note 1

Voltage at Any Pin Operating Temperature Range Storage Temperature Range Power Dissipation PD

Dual-In-Line Small Outline Operating VCC Range
−0.3V to VCC + 0.3V −55°C to +125°C −65°C to +150°C
700 mW 500 mW 3.0V to 15V

Absolute Maximum VCC

Lead Temperature

Soldering, 10 seconds
260°C

Note 1 “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The Electrical Characteristics table provides conditions for actual device operation.

DC Electrical Characteristics

Min/Max limits apply across temperature range unless otherwise noted

Parameter

Conditions

CMOS TO CMOS

VIN 1

Logical “1” Input Voltage

VIN 0

Logical “0” Input Voltage

VOUT 1

Logical “1” Output Voltage

VOUT 0

Logical “0” Output Voltage

IIN 1

Logical “1” Input Current

IIN 0

Logical “0” Input Current

Supply Current

CMOS/LPTTL INTERFACE

VCC = 5.0V VCC = 10V VCC = 5.0V VCC = 10V VCC = 5.0V, IO = −10 µA VCC = 10V, IO = −10 µA VCC = 5.0V, IO = 10 µA VCC = 10V, IO = 10 µA VCC = 15V, VIN = 15V VCC = 15V, VIN = 0V VCC = 15V

VIN 1 VIN 0 VOUT 1 VOUT 0

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Datasheet ID: MM74C32N 634350