HSP-EVAL

HSP-EVAL Datasheet

HSP-EVAL

Part	Datasheet
HSP-EVAL	HSP-EVAL (pdf)

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USER’S MANUAL HSP-EVAL May 1999 File Number DSP Evaluation Platform The HSP-EVAL is the mother board for a set of daughter boards based on the family of Digital Signal Processing products. Each product daughter board is mated with the HSP-EVAL to provide a mechanism for rapid evaluation and prototyping. As shown in Figure 1, the HSP-EVAL consists of a series of busses which provide input, output, and control to the target daughter board. These busses are brought out through dual 96 Pin connectors to support daisy chaining HSP-EVALs for multichip prototyping and evaluation. For added the input and control busses can be driven by registers on-board the HSP-EVAL which have been down loaded with data via the parallel port of an IBM PCTM or compatible. In addition, a Shift Register is provided to serialize data on the daughter board output busses for reading into the PC via the status lines of the parallel port. Together, the I/O and Control Registers can be used to drive the target daughter board with a PC based vector set while collecting daughter board outputs to the PC’s disk. Jumper selectable clock sources provide three different methods of clocking the part under evaluation. In mode one, the clock signal is generated under PC based software control. In mode two, the HSP-EVAL’s on-board oscillator may be selected as the clock source. In mode three, the user may provide an external clock through the 96 Pin Input Connector. The HSP-EVAL was built into a 3U Euro-Card form factor with dual 96 Pin Input/Output connectors. The I/O connectors conform to the VME J2/P2 connector standard. DSP Evaluation Platform • Single HSP-EVAL May be Used to Evaluate a Variety of Parts Within the Family of DSP Products • May be Daisy Chained to Support Evaluation of Multi-Chip Solutions • Parallel Port Interface to Support IBM PC Based Evaluation and Control • Three Clocking Modes for Flexibility in Performance Analysis and Prototyping • Dual 96-Pin Input/Output Connectors Conforming to the VME J2/P2 Connector Standard • PC Based Performance Analysis of Family of DSP Products • Rapid Prototyping CAUTION These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 \| Copyright Intersil Corporation 2000 IBM PC is a trademark of IBM Corporation. HSP-EVAL Getting Started The HSP-EVAL was designed to operate in conjunction with daughter boards designed for the family of DSP products. A simple procedure for assembly and operation of the target daughter board with the HSP-EVAL is described in the respective daughter board’s User’s Manual. What follows in this document is a detailed description of the HSP-EVAL and its operation. Bus Structure The HSP-EVAL utilizes a series of 16-bit busses for daughter board input, output and control as shown in Figure The input and output busses interface the daughter board to the outside world through 96 Pin DIN connectors conforming to the VME J2/P2 connector standard. Daughter board control is provided by register driven control busses down loaded with data via the parallel port of a PC. For added flexibility, the input busses may also be register driven with down loaded data. Two input busses, IN1_0-15 and IN2_0-15, bring data from the 96 Pin DIN connector P1 to the daughter board through the 50 position Input Connector J1 . Each input bus is 16 bits wide and the signal mapping for the above connectors is given in Tables 1 and As an alternative, the input busses may be driven by registers which have been down loaded with data through the Parallel Port Bus. Two output busses, OUT1_0-15 and OUT2_0-15, carry daughter board output from the 50 Pin Output Connector J2 to the 96 Pin DIN connector P2 . Each output bus is 16 bits wide and the signal mapping for the above connectors is given in Tables 2 and A shift register is provided to serialize data on the output busses for transmission via the Parallel Port Bus. A status bus, STAT0-3, maps four status outputs from the daughter board Output Connector J2 to the Jumper Field J4 . The Jumper Field is used to select one of the four status lines for transmission via the Parallel Port Bus see Jumper Field Section . The two control busses, IN3_0-15 and CTL0-15, connect a set of registers to the 50 Pin Control Connector J3 . Each control bus is 16 bits wide and the signal mapping for the J3 Control Connector is shown in Table The four least bits of the CTL0-15 bus are also used to control the operation of the HSP-EVAL see Register Structure Section . As with the registers driving the input busses, the registers driving the control busses are down loaded with data via the Parallel Port Bus. Parallel Port Bus The Parallel Port Bus carries the data and signals required to support bidirectional data transfers between the HSPEVAL and the parallel port of an IBM PC or compatible. The port bus contains eight data lines, PCD0-7, two control lines, PCWR0-1, and three serial output lines, PCRD0-2. The control and data lines are used to down load data into the HSPEVAL's on board registers via the Parallel Port Interface. The serial output lines carry daughter board status and output serialized by the On Board Shift Register. 96 PIN INPUT CONNECTOR P1 INPUT CONNECTOR J1 INPUT BUS 3 IN3_0-15 CTL BUS CTL0-15 STAT0-3 96 PIN OUTPUT CONNECTOR P2 OUTPUT CONNECTOR J2 INPUT BUS 1 IN1_0-15 INPUT BUS 2 IN2_0-15 CLK IN INPUT REG 1 INPUT REG 2

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USER’S MANUAL

HSP-EVAL

May 1999 File Number

DSP Evaluation Platform

The HSP-EVAL is the mother board for a set of daughter boards based on the family of Digital Signal Processing products. Each product daughter board is mated with the HSP-EVAL to provide a mechanism for rapid evaluation and prototyping. As shown in Figure 1, the HSP-EVAL consists of a series of busses which provide input, output, and control to the target daughter board. These busses are brought out through dual 96 Pin connectors to support daisy chaining HSP-EVALs for multichip prototyping and evaluation.

For added the input and control busses can be driven by registers on-board the HSP-EVAL which have been down loaded with data via the parallel port of an IBM PCTM or compatible. In addition, a Shift Register is provided to serialize data on the daughter board output busses for reading into the PC via the status lines of the parallel port. Together, the I/O and Control Registers can be used to drive the target daughter board with a PC based vector set while collecting daughter board outputs to the PC’s disk.

Jumper selectable clock sources provide three different methods of clocking the part under evaluation. In mode one, the clock signal is generated under PC based software control. In mode two, the HSP-EVAL’s on-board oscillator may be selected as the clock source. In mode three, the user may provide an external clock through the 96 Pin Input Connector.

The HSP-EVAL was built into a 3U Euro-Card form factor with dual 96 Pin Input/Output connectors. The I/O connectors conform to the VME J2/P2 connector standard.

DSP Evaluation Platform
• Single HSP-EVAL May be Used to Evaluate a Variety of Parts Within the Family of DSP Products
• May be Daisy Chained to Support Evaluation of Multi-Chip Solutions
• Parallel Port Interface to Support IBM PC Based Evaluation and Control
• Three Clocking Modes for Flexibility in Performance Analysis and Prototyping
• Dual 96-Pin Input/Output Connectors Conforming to the VME J2/P2 Connector Standard
• PC Based Performance Analysis of Family of DSP Products
• Rapid Prototyping

CAUTION These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 2000

IBM PC is a trademark of IBM Corporation.

HSP-EVAL

Getting Started

The HSP-EVAL was designed to operate in conjunction with daughter boards designed for the family of DSP products. A simple procedure for assembly and operation of the target daughter board with the HSP-EVAL is described in the respective daughter board’s User’s Manual. What follows in this document is a detailed description of the HSP-EVAL and its operation.

Bus Structure

The HSP-EVAL utilizes a series of 16-bit busses for daughter board input, output and control as shown in Figure The input and output busses interface the daughter board to the outside world through 96 Pin DIN connectors conforming to the VME J2/P2 connector standard. Daughter board control is provided by register driven control busses down loaded with data via the parallel port of a PC. For added flexibility, the input busses may also be register driven with down loaded data.

Two input busses, IN1_0-15 and IN2_0-15, bring data from the 96 Pin DIN connector P1 to the daughter board through the 50 position Input Connector J1 . Each input bus is 16 bits wide and the signal mapping for the above connectors is given in Tables 1 and As an alternative, the input busses may be driven by registers which have been down loaded with data through the Parallel Port Bus.

Two output busses, OUT1_0-15 and OUT2_0-15, carry daughter board output from the 50 Pin Output Connector

J2 to the 96 Pin DIN connector P2 . Each output bus is 16 bits wide and the signal mapping for the above connectors is given in Tables 2 and A shift register is provided to serialize data on the output busses for transmission via the Parallel Port Bus.

A status bus, STAT0-3, maps four status outputs from the daughter board Output Connector J2 to the Jumper Field J4 . The Jumper Field is used to select one of the four status lines for transmission via the Parallel Port Bus see Jumper Field Section .

The two control busses, IN3_0-15 and CTL0-15, connect a set of registers to the 50 Pin Control Connector J3 . Each control bus is 16 bits wide and the signal mapping for the J3 Control Connector is shown in Table The four least bits of the CTL0-15 bus are also used to control the operation of the HSP-EVAL see Register Structure Section . As with the registers driving the input busses, the registers driving the control busses are down loaded with data via the Parallel Port Bus.

Parallel Port Bus

The Parallel Port Bus carries the data and signals required to support bidirectional data transfers between the HSPEVAL and the parallel port of an IBM PC or compatible. The port bus contains eight data lines, PCD0-7, two control lines, PCWR0-1, and three serial output lines, PCRD0-2. The control and data lines are used to down load data into the HSPEVAL's on board registers via the Parallel Port Interface. The serial output lines carry daughter board status and output serialized by the On Board Shift Register.
96 PIN INPUT CONNECTOR P1 INPUT CONNECTOR J1 INPUT BUS 3 IN3_0-15 CTL BUS CTL0-15

STAT0-3
96 PIN OUTPUT CONNECTOR P2 OUTPUT CONNECTOR J2

INPUT BUS 1

IN1_0-15

INPUT BUS 2

IN2_0-15

CLK IN

INPUT REG 1

INPUT REG 2

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Datasheet ID: HSP-EVAL 639144