GCIXP1250BA

GCIXP1250BA Datasheet


i GCIXP1250xx INTEL M C 2001

Part Datasheet
GCIXP1250BA GCIXP1250BA GCIXP1250BA (pdf)
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IXP1250 Network Processor

Product Features

Datasheet

The IXP1250 Network Processor delivers high-performance processing power and flexibility to a wide variety of LAN and telecommunications products. Distinguishing features of the IXP1250 are the performance of ASIC hardware along with programmability of a microprocessor.
s Applications
s Industry Standard 64-bit SDRAM Interface

Multi-layer LAN Switches

Peak bandwidth of up to 928 Mbytes/sec

Multi-protocol Telecommunications Products Address up to 256 Mbytes of SDRAM

Broadband Cable Products

Memory bandwidth improvement through

Remote Access Devices
bank switching

Intelligent PCI adapters

Read-modify-write support
s Integrated StrongARM* Core High-performance, low-power, 32-bit

Embedded RISC processor

Byte aligner/merger Cyclic Redundancy Check CRC Error Correction Code ECC
16 Kbyte instruction cache
s Industry Standard 32-bit SRAM Interface
8 Kbyte data cache

Peak bandwidth of up to 464 Mbytes/sec
512 byte mini-cache for data that is used once Address up to 8 Mbytes of SRAM
and then discarded

Up to 8 Mbytes FlashROM for booting

Write buffer

StrongARM Core

Memory management unit

Supports atomic push/pop operations

Access to IXP1250 FBI Unit, PCI Unit and

Supports atomic bit set and bit clear

SDRAM Unit via the ARM* AMBA Bus
operations
s Six Integrated Programmable Microengines Operating frequency of up to 232 MHz

Memory bandwidth imporvement by reduced read/write turnaround bus cycles

Multi-thread support of four threads per
s Other Integrated Features
microengine

Hardware Hash Unit for generation of 48- or

Single-cycle ALU and shift operations
64-bit adaptive polynomial hash keys
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at

Copyright Intel Corporation, 2001 Intel is a registered trademark of Intel Corporation or its subsidiaries in the United States and other countries *Other names and brands may be claimed as the property of others.

Datasheet

IXP1250 Network Processor

Contents

Product Description 9

Functional

Conventions StrongARM* Core Microprocessor Microengines FBI Unit and the IX

IX Bus Access Behavior Reset and Idle Bus Considerations

SDRAM and SRAM SDRAM Unit SDRAM Bus Access Behavior SDRAM Cyclic Redundancy Checking CRC SDRAM Error Correction Code ECC SDRAM Configurations SRAM Types SRAM Configurations BootROM Configurations SRAM Bus Access Behavior

PCI Unit PCI Arbitration and Central Function Support

Device Reset Hardware Initiated Software Initiated Reset PCI Initiated Reset Watchdog Timer Initiated Reset

Signal Description

Pinout Pin Type Legend Pin Description, Grouped by

Processor Support SRAM Interface Pins SDRAM Interface Pins IX Bus Interface General Purpose Serial Port UART Pins PCI Interface Pins Power Supply Pins IEEE Interface Pins Miscellaneous Test Pin Usage Summary Pin/Signal Signals Listed in Alphabetical Order IX Bus Pins Function Listed by Operating IX Bus Decode Table Listed by Operating Mode Type

Datasheet

IXP1250 Network Processor

Pin State During 65 Pullup/Pulldown and Unused Pin Guidelines 67

Electrical Specifications 68

Absolute Maximum Ratings 68 DC 71

Type 1 Driver DC Specifications 71 Type 2 Driver DC Specifications 72 Overshoot/Undershoot Specifications 72 AC Specifications 73 Clock Timing Specifications 73 PXTAL Clock 73 PXTAL Clock Oscillator 74 PCI 74

PCI Electrical Specification 74 PCI Clock Signal AC Parameter Measurements....................... 74 PCI Bus Signals 76 77 Reset Timings Specification 77 IEEE 78 IEEE Timing Specifications 79 IX 81 FCLK Signal AC Parameter 81 IX Bus Signals Timing 82 IX Bus 84 118 TK_IN/TK_OUT 120 SRAM Interface 121 SRAM SCLK Signal AC Parameter Measurements 121 SRAM Bus Signal Timing 122 SRAM Bus - SRAM Signal Protocol and Timing 124 SRAM Bus - BootROM and SlowPort Timings........................ 129 SRAM Bus - BootRom Signal Protocol and Timing................. 129 SRAM Bus - Slow-Port Device Signal Protocol and Timing 132 SDRAM Interface 136 SDCLK AC Parameter 136 SDRAM Bus Signal Timing 137 SDRAM Signal Protocol 138 Asynchronous Signal Timing 143

Mechanical 144

Package Dimensions 144 IXP1250 Package Dimensions mm 147

Figures
1 2 3 4 5

Silicon Block Diagram 9 System Block 10 SDRAM Unit Block Diagram 16 SRAM Unit Block Diagram 19 Reset Logic 24

Datasheet

IXP1250 Network Processor

Pinout
64-Bit Bidirectional IX Bus, 1-2 MAC
64-Bit Bidirectional IX Bus, 1-2 MAC Mode, FastPort Device
64-Bit Bidirectional IX Bus, 3+ MAC
10 32-Bit Unidirectional IX Bus, 1-2 MAC Mode
11 32-bit Unidirectional IX Bus, 3+ MAC Mode 3-4 MACs Supported
12 Typical IXP1250 Heatsink
13 PXTAL Clock Input
14 PCI Clock Signal AC Parameter
15 PCI Bus Signals
16 RESET_IN_L Timing Diagram
17 IEEE 1149.1/Boundary-Scan General
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Datasheet ID: GCIXP1250BA 638949