IS25WP016-JBLE-TR

IS25WP016-JBLE-TR Datasheet

IS25WP016 IS25WP080 IS25WP040 IS25WP020

Part	Datasheet
IS25WP016-JBLE-TR	IS25WP016-JBLE-TR (pdf)

Related Parts	Information
IS25WP016-JNLE	IS25WP016-JNLE
IS25WP016-JBLE	IS25WP016-JBLE
IS25WP016-JNLE-TR	IS25WP016-JNLE-TR

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IS25WP016 IS25WP080 IS25WP040 IS25WP020 16/8/4/2MBIT 1.8V SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE PRELIMINARY DATA SHEET 16/8/4/2MBIT 1.8V SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE IS25WP016/080/040/020 PRELIMINARY INFORMATION • Industry Standard Serial Interface - IS25WP016 16Mbit/2Mbyte - IS25WP080 8Mbit/1Mbyte - IS25WP040 4Mbit/512Kbyte - IS25WP020 2Mbit/256Kbyte - 256 bytes per Programmable Page - Supports standard SPI, Fast, Dual, Dual I/O, Quad, Quad I/O, SPI DTR, Dual I/O DTR, Quad I/O DTR, and QPI - Supports Serial Flash Discoverable Parameters SFDP • High Performance Serial Flash SPI - 50MHz Normal and 133Mhz Fast Read - 532 MHz equivalent QPI - DTR Dual Transfer Rate up to 66MHz - Selectable Dummy Cycles - Configurable Drive Strength - Supports SPI Modes 0 and 3 - More than 100,000 Erase/Program cycles - More than 20-year Data Retention • Flexible & Efficient Memory Architecture - Chip Erase with Uniform Sector/Block Erase 4/32/64 Kbyte - Program 1 to 256 Bytes per Page - Program/Erase Suspend & Resume • Efficient Read and Program modes - Low Instruction Overhead Operations - Continuous Read 8/16/32/64-Byte Burst Wrap - Selectable Burst Length - QPI for Reduced Instruction Overhead - AutoBoot Operation • Low Power with Wide Temp. Ranges - Single 1.65V to 1.95V Voltage Supply - 10 mA Active Read Current typ. - 8 µA Standby Current typ. - 1 µA Deep Power Down typ. - Temp Grades Extended -40°C to +105°C Extended+ -40°C to +125°C Auto Grade up to +125°C Note Extended+ should not be used for Automotive. • Advanced Security Protection - Software and Hardware Write Protection - Power Supply Lock Protection - 4x256-Byte Dedicated Security Area with OTP User-lockable Bits - 128 bit Unique ID for Each Device Call Factory • Industry Standard Pin-out & Packages 1 , 2 - M =16-pin SOIC 300mil 3 - B = 8-pin SOIC 208mil - N = 8-pin SOIC 150mil - D = 8-pin TSSOP - V = 8-pin VVSOP 150mil - F = 8-pin VSOP 208mil - K = 8-contact WSON 6x5mm - T = 8-contact USON 4x3mm - U = 8-contact USON 2x3mm - G = 24-ball TFBGA 6x8mm 3 - KGD Call Factory Notes IS25WP016 not available in D and IS25WP080/040 not available in M, D, G and IS25WP020 not available in M, F, T, G Call Factory for WLCSP or other package options available For the dedicated RESET# pin option, see the Ordering Information Integrated Silicon Solution, Inc.- 09/24/2015 IS25WP016/080/040/020 The IS25WP016/080/040/020 Serial Flash memory offers a versatile storage solution with high flexibility and performance in a simplified pin count package. ISSI’s “Industry Standard Serial Interface” Flash is for systems that require limited space, a low pin count, and low power consumption. The device is accessed through a 4wire SPI Interface consisting of a Serial Data Input SI , Serial Data Output SO , Serial Clock SCK , and Chip Enable CE# pins, which can also be configured to serve as multi-I/O see pin descriptions . The device supports Dual and Quad I/O as well as standard, Dual Output, and Quad Output SPI. Clock frequencies of up to 133MHz allow for equivalent clock rates of up to 532MHz 133MHz x 4 which equates to 66Mbytes/s of data throughput. The IS25xP series of Flash adds support for DTR Double Transfer Rate commands that transfer addresses and read data on both edges of the clock. These transfer rates can outperform 16-bit Parallel Flash memories allowing for efficient memory access to support XIP execute in place operation. The memory array is organized into programmable pages of 256-bytes. This family supports page program mode where 1 to 256 bytes of data are programmed in a single command. QPI Quad Peripheral Interface supports 2-cycle instruction further reducing instruction times. Pages can be erased in groups of 4Kbyte sectors, 32Kbyte blocks, 64Kbyte blocks, and/or the entire chip. The uniform sector and block architecture allows for a high degree of flexibility so that the device can be utilized for a broad variety of applications requiring solid data retention. GLOSSARY Standard SPI In this operation, a 4-wire SPI Interface is utilized, consisting of Serial Data Input SI , Serial Data Output SO , Serial Clock SCK , and Chip Enable CE# pins. Instructions are sent via the SI pin to encode instructions, addresses, or input data to the device on the rising edge of SCK. The SO pin is used to read data or to check the status of the device. This device supports SPI bus operation modes 0,0 and Mutil I/O SPI Multi-I/O operation utilizes an enhanced SPI protocol to allow the device to function with Dual Output, Dual Input and Output, Quad Output, and Quad Input and Output capability. Executing these instructions through SPI mode will achieve double or quadruple the transfer bandwidth for READ and PROGRAM operations. QPI The device supports Quad Peripheral Interface QPI operations only when the device is switched from Standard/Dual/Quad SPI mode to QPI mode using the enter QPI 35h instruction. The typical SPI protocol requires that the byte-long instruction code being shifted into the device only via SI pin in eight serial clocks. The QPI mode utilizes all four I/O pins to input the instruction code thus requiring only two serial clocks. This can significantly reduce the SPI instruction overhead and improve system performance. Only QPI mode or SPI/Dual/Quad mode can be active at any given time. Enter QPI 35h and Exit QPI F5h instructions are used to switch between these two modes, regardless of the non-volatile Quad Enable QE bit status in the Status Register. Power Reset or Hardware/Software Reset will return the device into the standard SPI mode. SI and SO pins become bidirectional I/O0 and I/O1, and WP# and HOLD# pins become I/O2 and I/O3 respectively during QPI mode. DTR In addition to SPI and QPI features, the device also supports Fast READ DTR operation. DTR operation allows high data throughput while running at lower clock frequencies. Fast READ DTR operation uses both rising and falling edges of the clock for address inputs, and data outputs, resulting in reducing input and output cycles by half. Integrated Silicon Solution, Inc.- 09/24/2015 IS25WP016/080/040/020 TABLE OF CONTENTS FEATURES GENERAL DESCRIPTION TABLE OF CONTENTS PIN DESCRIPTIONS BLOCK DIAGRAM SPI MODES DESCRIPTION SYSTEM CONFIGURATION BLOCK/SECTOR ADDRESSES REGISTERS STATUS REGISTER FUNCTION REGISTER READ REGISTER AND EXTENDED AUTOBOOT REGISTER PROTECTION HARDWARE WRITE SOFTWARE WRITE PROTECTION DEVICE OPERATION NORMAL READ OPERATION NORD, 03h FAST READ OPERATION FRD, 0Bh HOLD FAST READ DUAL I/O OPERATION FRDIO, BBh FAST READ DUAL OUTPUT OPERATION FRDO, FAST READ QUAD OUTPUT OPERATION FRQO, FAST READ QUAD I/O OPERATION FRQIO, EBh PAGE PROGRAM OPERATION PP, QUAD INPUT PAGE PROGRAM OPERATION PPQ, 32h/38h ERASE OPERATION SECTOR ERASE OPERATION SER, BLOCK ERASE OPERATION BER32K:52h, BER64K:D8h CHIP ERASE OPERATION CER, C7h/60h WRITE ENABLE OPERATION WREN, 06h WRITE DISABLE OPERATION WRDI, READ STATUS REGISTER OPERATION RDSR, 05h WRITE STATUS REGISTER OPERATION WRSR, READ FUNCTION REGISTER OPERATION RDFR, 48h WRITE FUNCTION REGISTER OPERATION WRFR, ENTER QUAD PERIPHERAL INTERFACE QPI MODE OPERATION QPIEN, 35h QPIDI, F5h 54 Integrated Silicon Solution, Inc.- 09/24/2015 IS25WP016/080/040/020 PROGRAM/ERASE SUSPEND & ENTER DEEP POWER DOWN DP, B9h RELEASE DEEP POWER DOWN RDPD, ABh SET READ PARAMETERS OPERATION SRPNV 65h, SRPV C0h/63h SET EXTENDED READ PARAMETERS OPERATION SERPNV 85h, SERPV 83h READ PARAMETERS OPERATION RDRPNV, 61h READ EXTENDED READ PARAMETERS OPERATION RDRPNV, 81h READ PRODUCT IDENTIFICATION RDID, ABh READ PRODUCT IDENTIFICATION BY JEDEC ID OPERATION RDJDID, 9Fh RDJDIDQ, AFh 66 READ DEVICE MANUFACTURER AND DEVICE ID OPERATION RDMDID, 90h READ UNIQUE ID NUMBER RDUID, 4Bh READ SFDP OPERATION RDSFDP, 5Ah NO OPERATION NOP, 00h SOFTWARE RESET-ENABLE RSTEN, 66h AND RESET RST, 99h AND HARDWARE RESET SECURITY INFORMATION ROW ERASE OPERATION IRER, 64h INFORMATION ROW PROGRAM OPERATION IRP, 62h INFORMATION ROW READ OPERATION IRRD, 68h FAST READ DTR MODE OPERATION FRDTR, FAST READ DUAL IO DTR MODE OPERATION FRDDTR, BDh FAST READ QUAD IO DTR MODE OPERATION FRQDTR, EDh SECTOR LOCK/UNLOCK FUNCTIONS ELECTRICAL ABSOLUTE MAXIMUM RATINGS 1 OPERATING RANGE DC AC MEASUREMENT CONDITIONS PIN CAPACITANCE TA = 25°C, VCC=1.8V, 1MHz AC SERIAL INPUT/OUTPUT POWER-UP AND POWER-DOWN PROGRAM/ERASE PERFORMANCE RELIABILITY CHARACTERISTICS PACKAGE TYPE 8-Pin JEDEC 208mil Broad Small Outline Integrated Circuit SOIC Package B 8-Pin JEDEC 150mil Broad Small Outline Integrated Circuit SOIC Package N 8-Pin TSSOP Package D 8-Pin 150mil VVSOP Package Integrated Silicon Solution, Inc.- 09/24/2015 IS25WP016/080/040/020 8-Contact Ultra-Thin Small Outline No-Lead WSON Package 6x5mm 8-Contact Ultra-Thin Small Outline No-Lead USON Package 4x3mm 8-Contact Ultra-Thin Small Outline No-Lead USON Package 2x3mm U 8-Pin 208mil VSOP Package F 16-lead Plastic Small Outline package 300 mils body width M 24-Ball Thin Profile Fine Pitch BGA 6x8mm ORDERING INFORMATION - Valid Part Integrated Silicon Solution, Inc.- 09/24/2015 PIN CONFIGURATION IS25WP016/080/040/020 SO IO1 WP# IO2 CE# 1 HOLD# or 1 RESET# IO3 SO IO1 2 SI IO0 WP# IO2 3 GND 4 8 Vcc HOLD# or 1 RESET# IO3 6 SCK 5 SI IO0 8-pin SOIC 208mil 8-pin SOIC 150mil 8-pin VSOP 208mil 8-pin TSSOP 8-pin VVSOP 150mil 8-contact WSON 6x5mm 8-contact USON 4x3mm 8-contact USON 2x3mm HOLD# or RESET# IO3 RESET#/NC SO IO1 SI IO0 WP# IO2 Top View, Balls Facing Down NC RESET#/NC NC WP# IO2 D4 1,2 NC SO IO1 SI IO0 HOLD# IO3 or RESET# IO3 16-pin SOIC 300mil 24-ball TFBGA 6x8mm P7 bit setting in Read Register will select HOLD# P7=0 function or RESET# P7=1 function when QE=0 for the standard devices, which do not have dedicated RESET# pin. For the parts with dedicated RESET# pin on pin3 16-pin SOIC or ball A3 24-ball TFBGA , only HOLD# pin is selected for pin1 16-pin SOIC or ball D4 24-ball TFBGA regardless of the P7 bit setting. For the dedicated RESET# devices, Function Register Bit0 RESET# Enable/Disable was set to “0” from the factory. The RESET# pin is independent of the P7 bit of Read Register. The RESET# pin has an internal pull-up resistor and may be left floating if not used. See the Ordering Information for the additional RESET# pin option. 16-pin SOIC / 24-ball TFBGA Standard device 1 Device with dedicated RESET# pin 2,3 Pin1 / Ball D4 Hold# IO3 or RESET# IO3 by P7 bit setting Hold# IO3 only regardless of P7 bit setting Pin3 / Ball A3 RESET# Part Number Option R or P Integrated Silicon Solution, Inc.- 09/24/2015 IS25WP016/080/040/020 PIN DESCRIPTIONS For all the standard devices without dedicated RESET# pin TYPE SI IO0 , SO IO1 WP# IO2 HOLD# or RESET# IO3 INPUT/OUTPUT INPUT/OUTPUT INPUT/OUTPUT INPUT Chip Enable The Chip Enable CE# pin enables and disables the devices operation. When CE# is high the device is deselected and output pins are in a high impedance state. When deselected the devices non-critical internal circuitry power down to allow minimal levels of power consumption while in a standby state. When CE# is pulled low the device will be selected and brought out of standby mode. The device is considered active and instructions can be written to, data read, and written to the device. After power-up, CE# must transition from high to low before a new instruction will be accepted. Keeping CE# in a high state deselects the device and switches it into its low power state. Data will not be accepted when CE# is high. Serial Data Input, Serial Output, and IOs SI, SO, IO0, and IO1 This device supports standard SPI, Dual SPI, and Quad SPI operation. Standard SPI instructions use the unidirectional SI Serial Input pin to write instructions, addresses, or data to the device on the rising edge of the Serial Clock SCK . Standard SPI also uses the unidirectional SO Serial Output to read data or status from the device on the falling edge of the serial clock SCK . In Dual and Quad SPI mode, SI and SO become bidirectional IO pins to write instructions, addresses or data to the device on the rising edge of the Serial Clock SCK and read data or status from the device on the falling edge of SCK. Quad SPI instructions use the WP# and HOLD# pins as IO2 and IO3 respectively. Write Protect/Serial Data IO IO2 The WP# pin protects the Status Register from being written in conjunction with the SRWD bit. When the SRWD is set to “1” and the WP# is pulled low, the Status Register bits SRWD, QE, BP3, BP2, BP1, BP0 are write-protected and vice-versa for WP# high. When the SRWD is set to “0”, the Status Register is not write-protected regardless of WP# state. When the QE bit is set to “1”, the WP# pin Write Protect function is not available since this pin is used for IO2. HOLD# or RESET#/Serial Data IO IO3 When the QE bit of Status Register is set to “1”, HOLD# pin or RESET# is not available since it becomes IO3. When QE=0, the pin acts as HOLD# or RESET# and either one can be selected by the P7 bit setting in Read Register. HOLD# will be selected if P7=0 Default and RESET# will be selected if P7=1. The HOLD# pin allows the device to be paused while it is selected. It pauses serial communication by the master device without resetting the serial sequence. The HOLD# pin is active low. When HOLD# is in a low state and CE# is low, the SO pin will be at high impedance. Device operation can resume when HOLD# pin is brought to a high state. RESET# pin is a hardware RESET signal. When RESET# is driven HIGH, the memory is in the normal operating mode. When RESET# is driven LOW, the memory enters reset mode and output is High-Z. If RESET# is driven LOW while an internal WRITE, PROGRAM, or ERASE operation is in progress, data may be lost. Serial Data Clock Synchronized Clock for input and output timing operations. POWER Power Device Core Power Supply GROUND Ground Connect to ground when referenced to Vcc Unused NC Pins labeled “NC” stand for “No Connect” and should be left unconnected. Note1 In case of the device with dedicated RESET# pin, IO3 pin can be switched to HOLD# only when QE bit=0 See the Ordering Information for the dedicated RESET# pin option. Integrated Silicon Solution, Inc.- 09/24/2015 IS25WP016/080/040/020 SPI MODES DESCRIPTION Multiple IS25WP016/080/040/020 devices can be connected on the SPI serial bus and controlled by a SPI Master, i.e. microcontroller, as shown in Figure The devices support either of two SPI modes: Mode 0, 0 Mode 3 1, 1 The difference between these two modes is the clock polarity. When the SPI master is in stand-by mode, the serial clock remains at “0” SCK = 0 for Mode 0 and the clock remains at “1” SCK = 1 for Mode Please refer to Figure and Figure for SPI and QPI mode. In both modes, the input data is latched on the rising edge of Serial Clock SCK , and the output data is available from the falling edge of SCK. Figure Connection Diagram among SPI Master and SPI Slaves Memory Devices SPI interface with 0,0 or 1,1 SPI Master i.e. Microcontroller CS3 CS2 CS1 SDO SDI SCK SCK SO SI SCK SO SI SCK SO SI SPI Memory Device SPI Memory Device SPI Memory Device WP# HOLD# or 1 RESET WP# HOLD# or 1 RESET# WP# HOLD# or 1 RESET# Notes In case of the device with dedicated RESET# pin, IO3 pin can be switched to HOLD# only when QE bit=0 See the Ordering Information for the dedicated RESET# pin option. SI and SO pins become bidirectional IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3 respectively during QPI mode. Integrated Silicon Solution, Inc.- 09/24/2015 Figure SPI Mode Support SCK Mode 0,0 Mode 3 1,1 IS25WP016/080/040/020 Figure QPI Mode Support SCK IO0 Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Mode 0 3-byte Address Mode Bits Data 1 Data 2 Data 3 C4 C0 20 16 12 8 4 0 4 0 4 0 4 0 4 0 C5 C1 21 17 13 9 5 1 5 1 5 1 5 1 5 1 C6 C2 22 18 14 10 6 2 6 2 6 2 6 2 6 2 C71 C3 231 19 15 11 7 Note1 MSB Most Significant Bit Integrated Silicon Solution, Inc.- 09/24/2015 IS25WP016/080/040/020 SYSTEM CONFIGURATION The memory array is divided into uniform 4 Kbyte sectors or uniform 32/64 Kbyte blocks a block consists of eight/sixteen adjacent sectors respectively . Table illustrates the memory map of the device. The Status Register controls how the memory is protected. BLOCK/SECTOR ADDRESSES Table Block/Sector Addresses of IS25WP016/080/040/020 Memory Density Block No. 64Kbyte Block 0 2Mb 4Mb 8Mb Block 1 : Block 3 : 16Mb Block 7 Block 15 Block 30 Block 31 Block No. 32Kbyte ORDERING INFORMATION - Valid Part Numbers IS25WP016 - J B L E TEMPERATURE RANGE E = Extended -40°C to +105°C E1 = Extended+ -40°C to +125°C A1 = Automotive Grade -40°C to +85°C A2 = Automotive Grade -40°C to +105°C A3 = Automotive Grade -40°C to +125°C PACKAGING CONTENT L = RoHS compliant PACKAGE Type 1 , 2 B = 8-pin SOIC 208mil N = 8-pin SOIC 150mil D = 8-pin TSSOP V = 8-pin VVSOP 150mil K = 8-contact WSON 6x5mm T = 8-contact USON 4x3mm U = 8-contact USON 2x3mm F = 8-pin VSOP 208mil M = 16-pin SOIC 300mil G = 24-ball TFBGA 6x8mm W = KGD Call Factory Option J = Standard R = Dedicated RESET# pin option for 16-pin SOIC and 24- ball TFBGA Density 016 = 16 Megabit 080 = 8 Megabit 040 = 4 Megabit 020 = 2 Megabit BASE PART NUMBER IS = Integrated Silicon Solution Inc. 25WP = FLASH, 1.65V ~ 1.95V, QPI Notes IS25WP016 not available in D and IS25WP080/040 not available in D, M, G and IS25WP020 not available in T, F, M, G Call Factory for WLCSP package or other package options available Integrated Silicon Solution, Inc.- 09/24/2015 Density Frequency MHz 16Mb Order Part Number 1 IS25WP016-JBLE IS25WP016-JBLE1 IS25WP016-JNLE IS25WP016-JNLE1 IS25WP016-JVLE IS25WP016-JVLE1 IS25WP016-JKLE IS25WP016-JKLE1 IS25WP016-JTLE IS25WP016-JTLE1 IS25WP016-JULE IS25WP016-JULE1 IS25WP016-JFLE IS25WP016-JFLE1 IS25WP016-JMLE IS25WP016-JMLE1 IS25WP016-JGLE IS25WP016-JGLE1 IS25WP016-RMLE IS25WP016-RMLE1 IS25WP016-RGLE IS25WP016-RGLE1 IS25WP016-JBLA* IS25WP016-JNLA* IS25WP016-JVLA* IS25WP016-JKLA* IS25WP016-JTLA*

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IS25WP016 IS25WP080 IS25WP040 IS25WP020
16/8/4/2MBIT
1.8V SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE

PRELIMINARY DATA SHEET
16/8/4/2MBIT
1.8V SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE

IS25WP016/080/040/020

PRELIMINARY INFORMATION
• Industry Standard Serial Interface - IS25WP016 16Mbit/2Mbyte - IS25WP080 8Mbit/1Mbyte - IS25WP040 4Mbit/512Kbyte - IS25WP020 2Mbit/256Kbyte - 256 bytes per Programmable Page - Supports standard SPI, Fast, Dual, Dual I/O, Quad, Quad I/O, SPI DTR, Dual I/O DTR, Quad I/O DTR, and QPI - Supports Serial Flash Discoverable Parameters SFDP
• High Performance Serial Flash SPI - 50MHz Normal and 133Mhz Fast Read - 532 MHz equivalent QPI - DTR Dual Transfer Rate up to 66MHz - Selectable Dummy Cycles - Configurable Drive Strength - Supports SPI Modes 0 and 3 - More than 100,000 Erase/Program cycles - More than 20-year Data Retention
• Flexible & Efficient Memory Architecture - Chip Erase with Uniform Sector/Block Erase 4/32/64 Kbyte - Program 1 to 256 Bytes per Page - Program/Erase Suspend & Resume
• Efficient Read and Program modes - Low Instruction Overhead Operations - Continuous Read 8/16/32/64-Byte Burst Wrap - Selectable Burst Length - QPI for Reduced Instruction Overhead - AutoBoot Operation
• Low Power with Wide Temp. Ranges - Single 1.65V to 1.95V Voltage Supply - 10 mA Active Read Current typ. - 8 µA Standby Current typ. - 1 µA Deep Power Down typ. - Temp Grades Extended -40°C to +105°C Extended+ -40°C to +125°C Auto Grade up to +125°C

Note Extended+ should not be used for Automotive.
• Advanced Security Protection - Software and Hardware Write Protection - Power Supply Lock Protection - 4x256-Byte Dedicated Security Area with OTP User-lockable Bits - 128 bit Unique ID for Each Device Call Factory
• Industry Standard Pin-out & Packages 1 , 2 - M =16-pin SOIC 300mil 3 - B = 8-pin SOIC 208mil - N = 8-pin SOIC 150mil - D = 8-pin TSSOP - V = 8-pin VVSOP 150mil - F = 8-pin VSOP 208mil - K = 8-contact WSON 6x5mm - T = 8-contact USON 4x3mm - U = 8-contact USON 2x3mm - G = 24-ball TFBGA 6x8mm 3 - KGD Call Factory

Notes IS25WP016 not available in D and
IS25WP080/040 not available in M, D, G and IS25WP020 not available in M, F, T, G Call Factory for WLCSP or other package options available For the dedicated RESET# pin option, see the Ordering Information

Integrated Silicon Solution, Inc.-
09/24/2015

IS25WP016/080/040/020

The IS25WP016/080/040/020 Serial Flash memory offers a versatile storage solution with high flexibility and performance in a simplified pin count package. ISSI’s “Industry Standard Serial Interface” Flash is for systems that require limited space, a low pin count, and low power consumption. The device is accessed through a 4wire SPI Interface consisting of a Serial Data Input SI , Serial Data Output SO , Serial Clock SCK , and Chip Enable CE# pins, which can also be configured to serve as multi-I/O see pin descriptions .

The device supports Dual and Quad I/O as well as standard, Dual Output, and Quad Output SPI. Clock frequencies of up to 133MHz allow for equivalent clock rates of up to 532MHz 133MHz x 4 which equates to 66Mbytes/s of data throughput. The IS25xP series of Flash adds support for DTR Double Transfer Rate commands that transfer addresses and read data on both edges of the clock. These transfer rates can outperform 16-bit Parallel Flash memories allowing for efficient memory access to support XIP execute in place operation.

The memory array is organized into programmable pages of 256-bytes. This family supports page program mode where 1 to 256 bytes of data are programmed in a single command. QPI Quad Peripheral Interface supports 2-cycle instruction further reducing instruction times. Pages can be erased in groups of 4Kbyte sectors, 32Kbyte blocks, 64Kbyte blocks, and/or the entire chip. The uniform sector and block architecture allows for a high degree of flexibility so that the device can be utilized for a broad variety of applications requiring solid data retention.

GLOSSARY

Standard SPI In this operation, a 4-wire SPI Interface is utilized, consisting of Serial Data Input SI , Serial Data Output SO , Serial Clock SCK , and Chip Enable CE# pins. Instructions are sent via the SI pin to encode instructions, addresses, or input data to the device on the rising edge of SCK. The SO pin is used to read data or to check the status of the device. This device supports SPI bus operation modes 0,0 and

Mutil I/O SPI Multi-I/O operation utilizes an enhanced SPI protocol to allow the device to function with Dual Output, Dual Input and Output, Quad Output, and Quad Input and Output capability. Executing these instructions through SPI mode will achieve double or quadruple the transfer bandwidth for READ and PROGRAM operations.

QPI The device supports Quad Peripheral Interface QPI operations only when the device is switched from Standard/Dual/Quad SPI mode to QPI mode using the enter QPI 35h instruction. The typical SPI protocol requires that the byte-long instruction code being shifted into the device only via SI pin in eight serial clocks. The QPI mode utilizes all four I/O pins to input the instruction code thus requiring only two serial clocks. This can significantly reduce the SPI instruction overhead and improve system performance. Only QPI mode or SPI/Dual/Quad mode can be active at any given time. Enter QPI 35h and Exit QPI F5h instructions are used to switch between these two modes, regardless of the non-volatile Quad Enable QE bit status in the Status Register. Power Reset or Hardware/Software Reset will return the device into the standard SPI mode. SI and SO pins become bidirectional I/O0 and I/O1, and WP# and HOLD# pins become I/O2 and I/O3 respectively during QPI mode.

DTR In addition to SPI and QPI features, the device also supports Fast READ DTR operation. DTR operation allows high data throughput while running at lower clock frequencies. Fast READ DTR operation uses both rising and falling edges of the clock for address inputs, and data outputs, resulting in reducing input and output cycles by half.

Integrated Silicon Solution, Inc.-
09/24/2015

IS25WP016/080/040/020

TABLE OF CONTENTS

FEATURES GENERAL DESCRIPTION TABLE OF CONTENTS PIN DESCRIPTIONS BLOCK DIAGRAM SPI MODES DESCRIPTION SYSTEM CONFIGURATION

BLOCK/SECTOR ADDRESSES REGISTERS

STATUS REGISTER FUNCTION REGISTER READ REGISTER AND EXTENDED AUTOBOOT REGISTER PROTECTION HARDWARE WRITE SOFTWARE WRITE PROTECTION DEVICE OPERATION NORMAL READ OPERATION NORD, 03h FAST READ OPERATION FRD, 0Bh HOLD FAST READ DUAL I/O OPERATION FRDIO, BBh FAST READ DUAL OUTPUT OPERATION FRDO, FAST READ QUAD OUTPUT OPERATION FRQO, FAST READ QUAD I/O OPERATION FRQIO, EBh PAGE PROGRAM OPERATION PP, QUAD INPUT PAGE PROGRAM OPERATION PPQ, 32h/38h ERASE OPERATION SECTOR ERASE OPERATION SER, BLOCK ERASE OPERATION BER32K:52h, BER64K:D8h CHIP ERASE OPERATION CER, C7h/60h WRITE ENABLE OPERATION WREN, 06h WRITE DISABLE OPERATION WRDI, READ STATUS REGISTER OPERATION RDSR, 05h WRITE STATUS REGISTER OPERATION WRSR, READ FUNCTION REGISTER OPERATION RDFR, 48h WRITE FUNCTION REGISTER OPERATION WRFR, ENTER QUAD PERIPHERAL INTERFACE QPI MODE OPERATION QPIEN, 35h QPIDI, F5h 54

Integrated Silicon Solution, Inc.-
09/24/2015

IS25WP016/080/040/020

PROGRAM/ERASE SUSPEND & ENTER DEEP POWER DOWN DP, B9h RELEASE DEEP POWER DOWN RDPD, ABh SET READ PARAMETERS OPERATION SRPNV 65h, SRPV C0h/63h SET EXTENDED READ PARAMETERS OPERATION SERPNV 85h, SERPV 83h READ PARAMETERS OPERATION RDRPNV, 61h READ EXTENDED READ PARAMETERS OPERATION RDRPNV, 81h READ PRODUCT IDENTIFICATION RDID, ABh READ PRODUCT IDENTIFICATION BY JEDEC ID OPERATION RDJDID, 9Fh RDJDIDQ, AFh 66 READ DEVICE MANUFACTURER AND DEVICE ID OPERATION RDMDID, 90h READ UNIQUE ID NUMBER RDUID, 4Bh READ SFDP OPERATION RDSFDP, 5Ah NO OPERATION NOP, 00h SOFTWARE RESET-ENABLE RSTEN, 66h AND RESET RST, 99h AND HARDWARE RESET SECURITY INFORMATION ROW ERASE OPERATION IRER, 64h INFORMATION ROW PROGRAM OPERATION IRP, 62h INFORMATION ROW READ OPERATION IRRD, 68h FAST READ DTR MODE OPERATION FRDTR, FAST READ DUAL IO DTR MODE OPERATION FRDDTR, BDh FAST READ QUAD IO DTR MODE OPERATION FRQDTR, EDh SECTOR LOCK/UNLOCK FUNCTIONS ELECTRICAL ABSOLUTE MAXIMUM RATINGS 1 OPERATING RANGE DC AC MEASUREMENT CONDITIONS PIN CAPACITANCE TA = 25°C, VCC=1.8V, 1MHz AC SERIAL INPUT/OUTPUT POWER-UP AND POWER-DOWN PROGRAM/ERASE PERFORMANCE RELIABILITY CHARACTERISTICS PACKAGE TYPE 8-Pin JEDEC 208mil Broad Small Outline Integrated Circuit SOIC Package B 8-Pin JEDEC 150mil Broad Small Outline Integrated Circuit SOIC Package N 8-Pin TSSOP Package D 8-Pin 150mil VVSOP Package

Integrated Silicon Solution, Inc.-
09/24/2015

IS25WP016/080/040/020
8-Contact Ultra-Thin Small Outline No-Lead WSON Package 6x5mm 8-Contact Ultra-Thin Small Outline No-Lead USON Package 4x3mm 8-Contact Ultra-Thin Small Outline No-Lead USON Package 2x3mm U 8-Pin 208mil VSOP Package F 16-lead Plastic Small Outline package 300 mils body width M 24-Ball Thin Profile Fine Pitch BGA 6x8mm ORDERING INFORMATION - Valid Part

Integrated Silicon Solution, Inc.-
09/24/2015

PIN CONFIGURATION

IS25WP016/080/040/020

SO IO1

WP# IO2

CE# 1

HOLD# or 1

RESET# IO3

SO IO1 2

SI IO0

WP# IO2 3 GND 4
8 Vcc

HOLD# or 1

RESET# IO3
6 SCK
5 SI IO0
8-pin SOIC 208mil 8-pin SOIC 150mil 8-pin VSOP 208mil
8-pin TSSOP 8-pin VVSOP 150mil
8-contact WSON 6x5mm 8-contact USON 4x3mm 8-contact USON 2x3mm

HOLD# or RESET# IO3

RESET#/NC

SO IO1

SI IO0

WP# IO2

Top View, Balls Facing Down

NC RESET#/NC

NC WP# IO2

D4 1,2

NC SO IO1 SI IO0 HOLD# IO3 or RESET# IO3
16-pin SOIC 300mil
24-ball TFBGA 6x8mm

P7 bit setting in Read Register will select HOLD# P7=0 function or RESET# P7=1 function when QE=0 for the
standard devices, which do not have dedicated RESET# pin.

For the parts with dedicated RESET# pin on pin3 16-pin SOIC or ball A3 24-ball TFBGA , only HOLD# pin is
selected for pin1 16-pin SOIC or ball D4 24-ball TFBGA regardless of the P7 bit setting.

For the dedicated RESET# devices, Function Register Bit0 RESET# Enable/Disable was set to “0” from the
factory. The RESET# pin is independent of the P7 bit of Read Register.
The RESET# pin has an internal pull-up resistor and may be left floating if not used. See the Ordering Information
for the additional RESET# pin option.
16-pin SOIC / 24-ball TFBGA

Standard device 1

Device with dedicated RESET# pin 2,3

Pin1 / Ball D4

Hold# IO3 or RESET# IO3 by P7 bit setting

Hold# IO3 only regardless of P7 bit setting

Pin3 / Ball A3

RESET#

Part Number Option

R or P

Integrated Silicon Solution, Inc.-
09/24/2015

IS25WP016/080/040/020

PIN DESCRIPTIONS

For all the standard devices without dedicated RESET# pin

TYPE

SI IO0 , SO IO1

WP# IO2

HOLD# or RESET# IO3

INPUT/OUTPUT INPUT/OUTPUT INPUT/OUTPUT

INPUT

Chip Enable The Chip Enable CE# pin enables and disables the devices operation. When CE# is high the device is deselected and output pins are in a high impedance state. When deselected the devices non-critical internal circuitry power down to allow minimal levels of power consumption while in a standby state.

When CE# is pulled low the device will be selected and brought out of standby mode. The device is considered active and instructions can be written to, data read, and written to the device. After power-up, CE# must transition from high to low before a new instruction will be accepted.

Keeping CE# in a high state deselects the device and switches it into its low power state. Data will not be accepted when CE# is high.

Serial Data Input, Serial Output, and IOs SI, SO, IO0, and IO1 This device supports standard SPI, Dual SPI, and Quad SPI operation. Standard SPI instructions use the unidirectional SI Serial Input pin to write instructions, addresses, or data to the device on the rising edge of the Serial Clock SCK . Standard SPI also uses the unidirectional SO Serial Output to read data or status from the device on the falling edge of the serial clock SCK .

In Dual and Quad SPI mode, SI and SO become bidirectional IO pins to write instructions, addresses or data to the device on the rising edge of the Serial Clock SCK and read data or status from the device on the falling edge of SCK. Quad SPI instructions use the WP# and HOLD# pins as IO2 and IO3 respectively.

Write Protect/Serial Data IO IO2 The WP# pin protects the Status Register from being written in conjunction with the SRWD bit. When the SRWD is set to “1” and the WP# is pulled low, the Status Register bits SRWD, QE, BP3, BP2, BP1, BP0 are write-protected and vice-versa for WP# high. When the SRWD is set to “0”, the Status Register is not write-protected regardless of WP# state.

When the QE bit is set to “1”, the WP# pin Write Protect function is not available since this pin is used for IO2.

HOLD# or RESET#/Serial Data IO IO3 When the QE bit of Status Register is set to “1”, HOLD# pin or RESET# is not available since it becomes IO3.

When QE=0, the pin acts as HOLD# or RESET# and either one can be selected by the P7 bit setting in Read Register. HOLD# will be selected if P7=0 Default and RESET# will be selected if P7=1.

The HOLD# pin allows the device to be paused while it is selected. It pauses serial communication by the master device without resetting the serial sequence. The HOLD# pin is active low. When HOLD# is in a low state and CE# is low, the SO pin will be at high impedance. Device operation can resume when HOLD# pin is brought to a high state.

RESET# pin is a hardware RESET signal. When RESET# is driven HIGH, the memory is in the normal operating mode. When RESET# is driven LOW, the memory enters reset mode and output is High-Z. If RESET# is driven LOW while an internal WRITE, PROGRAM, or ERASE operation is in progress, data may be lost.

Serial Data Clock Synchronized Clock for input and output timing operations.

POWER

Power Device Core Power Supply

GROUND

Ground Connect to ground when referenced to Vcc

Unused

NC Pins labeled “NC” stand for “No Connect” and should be left unconnected.
Note1 In case of the device with dedicated RESET# pin, IO3 pin can be switched to HOLD# only when QE bit=0 See the Ordering Information for the dedicated RESET# pin option.

Integrated Silicon Solution, Inc.-
09/24/2015

IS25WP016/080/040/020

SPI MODES DESCRIPTION

Multiple IS25WP016/080/040/020 devices can be connected on the SPI serial bus and controlled by a SPI Master, i.e. microcontroller, as shown in Figure The devices support either of two SPI modes:

Mode 0, 0 Mode 3 1, 1

The difference between these two modes is the clock polarity. When the SPI master is in stand-by mode, the serial clock remains at “0” SCK = 0 for Mode 0 and the clock remains at “1” SCK = 1 for Mode Please refer to Figure and Figure for SPI and QPI mode. In both modes, the input data is latched on the rising edge of Serial Clock SCK , and the output data is available from the falling edge of SCK.

Figure Connection Diagram among SPI Master and SPI Slaves Memory Devices

SPI interface with 0,0 or 1,1

SPI Master i.e. Microcontroller

CS3 CS2 CS1

SDO SDI SCK

SCK SO SI

SCK SO SI

SCK SO SI

SPI Memory Device

SPI Memory Device

SPI Memory Device

WP# HOLD# or 1 RESET

WP# HOLD# or 1 RESET#

WP# HOLD# or 1 RESET#

Notes In case of the device with dedicated RESET# pin, IO3 pin can be switched to HOLD# only when QE bit=0 See the
Ordering Information for the dedicated RESET# pin option. SI and SO pins become bidirectional IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3 respectively
during QPI mode.

Integrated Silicon Solution, Inc.-
09/24/2015

Figure SPI Mode Support

SCK Mode 0,0

Mode 3 1,1

IS25WP016/080/040/020

Figure QPI Mode Support

SCK IO0

Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Mode 0
3-byte Address

Mode Bits Data 1

Data 2

Data 3

C4 C0 20 16 12 8 4 0 4 0 4 0 4 0 4 0

C5 C1 21 17 13 9 5 1 5 1 5 1 5 1 5 1

C6 C2 22 18 14 10 6 2 6 2 6 2 6 2 6 2

C71 C3 231 19 15 11 7

Note1 MSB Most Significant Bit

Integrated Silicon Solution, Inc.-
09/24/2015

IS25WP016/080/040/020

SYSTEM CONFIGURATION

The memory array is divided into uniform 4 Kbyte sectors or uniform 32/64 Kbyte blocks a block consists of eight/sixteen adjacent sectors respectively .

Table illustrates the memory map of the device. The Status Register controls how the memory is protected.

BLOCK/SECTOR ADDRESSES

Table Block/Sector Addresses of IS25WP016/080/040/020

Memory Density

Block No. 64Kbyte

Block 0
2Mb 4Mb 8Mb

Block 1 :

Block 3 :
16Mb

Block 7

Block 15

Block 30

Block 31

Block No. 32Kbyte
ORDERING INFORMATION - Valid Part Numbers

IS25WP016 - J B L E

TEMPERATURE RANGE E = Extended -40°C to +105°C E1 = Extended+ -40°C to +125°C A1 = Automotive Grade -40°C to +85°C A2 = Automotive Grade -40°C to +105°C A3 = Automotive Grade -40°C to +125°C

PACKAGING CONTENT L = RoHS compliant

PACKAGE Type 1 , 2 B = 8-pin SOIC 208mil N = 8-pin SOIC 150mil D = 8-pin TSSOP V = 8-pin VVSOP 150mil K = 8-contact WSON 6x5mm T = 8-contact USON 4x3mm U = 8-contact USON 2x3mm F = 8-pin VSOP 208mil M = 16-pin SOIC 300mil G = 24-ball TFBGA 6x8mm W = KGD Call Factory

Option J = Standard R = Dedicated RESET# pin option for 16-pin SOIC and 24-
ball TFBGA

Density 016 = 16 Megabit 080 = 8 Megabit 040 = 4 Megabit 020 = 2 Megabit

BASE PART NUMBER IS = Integrated Silicon Solution Inc. 25WP = FLASH, 1.65V ~ 1.95V, QPI

Notes IS25WP016 not available in D and IS25WP080/040 not available in D, M, G and

IS25WP020 not available in T, F, M, G Call Factory for WLCSP package or other package options available

Integrated Silicon Solution, Inc.-
09/24/2015

Density Frequency MHz
16Mb

Order Part Number 1

IS25WP016-JBLE

IS25WP016-JBLE1

IS25WP016-JNLE

IS25WP016-JNLE1

IS25WP016-JVLE

IS25WP016-JVLE1

IS25WP016-JKLE

IS25WP016-JKLE1

IS25WP016-JTLE

IS25WP016-JTLE1

IS25WP016-JULE

IS25WP016-JULE1

IS25WP016-JFLE

IS25WP016-JFLE1

IS25WP016-JMLE

IS25WP016-JMLE1

IS25WP016-JGLE

IS25WP016-JGLE1

IS25WP016-RMLE IS25WP016-RMLE1

IS25WP016-RGLE IS25WP016-RGLE1

IS25WP016-JBLA*

IS25WP016-JNLA*

IS25WP016-JVLA*

IS25WP016-JKLA*

IS25WP016-JTLA*

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IS25WP016-JBLE-TR Datasheet file may be downloaded here without warranties.

Datasheet ID: IS25WP016-JBLE-TR 639287