STAC9753XXTAEB2XR

STAC9753XXTAEB2XR Datasheet

TWO-CHANNEL, 20-BIT, AC’97 CODECS WITH HEADPHONE STAC9752/9753 DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

Part	Datasheet
STAC9753XXTAEB2XR	STAC9753XXTAEB2XR (pdf)

Related Parts	Information
STAC9753XXTAEB2X	STAC9753XXTAEB2X

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DATASHEET TWO-CHANNEL, 20-BIT, AC’97 CODECS WITH HEADPHONE STAC9752/9753 DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING • High performance technology • 20-bit full duplex stereo ADCs, DACs • Independent sample rates for ADCs & DACs • 5-wire AC-Link protocol compliance • 20-bit SPDIF Output • Internal Jack Sensing on Headphone and Line_Out • Internal Microphone Input Sensing • Digital PC Beep Option • Extended AC’97 Paging Registers • Adjustable VREF amplifier • Digital-ready status • General purpose I/Os • Crystal Elimination Circuit • Headphone drive capability 50 mW • 0dB, 10dB, 20dB, and 30dB microphone boost capability • V STAC9753 and +5 V STAC9752 analog power supply options • Pin compatible with the STAC9700, STAC9721, STAC9756 • 100% pin compatible with STAC9750 and STAC9766 STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING V 101006 STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING TABLE OF CONTENTS PRODUCT BRIEF 7 Description 7 STAC9752/9753 Block Diagram 8 Key Specifications 8 Related Materials 9 Additional Support 9 CHARACTERISTICS AND SPECIFICATIONS Electrical Specifications 10 Absolute Maximum Ratings 10 Recommended Operation Conditions 10 Power Consumption 11 AC-Link Static Digital Specifications 12 STAC9752 5 V Analog Performance Characteristics 12 STAC9753 3.3V Analog Performance Characteristics AC Timing Characteristics 16 Cold Reset 16 Warm Reset 16 Clocks 17 STAC9752/9753 Crystal Elimination Circuit and Clock Frequencies Data Setup and Hold 18 Signal Rise and Fall Times 18 AC-Link Low Power Mode Timing 19 ATE Test Mode 19 TYPICAL CONNECTION DIAGRAM Slit Independent Power Supply Operation 21 CONTROLLER, CODEC AND AC-LINK AC-Link Physical Interface 23 Controller to Single CODEC 23 Controller to Multiple CODECs 25 Primary CODEC Addressing 25 Secondary CODEC Addressing 25 CODEC ID Strapping 26 Clocking for Multiple CODEC Implementations 26 STAC9752/9753 as a Primary CODEC 26 STAC9752/9753 as a Secondary CODEC 26 AC-Link Power Management 27 Powering down the AC-Link 27 Waking up the AC-Link 27 CODEC Reset 28 AC-LINK DIGITAL INTERFACE Overview 29 AC-Link Serial Interface Protocol 30 AC-Link Variable Sample Rate Operation 30 Variable Sample Rate Signaling Protocol 30 Primary and Secondary CODEC Register Addressing 32 AC-Link Output Frame SDATA_OUT 32 Slot 0 TAG / CODEC ID 34 Slot 1 Command Address Port 34 Slot 2 Command Data Port 35 Slot 3 PCM Playback Left Channel 35 Slot 4 PCM Playback Right Channel 35 Slot 5 Modem Line 1 Output Channel 35 Slot 6 - 11 DAC 35 STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING Slot 12 Audio GPIO Control Channel 36 AC-Link Input Frame SDATA_IN 36 Slot 0 TAG Slot 1 Status Address Port / SLOTREQ signalling bits Slot 2 Status Data Port 38 Slot 3 PCM Record Left Channel 38 Slot 4 PCM Record Right Channel 38 Slot 5 Modem Line 1 ADC 38 Slot 6 - 9 ADC 38 Slots 7 & 8 Vendor Reserved 39 Slot 10 & 11 ADC 39 Slot 12 Reserved 39 AC-Link Interoperability Requirements and Recommendations 40 “Atomic slot” Treatment of Slot 1 Address and Slot 2 Data Slot Assignments for Audio 41 STAC9752/9753 MIXER FUNCTIONAL DIAGRAMS Analog Mixer Input 45 Mixer Analog Output 45 SPDIF Digital Mux PC Beep Implementation 46 Analog PC Beep 46 Digital PC Beep 46 PROGRAMMING REGISTERS Register Descriptions 48 Reset 00h 48 Master Volume Registers 02h 48 Headphone Volume Registers 04h 49 Master Volume MONO 06h 50 PC BEEP Volume 0Ah 51 Phone Volume Index 0Ch 51 Mic Volume Index 0Eh 52 LineIn Volume Index 10h 52 CD Volume Index 12h 53 Video Volume Index 14h 53 Aux Volume Index 16h 54 PCMOut Volume Index 18h 54 Record Select 1Ah 55 Record Gain 1Ch 55 General Purpose 20h 56 3D Control 22h 56 Audio Interrupt and Paging 24h 57 Powerdown Ctrl/Stat 26h 58 Extended Audio ID 28h 59 Extended Audio Control/Status 2Ah 61 PCM DAC Rate Registers 2Ch and 32h 63 PCM DAC Rate 2Ch 63 PCM LR ADC Rate 32h 63 SPDIF Control 3Ah 64 General Purpose Input & Outputs 64 EAPD 64 GPIO Pin Definitions 65 GPIO Pin Implementation 65 Extended Modem Status and Control Register 3Eh GPIO Pin Configuration Register 4Ch 66 STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING LIST OF FIGURES Figure Block Diagram 8 Figure Cold Reset Timing 16 Figure Warm Reset Timing 16 Figure Clocks Timing 17 Figure Data Setup and Hold Timing 18 Figure Signal Rise and Fall Times Timing 18 Figure AC-Link Low Power Mode Timing 19 Figure ATE Test Mode Timing 19 Figure Typical Connection Diagram 20 Figure Split Independent Power Supply Operation 22 Figure AC-Link to its Companion Controller 23 Figure CODEC Clock Source Detection 24 Figure STAC9752/9753 Powerdown Timing 27 Figure Bi-directional AC-Link Frame with Slot assignments 29 Figure AC-Link Audio Output Frame 33 Figure Start of an Audio Output Frame 33 Figure STAC9752/9753 Audio Input Frame 36 Figure Start of an Audio Input Frame 36 Figure Bi-directional AC-Link Frame with Slot assignments 41 Figure STAC9752 2-Channel Mixer Functional Diagram 44 Figure STAC9753 2-Channel Mixer Functional Diagram Figure Example of STAC9752/9753 Powerdown/Powerup flow Figure Powerdown/Powerup flow with analog still alive 81 Figure Pin Description Drawing 85 Figure Reflow Profile STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING LIST OF TABLES Table Clock Mode Configuration 17 Table Common Clocks and Sources 18 Table Recommended CODEC ID strapping 26 Table AC-Link output slots transmitted from the Controller 29 Table The AC-Link input slots transmitted from the CODEC 30 Table VRA Behavior 31 Table Output Slot 0 Bit Definitions 34 Table Command Address Port Bit Assignments 35 Table Status Address Port Bit Assignments 37 Table Status Data Port Bit Assignments 38 Table Primary CODEC Addressing Slot 0 Tag Bits 40 Table Secondary CODEC Addressing Slot 0 Tag Bits 40 Table AC-Link Slot Definitions 41 Table AC-Link Input Slots Dedicated To Audio 41 Table Audio Interrupt Slot Definitions 42 Table Digital PC Beep Examples 46 Table Programming Registers 47 Table Extended Audio ID Register Functions 60 Table AMAP compliant 63 Table Hardware Supported Sample Rates 63 Table Supported Jack and Microphone Sense Functions Table Reg 68h Default Values 73 Table Gain or Attenuation Examples 73 Table Register 68h/Page 01h Bit Overview 73 Table Sensed Bits Outputs 75 Table Sensed Bits Inputs 75 Table Low Power Modes 80 Table CODEC ID Selection Table Secondary CODEC Register Access Slot 0 Bit Definitions Table Test Mode Activation Table ATE Test Mode Operation 84 Table Digital Connection Signals 86 Table Analog Connection Signals 87 Table Filtering and Voltage References 88 Table Power and Ground Signals 88 STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING The STAC9752/9753 block diagram is illustrated in Figure The STAC9752/9753 provides variable sample rate Digital-to-Analog DA and Analog-to-Digital AD conversion, mixing, and analog processing. Supported audio sample rates include 48 KHz, KHz, 32 KHz, KHz, 16 KHz, KHz, and 8 KHz additional rates are supported in the STAC9752/9753 soft audio drivers. All ADCs and DACs operate at 20-bit resolution. Two 20-bit DACs convert the digital stereo PCM_OUT content to audio. The MIXER block combines the PCM_OUT with any analog sources, to drive the LINE_OUT and HP_OUT outputs. The MONO_OUT delivers either microphone only, or a mono mix of sources from the MIXER. The stereo variable-sample-rate 20-bit ADCs provide record capability for any mix of mono or stereo sources, and deliver a digital stereo PCM-in signal back to the AC-Link. The microphone input and mono mix input can be recorded simultaneously, thus allowing for an all digital output in support of the digital ready initiative. For a digital ready record path, the microphone is connected to the left channel ADC while the mono output of the stereo mixer is connected to right channel ADC. The STAC9752/9753 include jack sensing on the Headphone and Line_Out. The STAC9752/9753 jack sense can detect the presence of devices on the Headphone and Line Outputs and on both Microphone inputs. With proprietary IDT current and impedance-sensing techniques, the impedance load on the Headphone and Line Outputs can also be detected. The GPIOs on the STAC9752/9753 remain available for advanced configurations. The STAC9752/9753 implementation of jack sense uses the Extended Paging Registers defined by the AC'97 Specification. This allows for additional registry space to hold the identification information about the CODEC, the jack sensing details and results, and the external surroundings of the CODEC. The information within the Extended Paging Registers will allow for the automatic configuration of the audio subsystem without end-user intervention. For example, the BIOS can populate the Extended Paging Registers with valuable information for both the audio driver and the operating system such as gain and attenuation stages, input population and input phase. With this input information, the IDT driver will automatically provide to the Volume Control Panel only the volume sliders that are implemented in the system, thus improving the end-user's experience with the PC. The information in the Extended Paging Registers will also allow for automatic configuration of microphone inputs, the ability to switch between SPDIF and analog outputs, the routing of the mas- STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING ter volume slider to the proper physical output, and SoftEQ configurations. The fully parametric IDT SoftEQ can be initiated upon jack insertion and sensed impedance levels. The STAC9752/9753 also offers 2 styles of PC BEEP Analog and Digital. The digital PC Beep is a new feature added to the AC’97 Specification Rev The STAC9752/9753 is designed primarily to support stereo 2-speaker audio. True AC-3 playback can be achieved for 6-speaker applications by taking advantage of the multi-CODEC option available in the STAC9752/9753 to support multiple CODECs in an AC'97 architecture. Additionally, the STAC9752/9753 provides for a stereo enhancement feature, IDT Surround 3D SS3D . SS3D provides the listener with several options for improved speaker separation beyond the normal two- or four-speaker arrangements. The STAC9752/9753 can be and Windows Sound compatible when used with IDT’s WDM driver for Windows 98/2K/ME/XP or with Intel/Microsoft driver included with Windows 2K/ME/XP. SoundBlaster is a registered trademark of Creative Labs. Windows is a registered trademark of Microsoft Corporation. STAC9752/9753 Block Diagram AC-link SYNC BIT_CLK SDATA_OUT SDATA_IN RESET# Multi-Codec CID0 CID1 EAPD Variable Sample Rate 20-Bit DACs and 20-Bit ADCs Figure Block Diagram Power Management 4 stereo sources PCM out DACs 2 mono sources Stereo Mono Digital Interface MIXER HP_OUT LINE_OUT Registers 64x16 bits ORDERING INFORMATION Part Number STAC9752XXTAEyyX STAC9753XXTAEyyX Package 48-pin RoHS QFP 7mm x 7mm x 1.4mm 48-pin RoHS QFP 7mm x 7mm x 1.4mm Temp Range 0° C to +70° C 0° C to +70° C Supply Range DVdd = 3.3V, AVdd = 5.0V DVdd = 3.3V, AVdd = 3.3V Add an “R” to the end of the Part number for Tape and Reel delivery. Minimum order quantitiy is 2ku. PACKAGE DRAWING 48 pin LQFP Pin 1 LQFP Dimensions in mm Key Min. Nom. Max. STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING SOLDER REFLOW PROFILE Standard Reflow Profile Data Note These devices can be hand soldered at 360 oC for 3 to 5 seconds. FROM IPC / JEDEC J-STD-020C “Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices” Profile Feature Pb Free Assembly Average Ramp-Up Rate Tsmax - Tp Preheat Temperature Min Tsmin Temperature Max Tsmax Time tsmin - tsmax Time maintained above Temperature TL Time tL Peak / Classification Temperature Tp 3 oC / second max 150 oC 200 oC 60 - 180 seconds 217 oC 60 - 150 seconds See “Package Classification Reflow Temperatures” on page Time within 5 oC of actual Peak Temperature tp 20 - 40 seconds Ramp-Down rate 6 oC / second max Time 25 oC to Peak Temperature 8 minutes max Note All temperatures refer to topside of the package, measured on the package body surface. Figure Reflow Profile STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING Pb Free Process - Package Classification Reflow Temperatures Package Type TQFP 48-pin MSL 3 Reflow Temperature 260 oC* STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING Updated part ordering information to longer orderable part number related to previously issued PCN. STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING Innovate with IDT audio for high fidelity. Contact: For Sales 800-345-7015 408-284-8200 Fax 408-284-2775 For Tech Support Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 outside U.S. Europe IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE +44 1372 363 339 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners.

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DATASHEET

TWO-CHANNEL, 20-BIT, AC’97 CODECS WITH HEADPHONE STAC9752/9753 DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
• High performance technology
• 20-bit full duplex stereo ADCs, DACs
• Independent sample rates for ADCs & DACs
• 5-wire AC-Link protocol compliance
• 20-bit SPDIF Output
• Internal Jack Sensing on Headphone and Line_Out
• Internal Microphone Input Sensing
• Digital PC Beep Option
• Extended AC’97 Paging Registers
• Adjustable VREF amplifier
• Digital-ready status
• General purpose I/Os
• Crystal Elimination Circuit
• Headphone drive capability 50 mW
• 0dB, 10dB, 20dB, and 30dB microphone boost
capability
• V STAC9753 and +5 V STAC9752 analog
power supply options
• Pin compatible with the STAC9700, STAC9721,

STAC9756
• 100% pin compatible with STAC9750 and

STAC9766

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

V 101006

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

TABLE OF CONTENTS

PRODUCT BRIEF 7 Description 7 STAC9752/9753 Block Diagram 8 Key Specifications 8 Related Materials 9 Additional Support 9

CHARACTERISTICS AND SPECIFICATIONS Electrical Specifications 10 Absolute Maximum Ratings 10 Recommended Operation Conditions 10 Power Consumption 11 AC-Link Static Digital Specifications 12 STAC9752 5 V Analog Performance Characteristics 12 STAC9753 3.3V Analog Performance Characteristics AC Timing Characteristics 16 Cold Reset 16 Warm Reset 16 Clocks 17 STAC9752/9753 Crystal Elimination Circuit and Clock Frequencies Data Setup and Hold 18 Signal Rise and Fall Times 18 AC-Link Low Power Mode Timing 19 ATE Test Mode 19

TYPICAL CONNECTION DIAGRAM Slit Independent Power Supply Operation 21

CONTROLLER, CODEC AND AC-LINK AC-Link Physical Interface 23 Controller to Single CODEC 23 Controller to Multiple CODECs 25 Primary CODEC Addressing 25 Secondary CODEC Addressing 25 CODEC ID Strapping 26 Clocking for Multiple CODEC Implementations 26 STAC9752/9753 as a Primary CODEC 26 STAC9752/9753 as a Secondary CODEC 26 AC-Link Power Management 27 Powering down the AC-Link 27 Waking up the AC-Link 27 CODEC Reset 28

AC-LINK DIGITAL INTERFACE Overview 29 AC-Link Serial Interface Protocol 30 AC-Link Variable Sample Rate Operation 30 Variable Sample Rate Signaling Protocol 30 Primary and Secondary CODEC Register Addressing 32 AC-Link Output Frame SDATA_OUT 32 Slot 0 TAG / CODEC ID 34 Slot 1 Command Address Port 34 Slot 2 Command Data Port 35 Slot 3 PCM Playback Left Channel 35 Slot 4 PCM Playback Right Channel 35 Slot 5 Modem Line 1 Output Channel 35 Slot 6 - 11 DAC 35

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

Slot 12 Audio GPIO Control Channel 36 AC-Link Input Frame SDATA_IN 36

Slot 0 TAG Slot 1 Status Address Port / SLOTREQ signalling bits Slot 2 Status Data Port 38 Slot 3 PCM Record Left Channel 38 Slot 4 PCM Record Right Channel 38 Slot 5 Modem Line 1 ADC 38 Slot 6 - 9 ADC 38 Slots 7 & 8 Vendor Reserved 39 Slot 10 & 11 ADC 39 Slot 12 Reserved 39 AC-Link Interoperability Requirements and Recommendations 40 “Atomic slot” Treatment of Slot 1 Address and Slot 2 Data Slot Assignments for Audio 41 STAC9752/9753 MIXER FUNCTIONAL DIAGRAMS Analog Mixer Input 45 Mixer Analog Output 45 SPDIF Digital Mux PC Beep Implementation 46 Analog PC Beep 46 Digital PC Beep 46 PROGRAMMING REGISTERS Register Descriptions 48 Reset 00h 48 Master Volume Registers 02h 48 Headphone Volume Registers 04h 49 Master Volume MONO 06h 50 PC BEEP Volume 0Ah 51 Phone Volume Index 0Ch 51 Mic Volume Index 0Eh 52 LineIn Volume Index 10h 52 CD Volume Index 12h 53 Video Volume Index 14h 53 Aux Volume Index 16h 54 PCMOut Volume Index 18h 54 Record Select 1Ah 55 Record Gain 1Ch 55 General Purpose 20h 56 3D Control 22h 56 Audio Interrupt and Paging 24h 57 Powerdown Ctrl/Stat 26h 58 Extended Audio ID 28h 59 Extended Audio Control/Status 2Ah 61 PCM DAC Rate Registers 2Ch and 32h 63 PCM DAC Rate 2Ch 63 PCM LR ADC Rate 32h 63 SPDIF Control 3Ah 64 General Purpose Input & Outputs 64 EAPD 64 GPIO Pin Definitions 65 GPIO Pin Implementation 65 Extended Modem Status and Control Register 3Eh GPIO Pin Configuration Register 4Ch 66

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

LIST OF FIGURES

Figure Block Diagram 8 Figure Cold Reset Timing 16 Figure Warm Reset Timing 16 Figure Clocks Timing 17 Figure Data Setup and Hold Timing 18 Figure Signal Rise and Fall Times Timing 18 Figure AC-Link Low Power Mode Timing 19 Figure ATE Test Mode Timing 19 Figure Typical Connection Diagram 20 Figure Split Independent Power Supply Operation 22 Figure AC-Link to its Companion Controller 23 Figure CODEC Clock Source Detection 24 Figure STAC9752/9753 Powerdown Timing 27 Figure Bi-directional AC-Link Frame with Slot assignments 29 Figure AC-Link Audio Output Frame 33 Figure Start of an Audio Output Frame 33 Figure STAC9752/9753 Audio Input Frame 36 Figure Start of an Audio Input Frame 36 Figure Bi-directional AC-Link Frame with Slot assignments 41 Figure STAC9752 2-Channel Mixer Functional Diagram 44 Figure STAC9753 2-Channel Mixer Functional Diagram Figure Example of STAC9752/9753 Powerdown/Powerup flow Figure Powerdown/Powerup flow with analog still alive 81 Figure Pin Description Drawing 85 Figure Reflow Profile

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

LIST OF TABLES

Table Clock Mode Configuration 17 Table Common Clocks and Sources 18 Table Recommended CODEC ID strapping 26 Table AC-Link output slots transmitted from the Controller 29 Table The AC-Link input slots transmitted from the CODEC 30 Table VRA Behavior 31 Table Output Slot 0 Bit Definitions 34 Table Command Address Port Bit Assignments 35 Table Status Address Port Bit Assignments 37 Table Status Data Port Bit Assignments 38 Table Primary CODEC Addressing Slot 0 Tag Bits 40 Table Secondary CODEC Addressing Slot 0 Tag Bits 40 Table AC-Link Slot Definitions 41 Table AC-Link Input Slots Dedicated To Audio 41 Table Audio Interrupt Slot Definitions 42 Table Digital PC Beep Examples 46 Table Programming Registers 47 Table Extended Audio ID Register Functions 60 Table AMAP compliant 63 Table Hardware Supported Sample Rates 63 Table Supported Jack and Microphone Sense Functions Table Reg 68h Default Values 73 Table Gain or Attenuation Examples 73 Table Register 68h/Page 01h Bit Overview 73 Table Sensed Bits Outputs 75 Table Sensed Bits Inputs 75 Table Low Power Modes 80 Table CODEC ID Selection Table Secondary CODEC Register Access Slot 0 Bit Definitions Table Test Mode Activation Table ATE Test Mode Operation 84 Table Digital Connection Signals 86 Table Analog Connection Signals 87 Table Filtering and Voltage References 88 Table Power and Ground Signals 88

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

The STAC9752/9753 block diagram is illustrated in Figure The STAC9752/9753 provides variable sample rate Digital-to-Analog DA and Analog-to-Digital AD conversion, mixing, and analog processing. Supported audio sample rates include 48 KHz, KHz, 32 KHz, KHz, 16 KHz, KHz, and 8 KHz additional rates are supported in the STAC9752/9753 soft audio drivers. All ADCs and DACs operate at 20-bit resolution.

Two 20-bit DACs convert the digital stereo PCM_OUT content to audio. The MIXER block combines the PCM_OUT with any analog sources, to drive the LINE_OUT and HP_OUT outputs. The MONO_OUT delivers either microphone only, or a mono mix of sources from the MIXER. The stereo variable-sample-rate 20-bit ADCs provide record capability for any mix of mono or stereo sources, and deliver a digital stereo PCM-in signal back to the AC-Link. The microphone input and mono mix input can be recorded simultaneously, thus allowing for an all digital output in support of the digital ready initiative. For a digital ready record path, the microphone is connected to the left channel ADC while the mono output of the stereo mixer is connected to right channel ADC.

The STAC9752/9753 include jack sensing on the Headphone and Line_Out. The STAC9752/9753 jack sense can detect the presence of devices on the Headphone and Line Outputs and on both Microphone inputs. With proprietary IDT current and impedance-sensing techniques, the impedance load on the Headphone and Line Outputs can also be detected. The GPIOs on the STAC9752/9753 remain available for advanced configurations.

The STAC9752/9753 implementation of jack sense uses the Extended Paging Registers defined by the AC'97 Specification. This allows for additional registry space to hold the identification information about the CODEC, the jack sensing details and results, and the external surroundings of the CODEC. The information within the Extended Paging Registers will allow for the automatic configuration of the audio subsystem without end-user intervention. For example, the BIOS can populate the Extended Paging Registers with valuable information for both the audio driver and the operating system such as gain and attenuation stages, input population and input phase. With this input information, the IDT driver will automatically provide to the Volume Control Panel only the volume sliders that are implemented in the system, thus improving the end-user's experience with the PC.

The information in the Extended Paging Registers will also allow for automatic configuration of microphone inputs, the ability to switch between SPDIF and analog outputs, the routing of the mas-

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
ter volume slider to the proper physical output, and SoftEQ configurations. The fully parametric IDT SoftEQ can be initiated upon jack insertion and sensed impedance levels.

The STAC9752/9753 also offers 2 styles of PC BEEP Analog and Digital. The digital PC Beep is a new feature added to the AC’97 Specification Rev

The STAC9752/9753 is designed primarily to support stereo 2-speaker audio. True AC-3 playback can be achieved for 6-speaker applications by taking advantage of the multi-CODEC option available in the STAC9752/9753 to support multiple CODECs in an AC'97 architecture. Additionally, the STAC9752/9753 provides for a stereo enhancement feature, IDT Surround 3D SS3D . SS3D provides the listener with several options for improved speaker separation beyond the normal two- or four-speaker arrangements. The STAC9752/9753 can be and Windows Sound compatible when used with IDT’s WDM driver for Windows 98/2K/ME/XP or with Intel/Microsoft driver included with Windows 2K/ME/XP. SoundBlaster is a registered trademark of Creative Labs. Windows is a registered trademark of Microsoft Corporation.

STAC9752/9753 Block Diagram

AC-link SYNC

BIT_CLK SDATA_OUT

SDATA_IN RESET#

Multi-Codec CID0 CID1

EAPD

Variable Sample Rate 20-Bit DACs and 20-Bit ADCs

Figure Block Diagram

Power Management
4 stereo sources

PCM out DACs
2 mono sources

Stereo Mono

Digital Interface

MIXER

HP_OUT LINE_OUT

Registers 64x16 bits
ORDERING INFORMATION

Part Number STAC9752XXTAEyyX STAC9753XXTAEyyX

Package 48-pin RoHS QFP 7mm x 7mm x 1.4mm 48-pin RoHS QFP 7mm x 7mm x 1.4mm

Temp Range 0° C to +70° C 0° C to +70° C

Supply Range DVdd = 3.3V, AVdd = 5.0V DVdd = 3.3V, AVdd = 3.3V
Add an “R” to the end of the Part number for Tape and Reel delivery. Minimum order quantitiy is 2ku.

PACKAGE DRAWING
48 pin LQFP

Pin 1

LQFP Dimensions in mm

Key Min.

Nom.

Max.

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

SOLDER REFLOW PROFILE

Standard Reflow Profile Data

Note These devices can be hand soldered at 360 oC for 3 to 5 seconds. FROM IPC / JEDEC J-STD-020C “Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices”

Profile Feature

Pb Free Assembly

Average Ramp-Up Rate Tsmax - Tp

Preheat

Temperature Min Tsmin Temperature Max Tsmax

Time tsmin - tsmax

Time maintained above

Temperature TL Time tL

Peak / Classification Temperature Tp
3 oC / second max
150 oC 200 oC 60 - 180 seconds
217 oC 60 - 150 seconds

See “Package Classification Reflow Temperatures” on page

Time within 5 oC of actual Peak Temperature tp 20 - 40 seconds

Ramp-Down rate 6 oC / second max

Time 25 oC to Peak Temperature 8 minutes max

Note All temperatures refer to topside of the package, measured on the package body surface.

Figure Reflow Profile

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

Pb Free Process - Package Classification Reflow Temperatures

Package Type TQFP 48-pin

MSL 3

Reflow Temperature 260 oC*

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
Updated part ordering information to longer orderable part number related to previously issued PCN.

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

Innovate with IDT audio for high fidelity. Contact:

For Sales
800-345-7015 408-284-8200 Fax 408-284-2775

For Tech Support

Corporate Headquarters

Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 outside U.S.

Europe

IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE +44 1372 363 339
2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived STAC9753XXTAEB2XR Datasheet file may be downloaded here without warranties.

Datasheet ID: STAC9753XXTAEB2XR 637518