SCAN182373ASSC

SCAN182373ASSC Datasheet

SCAN182373A Transparent Latch with Series Resistor Outputs

Part	Datasheet
SCAN182373ASSC	SCAN182373ASSC (pdf)

Related Parts	Information
SCAN182373ASSCX	SCAN182373ASSCX

PDF Datasheet Preview
SCAN182373A Transparent Latch with Series Resistor Outputs SCAN182373A Transparent Latch with Series Resistor Outputs The SCAN182373A is a high performance BiCMOS transparent latch featuring separate data inputs organized into dual 9-bit bytes with byte-oriented latch enable and output enable control signals. This device is compliant with IEEE Standard Test Access Port and Boundary-Scan Architecture with the incorporation of the defined boundaryscan test logic and test access port consisting of Test Data Input TDI , Test Data Out TDO , Test Mode Select TMS , and Test Clock TCK . s IEEE JTAG Compliant s High performance BiCMOS technology s series resistor outputs eliminate need for external terminating resistors s Buffered active-low latch enable s 3-STATE outputs for bus-oriented applications s 25 mil pitch SSOP Shrink Small Outline Package s Includes CLAMP, IDCODE and HIGHZ instructions s Additional instructions SAMPLE-IN, SAMPLE-OUT and EXTEST-OUT s Power up 3-STATE for hot insert s Member of Fairchild’s SCAN Products Ordering Code: Order Number Package Number Package Description SCAN182373ASSC MS56A 56-Lead Shrink Small Outline Package SSOP , JEDEC MO-118, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names ALE, BLE AOE1, BOE1 Description Data Inputs Latch Enable Inputs 3-STATE Output Enable Inputs 3-STATE Latch Outputs 2000 Fairchild Semiconductor Corporation DS011544 SCAN182373A Truth Tables Inputs †AOE1 H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance AI X L H X Z L H AO0 Functional Description The SCAN182373A consists of two sets of nine D-type latches with 3-STATE standard outputs. When the Latch Enable ALE or BLE input is HIGH, data on the inputs or enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its input changes. When Latch Enable is LOW, the latches store the information that was present on Logic Diagram Inputs †BOE1 AO0 = Previous AO before H-to-L transition of ALE BO0 = Previous BO before H-to-L transition of BLE † = Inactive-to-active transition must occur to enable outputs upon power-up. the inputs a set-up time preceding the HIGH-to-LOW transition of the Latch Enable. The 3-STATE standard outputs are controlled by the Output Enable AOE1 or BOE1 input. When Output Enable is LOW, the standard outputs are in the 2-state mode. When Output Enable is HIGH, the standard outputs are in the high impedance mode, but this does not interfere with entering new data into the latches. Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. SCAN182373A Block Diagrams Byte-A Tap Controller Byte-B Note BSR stands for Boundary Scan Register. SCAN182373A Description of BOUNDARY-SCAN Circuitry The scan cells used in the BOUNDARY-SCAN register are one of the following two types depending upon their location. Scan cell TYPE1 is intended to solely observe system data, while TYPE2 has the additional ability to control system data. Scan cell TYPE 1 is located on each system input pin while scan cell TYPE2 is located at each system output pin as well as at each of the two internal active-high output enable signals. AOE controls the activity of the A-outputs while BOE controls the activity of the B-outputs. Each will activate their respective outputs by loading a logic high. The BYPASS register is a single bit shift register stage identical to scan cell TYPE1. It captures a fixed logic low. The INSTRUCTION register is an 8-bit register which captures the default value of SAMPLE/PRELOAD during the CAPTURE-IR instruction command. The benefit of capturing SAMPLE/PRELOAD as the default instruction during CAPTURE-IR is that the user is no longer required to shift in the 8-bit instruction for SAMPLE/PRELOAD. The sequence of CAPTURE-IR EXIT1-IR UPDATE-IR will update the SAMPLE/PRELOAD instruction. For more information refer to the section on instruction definitions. Instruction Register Scan Chain Definition Bypass Register Scan Chain Definition Logic 0 SCAN182373A Product IDCODE 32-Bit Code per IEEE Version Entity Part Manufacturer Required by Number 0000 MSB LSB Instruction Code 01000010 00100010 10101010 All Others Instruction EXTEST SAMPLE/PRELOAD CLAMP HIGH-Z

PDF Datasheet Preview

SCAN182373A Transparent Latch with Series Resistor Outputs

SCAN182373A Transparent Latch with Series Resistor Outputs

The SCAN182373A is a high performance BiCMOS transparent latch featuring separate data inputs organized into dual 9-bit bytes with byte-oriented latch enable and output enable control signals. This device is compliant with IEEE Standard Test Access Port and Boundary-Scan Architecture with the incorporation of the defined boundaryscan test logic and test access port consisting of Test Data Input TDI , Test Data Out TDO , Test Mode Select TMS , and Test Clock TCK .
s IEEE JTAG Compliant s High performance BiCMOS technology s series resistor outputs eliminate need for external
terminating resistors s Buffered active-low latch enable s 3-STATE outputs for bus-oriented applications s 25 mil pitch SSOP Shrink Small Outline Package s Includes CLAMP, IDCODE and HIGHZ instructions s Additional instructions SAMPLE-IN, SAMPLE-OUT and

EXTEST-OUT s Power up 3-STATE for hot insert s Member of Fairchild’s SCAN Products
Ordering Code:

Order Number

Package Number

Package Description

SCAN182373ASSC

MS56A
56-Lead Shrink Small Outline Package SSOP , JEDEC MO-118, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

Pin Names ALE, BLE AOE1, BOE1

Description Data Inputs Latch Enable Inputs 3-STATE Output Enable Inputs 3-STATE Latch Outputs
2000 Fairchild Semiconductor Corporation DS011544

SCAN182373A

Truth Tables

Inputs
†AOE1

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance

AI X L H X

Z L H AO0

Functional Description

The SCAN182373A consists of two sets of nine D-type latches with 3-STATE standard outputs. When the Latch Enable ALE or BLE input is HIGH, data on the inputs or enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its input changes. When Latch Enable is LOW, the latches store the information that was present on

Logic Diagram

Inputs †BOE1

AO0 = Previous AO before H-to-L transition of ALE BO0 = Previous BO before H-to-L transition of BLE † = Inactive-to-active transition must occur to enable outputs upon power-up.
the inputs a set-up time preceding the HIGH-to-LOW transition of the Latch Enable. The 3-STATE standard outputs are controlled by the Output Enable AOE1 or BOE1 input. When Output Enable is LOW, the standard outputs are in the 2-state mode. When Output Enable is HIGH, the standard outputs are in the high impedance mode, but this does not interfere with entering new data into the latches.

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

SCAN182373A

Block Diagrams

Byte-A

Tap Controller

Byte-B

Note BSR stands for Boundary Scan Register.

SCAN182373A

Description of BOUNDARY-SCAN Circuitry

The scan cells used in the BOUNDARY-SCAN register are one of the following two types depending upon their location. Scan cell TYPE1 is intended to solely observe system data, while TYPE2 has the additional ability to control system data.

Scan cell TYPE 1 is located on each system input pin while scan cell TYPE2 is located at each system output pin as well as at each of the two internal active-high output enable signals. AOE controls the activity of the A-outputs while BOE controls the activity of the B-outputs. Each will activate their respective outputs by loading a logic high.

The BYPASS register is a single bit shift register stage identical to scan cell TYPE1. It captures a fixed logic low.

The INSTRUCTION register is an 8-bit register which captures the default value of SAMPLE/PRELOAD during the CAPTURE-IR instruction command. The benefit of capturing SAMPLE/PRELOAD as the default instruction during CAPTURE-IR is that the user is no longer required to shift in the 8-bit instruction for SAMPLE/PRELOAD. The sequence of CAPTURE-IR EXIT1-IR UPDATE-IR will update the SAMPLE/PRELOAD instruction. For more information refer to the section on instruction definitions.

Instruction Register Scan Chain Definition

Bypass Register Scan Chain Definition Logic 0

SCAN182373A Product IDCODE 32-Bit Code per IEEE

Version Entity Part Manufacturer Required by

Number
0000

MSB LSB Instruction Code 01000010 00100010 10101010 All Others

Instruction EXTEST

SAMPLE/PRELOAD CLAMP HIGH-Z

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived SCAN182373ASSC Datasheet file may be downloaded here without warranties.

Datasheet ID: SCAN182373ASSC 634701