IDT82V8313BB

IDT82V8313BB Datasheet

VOLT M13 MULTIPLEXER IDT82V8313

Part	Datasheet
IDT82V8313BB	IDT82V8313BB (pdf)

Related Parts	Information
IDT82V8313DS	IDT82V8313DS
IDT82V8313DSG	IDT82V8313DSG

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VOLT M13 MULTIPLEXER IDT82V8313 Version 3 June 3, 2004 2975 Stender Way, Santa Clara, California 95054 Telephone 800 345-7015 • • FAX 408 492-8674 Printed in U.S.A. 2004 Integrated Device Technology, Inc. DISCLAIMER Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc. LIFE SUPPORT POLICY Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of IDT. Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Table of Contents PACKAGE 2-4 PIN 5-12 REGISTER MEMORY MAP 13-16 REGISTER DESCRIPTIONS 17 Table of Contents Notice The information in this document is subject to change without notice June 3, 2004 IDT82V8313 VOLT M13 MULTIPLEXER RFDL TSB Interrupt Control/Status 35 RFDL TSB Status 36 RFDL TSB Receive 36 MX23 Configuration 37 DeMux AIS Insert Register 38 MX23 MUX AIS Insert Register 38 MX23 Loopback Activate 39 MX23 Loopback Request Insert Register 39 MX23 Loopback Request Detect 40 MX23 Loopback Request Interrupt 40 FEAC XBOC TSB 41 RBOC Configuration/Interrupt 41 RBOC Interrupt 42 DS3 FRMR Configuration 43 DS3 FRMR Interrupt Enable ACE=0 44 DS3 FRMR Additional Configuration Register ACE=1 45 DS3 FRMR Interrupt 46 DS3 FRMR Status 47 DS2 FRMR Configuration 48 DS2 FRMR Interrupt 49 DS2 Framer Interrupt 50 DS2 Framer Status 51 DS2 Framer Monitor Interrupt 52 DS2 FRMR FERR Count 52 DS2 FRMR PERR Count 53 DS2 FRMR PERR Count 53 MX12 Configuration And Control 54 MX12 Loopback Code Select Register 55 MX12 AIS Insert Register 56 MX12 Loopback Activate 56 MX12 Loopback Interrupt Register 57 DS1 Transmit And Receive Edge Select 57 FUNCTIONAL 59-78 DATA LINK 79-92 FUNCTIONAL TIMING 93-94 LOOPBACK 95-100 DC ELECTRICAL CHARACTERISTICS 101-102 Absolute Maximum Ratings 101 Recommended Operating Conditions 1 101 DC Electrical Characteristics 102 Table of Contents Notice The information in this document is subject to change without notice June 3, 2004 IDT82V8313 VOLT M13 MULTIPLEXER AC ELECTRICAL CHARACTERISTICS 103-114 Microprocesser Interface Timing Characteristics/Microprocessor Read Access 103 Microprocessor Write Access 104 Timing Characteristics 105 Transmit DS3 Input 106 Transmit Overhead input 106 Transmit Tributary Input 107 Transmit Data Link 107 Transmit Data Link EOM 108 Transmit DS3 Output 109 Receive DS3 Output Receive Overhead Output Transmit Overhead Output Receive Tributary Output Receive Data Link JTAG 115-120 JTAG Timing JTAG AC Electrical Identification Register Scan Register System Interface Parameters JTAG Scan 118-120 ORDERING INFORMATION 121 GLOSSARY 123-126 127-128 INDEX 129-130 Table of Contents Notice The information in this document is subject to change without notice June 3, 2004 IDT82V8313 VOLT M13 MULTIPLEXER Table of Contents Notice The information in this document is subject to change without notice June 3, 2004 List of Tables Table 1 Pin Descriptions 5-11 Table 2 Register Memory Map 13-16 Table 3 FERF Status X1 & X2 62 Table 4 C-Bit Parity Mode DS3 C-Bit 63 Table 5 DS3 FEAC Loopback Control Message 65 Table 6 DS3 FEAC Alarm and Status 65 Table 7 DS1 Bit Oriented Codes Command and Response 67 Table 8 DS1 Bit Oriented Priority 67 Table 9 DS1 Bit Oriented Codes Reserved Messages 67 Table 10 Data Link 68 Table 11 Max Jitter Tolerance on DS if CAT 70 List of Tables Notice The information in this document is subject to change without notice June 3, 2004 IDT82V8313 VOLT M13 MULTIPLEXER List of Tables Notice The information in this document is subject to change without notice June 3, 2004 List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 DS3 Framer 59 DS3 Frame 59 B3ZS Coding 60 Transmit BOC 66 Receive BOC 66 Jitter Definition 69 Maximum Jitter Tolerance on DSn Interface 70 M23 Multiplexer 71 DS3 Stuff 72 DS2 Framer 73 DS2 Frame 73 G.747 Frame Format 74 M12 Block 77 DS2 Stuff 78 79 XFDL Polled 80 XFDL Interrupt Mode 81 XFDL Interrupt Service 81 XFDL DMA 82 XFDL Normal Data Sequence 83 XFDL Underrun 84 TDLINT Timing Normal Data 85 TDLEOMI Timing EOMI After 86 RFDL 87 RFDL Polled 88 RFDL Interrupt Driven 89 RFDL Interrupt Service 89 RFDL DMA 90 RFDL Normal Data And Abort Sequence 91 Receive DS3 OH Serial 93 Transmit DS3 OH Serial 93 Functional Receive OH Timing 93 Functional Receive Timing 94 Functional Receive OH Timing High-Speed 94 DS3 Diagnostic 96 DS3 Line Loopback 97 DS2/G.747 Demultiplex 98 DS1/E1 Demultiplex Loopback 99 Microprocessor Read Access Timing 103 Microprocessor Write Access 104 Receive DS3 Input Timing 105 Transmit DS3 Input Timing 106 Transmit Overhead Input Timing 106 Transmit Tributary Input 107 Transmit Data Link Input 107 List of Figures viii Notice The information in this document is subject to change without notice June 3, 2004 IDT82V8313 VOLT M13 MULTIPLEXER Figure 46 Figure 47 Figure 48 Figure 49 Figure 50 Figure 51 Figure 52 Figure 53 Transmit Data Link EOM Input 108 Transmit DS3 Output Timing 109 Receive DS3 Output Timing 110 Receive Overhead Output Timing 111 Transmit Overhead Output Timing 112 Receive Tributary Output Timing 112 Receive Data Output Link Output Timing 113 Standad JTAG Timing 115 List of Figures viii Notice The information in this document is subject to change without notice June 3, 2004 VOLT M13 MULTIPLEXER IDT82V8313 FEATURES: Full featured single chip M13-ideal for upgrading existing multi-line T1/E1 line cards to single line channelized T3 service ORDERING INFORMATION Device Type XX Package VOLT M13 MULTIPLEXER Process/ Temperature Range BLANK Commercial -40°C to +85°C Plastic Quad Flatpack PQFP, DS208-1 Plastic Ball Grid Array PBGA, BB208-1 82V8313 3.3V M13 Multiplexer 6143 drw18 Datasheet Document History 12/15/2003 Pgs. 1 thru 130 03/15/2004 Pgs. 3 and 06/03/2004 Pgs. 101, 102 and CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES 800-345-7015 or 408-727-5116 fax 408-492-8674 ORDERING INFORMATION The IDT logo is a registered trademark of Integrated Device Technology, Inc. Notice The information in this document is subject to change without notice for Tech Support 408-330-1552 June 3, 2004 IDT82V8313 VOLT M13 MULTIPLEXER ORDERING INFORMATION Notice The information in this document is subject to change without notice June 3, 2004 STANDARDS American National Standards Institute ANSI ANSI T1.101 1994 Synchronization Interface Standard. ANSI T1.102 1993 Digital Hierarchy Electrical Interfaces. ANSI T1.107 1995 Digital Hierarchy Formats Specifications. ANSI T1.231 1997 Digital Hierarchy Layer1 In-Service Digital Transmission Performance Monitoring. ANSI T1.403 1995 Network-to-Customer Installation Ds1 Metallic Interface. ANSI T1.404 1994 Network-to-Customer Installation Ds3 Metallic Interface Specification Bell Communications Research Bellcore Issue 1, 05/1986 Asynchronous Digital Multiplexes - Requirements and Objectives. TR-NWT-000170 Issue 2, 01/1993 Digital Cross-Connect System Generic Requirements and Objectives. TR-NWT-000233 Issue 3, 11/1993 Wideband and Broadband Digital Cross-Connect Systems Generic Criteria. TR-NWT-001112 Issue 1, 06/1993 Broadband-ISDN User to Network Interface and Network Node Interface Physical Layer Generic Criteria. GR-499-CORE Issue 2, 12/1998 Transport Systems Generic Requirements TSGR Common Requirements. GR-820-CORE Issue 2, 12/1997 Generic Digital Transmission Surveillance A module of OTGR, FR-439 . GR-1244-CORE - Issue 1, 06/1995 Clocks for the Synchronized Network Common Generic Criteria International Telecommunication Union ITU-T Recommendation G.703 04/91 Physical/electrical characteristics oh hierarchical digitalinterfaces Recommendation G.704 07/95 Synchronous frame structures used at 1544, 6312, 2048, 8488 and 44 736 kbit/s hierarchical levels Recommendation G.706 04/91 Frame alignment and cyclic redundancy check CGC procedures relating to basic frame structures defined in Recommendation G.704 Recommendation G.747 1988 Second order digital multiplex equipment operating at 6312 kbit/s and multiplexing three tributaries at 2048 kbit/s Recommendation G.752 1988 Characteristics of digital multiplex equipment based on a second order bit rate of 6312 kbit/s and using positive justification Recommendation G.824 03/93 The control of jitter and wander within digital networks which are based on the 1544 kbit/s hierarchy Recommendation M.20 10/92 Maintenance and Philosophy for telecommunication networks Recommendation O.150 05/96 General requirements for instrumentation for performance measurements on digital transmission equipment Recommendation O.151 10/92 Error performance measuring equipment operating at the primary rate and above Recommendation O.152 10/92 Error performance measuring equipment for bit rates of 64 kbit/s and N x 64 kbit/s signals Recommendation O.153 10/92 Basic parameters for the measurement of error performance at bit rates below the primary rate Recommendation Q.921 03/93 ISDN user-network interface Data link layer specification Standards Notice The information in this document is subject to change without notice June 3, 2004 IDT82V8313 Network Working Group RFC 2495 01/99 Definitions of Managed Objects for the Ds1, E1, Ds2 and E2 Interface Types. Other documents T1 Basics Telecommunications Techniques Corporation - TTC The Fundamentals of Ds3 1992 Telecommunications Techniques Corporation - TTC VOLT M13 MULTIPLEXER STANDARDS Notice The information in this document is subject to change without notice June 3, 2004 GLOSSARY ADM AIC AIS-CI AISS AMI ANSI B-DCS BER BERT BITS BnZS BOC BPV C/R CAS-BR CAS-CC CCS CFA CGA CI COFA CP CRC CS CSS CSU CV Add / Drop Multiplexer Application Identification Alarm Indication Singnal Alarm Indication Signal - Customer Installation AIS Second Alternate Mark Inversion American National Standards Institute Broadband DCS Bit Error Rate Bit Error Rate Testing Building Integrated Timing Source or Supply Bipolar with n zero Substitution n = 3 for Ds3 and 8 for Ds1 level Bit Oriented Code Bipolar Violation Command / Response Channel Associated Signaling - Bit Robbing signaling distributed in each Ds0 Channel Associated Signaling - Common Channel in timeslot 24 in T1 channel Composite Clock Common Channel Signaling Carrier Failure Alarm Carrier Group Alarm Customer Installation Change of Frame Alignment Parity bit instead of stuffing indicator in Ds3 C-bit parity mode Cyclical Redundancy Check Controlled Slip Controlled Slip Second Customer Service Unit Code Violation GLOSSARY Notice The information in this document is subject to change without notice June 3, 2004 IDT82V8313 CVCP CVP DCS Dsx EA EDF EIC EOM ERR ES ESA ESACP ESAP ESB ESBCP ESBP ESCP ESP EXZ EXZS FAS FC FCS FDL FEAC FEBE FEPR FERF FIC GPS HDB3 HDLC HSSL IDL "Code Violation, CP-bit" "Code Violation, P-bit" Digital Cross-connect System "Digital Signal hierarchy, level x" Extension Address field Extended Superframe Format Equipment Identification Channel End of Message Error Errored Second "Errored Second, type A" "Errored Second, type A, CP-bit" "Errored Second, type A, P-bit" "Errored Second, type B" "Errored Second, type B, CP-bit" "Errored Second, type B, P-bit" "Errored Second, CP-bit" "Errored Second, P-bit" Excessive Zeros Excessive Zero Suppression Frame Alignment Signal Failure Count Frame Check Sequence Facility Data Link Far End Alarm and Control Channel Far End Block Error Far End Performance Report Far End Receive Failure Fast Information Channel General Positioning System High Density Bipolar Three High Level Data Link Control High Speed Serial Link Idle Pattern VOLT M13 MULTIPLEXER GLOSSARY Notice The information in this document is subject to change without notice June 3, 2004 IDT82V8313 ISDN ISID ITU L LAPD LCV LFE LIC LIU LOD LOF LOS MART MDL MOP NE NP NPFE NPRM OC-n OOF P PER PFE PID PM POL PRM PRS PS PSC PSD PTE RAI Integrated Services Digital Network Idle Signal Identification International Telecommunication Union Line Link Access Protocol on the D Channel Line Code Violation Line Far End Location Identification Channel Line Interface Unit Loss of Data Loss of Frame Loss of Signal Maximum Average Reframe Time Maintenance Data Link Message Oriented Protocol Network Element Network Path Network Path Network Performance Report Message Optical Carrier level n Out of Frame Path Parity Error Ratio Path Far End Path Identification Performance Monitoring Polarity Performance Report Message Primary Reference Source Protection Switching Protection Switching Count Protection Switching Duration Path Terminating Equipment Remote Alarm Indication VOLT M13 MULTIPLEXER GLOSSARY *Notice The information in this document is subject to change without notice

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VOLT M13 MULTIPLEXER IDT82V8313

Version 3 June 3, 2004
2975 Stender Way, Santa Clara, California 95054 Telephone 800 345-7015
•
• FAX 408 492-8674

Printed in U.S.A. 2004 Integrated Device Technology, Inc.

DISCLAIMER Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc.

LIFE SUPPORT POLICY Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of IDT. Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

Table of Contents

PACKAGE 2-4

PIN 5-12

REGISTER MEMORY MAP 13-16

REGISTER DESCRIPTIONS 17

Table of Contents
*Notice The information in this document is subject to change without notice

June 3, 2004

IDT82V8313

VOLT M13 MULTIPLEXER

RFDL TSB Interrupt Control/Status 35 RFDL TSB Status 36 RFDL TSB Receive 36 MX23 Configuration 37 DeMux AIS Insert Register 38 MX23 MUX AIS Insert Register 38 MX23 Loopback Activate 39 MX23 Loopback Request Insert Register 39 MX23 Loopback Request Detect 40 MX23 Loopback Request Interrupt 40 FEAC XBOC TSB 41 RBOC Configuration/Interrupt 41 RBOC Interrupt 42 DS3 FRMR Configuration 43 DS3 FRMR Interrupt Enable ACE=0 44 DS3 FRMR Additional Configuration Register ACE=1 45 DS3 FRMR Interrupt 46 DS3 FRMR Status 47 DS2 FRMR Configuration 48 DS2 FRMR Interrupt 49 DS2 Framer Interrupt 50 DS2 Framer Status 51 DS2 Framer Monitor Interrupt 52 DS2 FRMR FERR Count 52 DS2 FRMR PERR Count 53 DS2 FRMR PERR Count 53 MX12 Configuration And Control 54 MX12 Loopback Code Select Register 55 MX12 AIS Insert Register 56 MX12 Loopback Activate 56 MX12 Loopback Interrupt Register 57 DS1 Transmit And Receive Edge Select 57

FUNCTIONAL 59-78

DATA LINK 79-92

FUNCTIONAL TIMING 93-94

LOOPBACK 95-100

DC ELECTRICAL CHARACTERISTICS 101-102

Absolute Maximum Ratings 101 Recommended Operating Conditions 1 101 DC Electrical Characteristics 102

Table of Contents
*Notice The information in this document is subject to change without notice

June 3, 2004

IDT82V8313

VOLT M13 MULTIPLEXER

AC ELECTRICAL CHARACTERISTICS 103-114

Microprocesser Interface Timing Characteristics/Microprocessor Read Access 103 Microprocessor Write Access 104 Timing Characteristics 105 Transmit DS3 Input 106 Transmit Overhead input 106 Transmit Tributary Input 107 Transmit Data Link 107 Transmit Data Link EOM 108 Transmit DS3 Output 109 Receive DS3 Output Receive Overhead Output Transmit Overhead Output Receive Tributary Output Receive Data Link

JTAG 115-120

JTAG Timing JTAG AC Electrical Identification Register Scan Register System Interface Parameters JTAG Scan 118-120
ORDERING INFORMATION 121

GLOSSARY 123-126
127-128

INDEX 129-130

Table of Contents
*Notice The information in this document is subject to change without notice

June 3, 2004

IDT82V8313

VOLT M13 MULTIPLEXER

Table of Contents
*Notice The information in this document is subject to change without notice

June 3, 2004

List of Tables

Table 1 Pin Descriptions 5-11 Table 2 Register Memory Map 13-16 Table 3 FERF Status X1 & X2 62 Table 4 C-Bit Parity Mode DS3 C-Bit 63 Table 5 DS3 FEAC Loopback Control Message 65 Table 6 DS3 FEAC Alarm and Status 65 Table 7 DS1 Bit Oriented Codes Command and Response 67 Table 8 DS1 Bit Oriented Priority 67 Table 9 DS1 Bit Oriented Codes Reserved Messages 67 Table 10 Data Link 68 Table 11 Max Jitter Tolerance on DS if CAT 70

List of Tables
*Notice The information in this document is subject to change without notice

June 3, 2004

IDT82V8313

VOLT M13 MULTIPLEXER

List of Tables
*Notice The information in this document is subject to change without notice

June 3, 2004

List of Figures

Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45

DS3 Framer 59 DS3 Frame 59 B3ZS Coding 60 Transmit BOC 66 Receive BOC 66 Jitter Definition 69 Maximum Jitter Tolerance on DSn Interface 70 M23 Multiplexer 71 DS3 Stuff 72 DS2 Framer 73 DS2 Frame 73 G.747 Frame Format 74 M12 Block 77 DS2 Stuff 78 79 XFDL Polled 80 XFDL Interrupt Mode 81 XFDL Interrupt Service 81 XFDL DMA 82 XFDL Normal Data Sequence 83 XFDL Underrun 84 TDLINT Timing Normal Data 85 TDLEOMI Timing EOMI After 86 RFDL 87 RFDL Polled 88 RFDL Interrupt Driven 89 RFDL Interrupt Service 89 RFDL DMA 90 RFDL Normal Data And Abort Sequence 91 Receive DS3 OH Serial 93 Transmit DS3 OH Serial 93 Functional Receive OH Timing 93 Functional Receive Timing 94 Functional Receive OH Timing High-Speed 94 DS3 Diagnostic 96 DS3 Line Loopback 97 DS2/G.747 Demultiplex 98 DS1/E1 Demultiplex Loopback 99 Microprocessor Read Access Timing 103 Microprocessor Write Access 104 Receive DS3 Input Timing 105 Transmit DS3 Input Timing 106 Transmit Overhead Input Timing 106 Transmit Tributary Input 107 Transmit Data Link Input 107

List of Figures
viii
*Notice The information in this document is subject to change without notice

June 3, 2004

IDT82V8313

VOLT M13 MULTIPLEXER

Figure 46 Figure 47 Figure 48 Figure 49 Figure 50 Figure 51 Figure 52 Figure 53

Transmit Data Link EOM Input 108 Transmit DS3 Output Timing 109 Receive DS3 Output Timing 110 Receive Overhead Output Timing 111 Transmit Overhead Output Timing 112 Receive Tributary Output Timing 112 Receive Data Output Link Output Timing 113 Standad JTAG Timing 115

List of Figures
viii
*Notice The information in this document is subject to change without notice

June 3, 2004

VOLT M13 MULTIPLEXER

IDT82V8313

FEATURES:

Full featured single chip M13-ideal for upgrading existing multi-line T1/E1 line cards to single line channelized T3 service
ORDERING INFORMATION

Device Type

XX Package

VOLT M13 MULTIPLEXER

Process/ Temperature

Range

BLANK

Commercial -40°C to +85°C

Plastic Quad Flatpack PQFP, DS208-1

Plastic Ball Grid Array PBGA, BB208-1
82V8313 3.3V M13 Multiplexer
6143 drw18

Datasheet Document History
12/15/2003

Pgs. 1 thru 130
03/15/2004

Pgs. 3 and
06/03/2004

Pgs. 101, 102 and

CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES 800-345-7015 or 408-727-5116 fax 408-492-8674
ORDERING INFORMATION

The IDT logo is a registered trademark of Integrated Device Technology, Inc.
*Notice The information in this document is subject to change without notice
for Tech Support 408-330-1552

June 3, 2004

IDT82V8313

VOLT M13 MULTIPLEXER
ORDERING INFORMATION
*Notice The information in this document is subject to change without notice

June 3, 2004

STANDARDS

American National Standards Institute ANSI

ANSI T1.101 1994 Synchronization Interface Standard. ANSI T1.102 1993 Digital Hierarchy Electrical Interfaces. ANSI T1.107 1995 Digital Hierarchy Formats Specifications. ANSI T1.231 1997 Digital Hierarchy Layer1 In-Service Digital Transmission Performance Monitoring. ANSI T1.403 1995 Network-to-Customer Installation Ds1 Metallic Interface. ANSI T1.404 1994 Network-to-Customer Installation Ds3 Metallic Interface Specification

Bell Communications Research Bellcore

Issue 1, 05/1986 Asynchronous Digital Multiplexes - Requirements and Objectives. TR-NWT-000170 Issue 2, 01/1993 Digital Cross-Connect System Generic Requirements and Objectives. TR-NWT-000233 Issue 3, 11/1993 Wideband and Broadband Digital Cross-Connect Systems Generic Criteria. TR-NWT-001112 Issue 1, 06/1993 Broadband-ISDN User to Network Interface and Network Node Interface Physical Layer Generic Criteria. GR-499-CORE Issue 2, 12/1998 Transport Systems Generic Requirements TSGR Common Requirements. GR-820-CORE Issue 2, 12/1997 Generic Digital Transmission Surveillance A module of OTGR, FR-439 . GR-1244-CORE - Issue 1, 06/1995 Clocks for the Synchronized Network Common Generic Criteria

International Telecommunication Union ITU-T

Recommendation G.703 04/91 Physical/electrical characteristics oh hierarchical digitalinterfaces Recommendation G.704 07/95 Synchronous frame structures used at 1544, 6312, 2048, 8488 and 44 736 kbit/s hierarchical levels Recommendation G.706 04/91 Frame alignment and cyclic redundancy check CGC procedures relating to basic frame structures defined in Recommendation G.704 Recommendation G.747 1988 Second order digital multiplex equipment operating at 6312 kbit/s and multiplexing three tributaries at 2048 kbit/s Recommendation G.752 1988 Characteristics of digital multiplex equipment based on a second order bit rate of 6312 kbit/s and using positive justification Recommendation G.824 03/93 The control of jitter and wander within digital networks which are based on the 1544 kbit/s hierarchy Recommendation M.20 10/92 Maintenance and Philosophy for telecommunication networks Recommendation O.150 05/96 General requirements for instrumentation for performance measurements on digital transmission equipment Recommendation O.151 10/92 Error performance measuring equipment operating at the primary rate and above Recommendation O.152 10/92 Error performance measuring equipment for bit rates of 64 kbit/s and N x 64 kbit/s signals Recommendation O.153 10/92 Basic parameters for the measurement of error performance at bit rates below the primary rate Recommendation Q.921 03/93 ISDN user-network interface Data link layer specification

Standards
*Notice The information in this document is subject to change without notice

June 3, 2004

IDT82V8313

Network Working Group

RFC 2495 01/99 Definitions of Managed Objects for the Ds1, E1, Ds2 and E2 Interface Types.

Other documents

T1 Basics Telecommunications Techniques Corporation - TTC The Fundamentals of Ds3 1992 Telecommunications Techniques Corporation - TTC

VOLT M13 MULTIPLEXER

STANDARDS
*Notice The information in this document is subject to change without notice

June 3, 2004

GLOSSARY

ADM AIC AIS-CI AISS AMI ANSI B-DCS BER BERT BITS BnZS BOC BPV C/R CAS-BR CAS-CC CCS CFA CGA CI COFA CP CRC CS CSS CSU CV

Add / Drop Multiplexer Application Identification Alarm Indication Singnal Alarm Indication Signal - Customer Installation AIS Second Alternate Mark Inversion American National Standards Institute Broadband DCS Bit Error Rate Bit Error Rate Testing Building Integrated Timing Source or Supply Bipolar with n zero Substitution n = 3 for Ds3 and 8 for Ds1 level Bit Oriented Code Bipolar Violation Command / Response Channel Associated Signaling - Bit Robbing signaling distributed in each Ds0 Channel Associated Signaling - Common Channel in timeslot 24 in T1 channel Composite Clock Common Channel Signaling Carrier Failure Alarm Carrier Group Alarm Customer Installation Change of Frame Alignment Parity bit instead of stuffing indicator in Ds3 C-bit parity mode Cyclical Redundancy Check Controlled Slip Controlled Slip Second Customer Service Unit Code Violation

GLOSSARY
*Notice The information in this document is subject to change without notice

June 3, 2004

IDT82V8313

CVCP CVP DCS Dsx EA EDF EIC EOM ERR ES ESA ESACP ESAP ESB ESBCP ESBP ESCP ESP EXZ EXZS FAS FC FCS FDL FEAC FEBE FEPR FERF FIC GPS HDB3 HDLC HSSL IDL
"Code Violation, CP-bit" "Code Violation, P-bit" Digital Cross-connect System "Digital Signal hierarchy, level x" Extension Address field Extended Superframe Format Equipment Identification Channel End of Message Error Errored Second "Errored Second, type A" "Errored Second, type A, CP-bit" "Errored Second, type A, P-bit" "Errored Second, type B" "Errored Second, type B, CP-bit" "Errored Second, type B, P-bit" "Errored Second, CP-bit" "Errored Second, P-bit" Excessive Zeros Excessive Zero Suppression Frame Alignment Signal Failure Count Frame Check Sequence Facility Data Link Far End Alarm and Control Channel Far End Block Error Far End Performance Report Far End Receive Failure Fast Information Channel General Positioning System High Density Bipolar Three High Level Data Link Control High Speed Serial Link Idle Pattern

VOLT M13 MULTIPLEXER

GLOSSARY
*Notice The information in this document is subject to change without notice

June 3, 2004

IDT82V8313

ISDN ISID ITU L LAPD LCV LFE LIC LIU LOD LOF LOS MART MDL MOP NE NP NPFE NPRM OC-n OOF P PER PFE PID PM POL PRM PRS PS PSC PSD PTE RAI

Integrated Services Digital Network Idle Signal Identification International Telecommunication Union Line Link Access Protocol on the D Channel Line Code Violation Line Far End Location Identification Channel Line Interface Unit Loss of Data Loss of Frame Loss of Signal Maximum Average Reframe Time Maintenance Data Link Message Oriented Protocol Network Element Network Path Network Path Network Performance Report Message Optical Carrier level n Out of Frame Path Parity Error Ratio Path Far End Path Identification Performance Monitoring Polarity Performance Report Message Primary Reference Source Protection Switching Protection Switching Count Protection Switching Duration Path Terminating Equipment Remote Alarm Indication

VOLT M13 MULTIPLEXER

GLOSSARY
*Notice The information in this document is subject to change without notice

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IDT82V8313BB Datasheet file may be downloaded here without warranties.

Datasheet ID: IDT82V8313BB 637395