IDT74LVCHR16646APAG8
IDT74LVCHR16646APAG8 Datasheet
IDT74LVCHR16646A 3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER WITH 3-STATE OUTPUTS
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IDT74LVCHR16646APAG8 |
IDT74LVCHR16646APAG8 (pdf) |
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IDT74LVCHR16646APAG |
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| IDT74LVCHR16646A 3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 16-BIT BUS IDT74LVCHR16646A TRANSCEIVER/REGISTER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD FEATURES: • Typical tSK o Output Skew < 250ps • ESD > 2000V per MIL-STD-883, Method 3015 > 200V using machine model C = 200pF, R = 0 • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • CMOS power levels W typ. static • All inputs, outputs, and I/O are 5V tolerant • Supports hot insertion • Available in SSOP, TSSOP, and TVSOP packages DRIVE FEATURES: • Balanced Output Drivers ±12mA • Low switching noise APPLICATIONS: • 5V and 3.3V mixed voltage systems • Data communication and telecommunication systems DESCRIPTION: The LVCHR16646A 16-bit transceiver/register is built using advanced dual metal CMOS technology. This high-speed, low power device is organized as two independent 8-bit D-type transceivers with 3-state D-type registers. The controls circuitry is organized for multiplexed transmission of data between A bus and B bus either directly or from the internal storage registers. Each 8-bit transceiver/register features direction control DIR , over-riding Output Enable control OE and Select lines SAB and SBA to select either real-time data or stored data. Separate clock inputs are provided for A and B port registers. Data on the A or B data bus, or both, can be stored in the internal registers by the low-to-high transitions at the appropriate clock pins. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. All pins can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V supply system. The LVCHR16646A has series resistors in the device output structure which will significantly reduce line noise when used with light loads. This driver has been developed to drive ±12mA at the designated threshold levels. The LVCHR16646A has “bus-hold” which retains the inputs’ last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors FUNCTIONAL BLOCK DIAGRAM 1DIR 1 1CLKBA 55 1SBA 1CLKAB 1SAB A REG D C B REG D 2DIR 2CLKBA 28 30 2SBA 2CLKAB 2SAB 52 1B1 2A1 15 A REG D C B REG D 42 2B1 TO SEVEN OTHER CHANNELS TO SEVEN OTHER CHANNELS The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE 1999 Integrated Device Technology, Inc. OCTOBER 1999 ORDERING INFORMATION IDT XX LVC X XXXX Temp. Range Bus-Hold Family Device Type Package INDUSTRIAL TEMPERATURE RANGE PV PA PF 646A Shrink Small Outline Package Thin Shrink Small Outline Package Thin Very Small Outline Package 16-Bit Transceiver/Register with 3-State Outputs, 5 Volt Tolerant I/O R16 Double-Density, ±12mA H Bus-hold 74 -40°C to +85°C CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES 800-345-7015 or 408-727-6116 fax 408-492-8674 for Tech Support 408 654-6459 |
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