ICS1893CYI-10LFT

ICS1893CYI-10LFT Datasheet

ICS1893CY-10

Part	Datasheet
ICS1893CYI-10LFT	ICS1893CYI-10LFT (pdf)

Related Parts	Information
ICS1893CYI-10LF	ICS1893CYI-10LF

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Integrated Device Technology, Inc. ICS1893CY-10 Document Type Data Sheet Document Stage Preliminary Release 3.3-V 10Base-T/100Base-TX Integrated PHYceiver General The ICS1893CY-10 is a low-power, physical-layer device PHY that supports the ISO/IEC 10Base-T and 100Base-TX Carrier-Sense Multiple Access/Collision Detection CSMA/CD Ethernet standards. The ICS1893CY-10 supports managed or unmanaged node, repeater, and switch applications. The ICS1893CY-10 is intended for MII, Node applications that require the Auto-MIDIX feature that automatically corrects crossover errors in plant wiring. The ICS1893CY-10 incorporates digital signal processing DSP in its Physical Medium Dependent PMD sublayer. As a result, it can transmit and receive data on unshielded twisted-pair UTP category 5 cables with attenuation in excess of 24 dB at 100 MHz. With this ICS-patented technology, the ICS1893CY-10 can virtually eliminate errors from killer packets. The ICS1893CY-10 provides a Serial Management Interface for exchanging command and status information with a Station Management STA entity. The ICS1893CY-10 Media Dependent Interface MDI can be configured to provide either half- or full-duplex operation at data rates of 10 MHz or 100 MHz. The MDI configuration can be established manually with input pins or control register settings or automatically using the Auto-Negotiation features . When the ICS1893CY-10 Auto-Negotiation sublayer is enabled, it exchanges technology capability data with its remote link partner and automatically selects the highest-performance operating mode they have in common. • Supports category 5 cables with attenuation in excess of 24 dB at 100 MHz • Fully integrated, DSP-based PMD includes: Adaptive equalization and baseline wander correction Transmit wave shaping and stream cipher scrambler MLT-3 encoder and NRZ/NRZI encoder • Low-power, 0.35-micron CMOS typically 400 mW • Power-down mode typically 21mW • Single 3.3-V power supply. • Single-chip, fully integrated PHY provides PCS, PMA, PMD, and AUTONEG sublayers of IEEE standard • 10Base-T and 100Base-TX IEEE compliant • Highly configurable design supports: Node, repeater, and switch applications Managed and unmanaged applications 10M or 100M half- and full-duplex modes Parallel detection Auto-negotiation, with Next Page capabilities Auto-MDI/MDIX crossover correction • MAC/Repeater Interface can be configured as: 10M or 100M Media Independent Interface 100M Symbol Interface bypasses the PCS 10M 7-wire Serial Interface • Clock and crystal supported • Small Footprint 64-pin Thin Quad Flat Pack TQFP • Available in Industrial Temperature and Lead-Free ICS1893CY-10 Block Diagram 10/100 MII or Alternate MAC/Repeater Interface Interface MUX PCS • Frame • CRS/COL Detection • Parallel to Serial • 4B/5B MII Serial Management Interface MII Extended Register Low-Jitter Clock Synthesizer Clock 100Base-T Physical Dimensions of ICS1893CY-10 141 Ordering 142 Copyright 2007, Integrated Device Technology, Inc. All rights reserved. ICS1893CY-10 - Release Copyright 2007, Integrated Device Technology, Inc. All rights reserved. ICS1893CY-10 Data Sheet - Release Chapter 1 Abbreviations and Acronyms Chapter 1 Abbreviations and Acronyms Table 1-1 lists and interprets the abbreviations and acronyms used throughout this data sheet. Table Abbreviations and Acronyms Abbreviation / Acronym Interpretation 4B/5B 4-Bit / 5-Bit Encoding/Decoding ANSI American National Standards Institute CMOS complimentary metal-oxide semiconductor CSMA/CD Carrier Sense Multiple Access with Collision Detection Command Override Write digital signal processing End-of-Stream Delimiter FDDI Fiber Distributed Data Interface frequency-locked loop Fast Link Pulse A ‘dead’ time on the link following a 10Base-T packet, not to be confused with idle International Electrotechnical Commission IEEE Institute of Electrical and Electronic Engineers International Standards Organization Latching High Latching Low Latching Maximum Media Access Control Max. maximum Mbps Megabits per second Media Dependent Interface Management Frame Chapter 11 Ordering Information Chapter 11 Ordering Information Figure ICS1893CY-10 Ordering Information Part / Order Number ICS1893CY-10 ICS1893CYI-10 ICS1893CY-10LF ICS1893CYI-10LF Marking 1893CY-10 1893CYI-10 1893CY-10LF 1893CYI-10LF Package Temperature 10x10 TQFP Thin Quad Flat Pack 0° C to 70° C 10x10 TQFP Thin Quad Flat Pack -40° C to 85° C 10x10 TQFP Lead Free 0° C to 70° C 10x10 TQFP Lead Free -40° C to 85° C Copyright 2007, Integrated Device Technology, Inc. All rights reserved. ICS1893CY-10 - Release Chapter 11 Ordering Information Integrated Device Technology, Inc. Corporate Headquarters: 6024 Silver Creek Valley Rd. San Jose, CA 95138 Copyright 2007, Integrated Device Technology, Inc. All rights reserved. ICS1893CY-10 Data Sheet - Release Chapter 11 Ordering Information Copyright 2006, Integrated Device Technology, Inc. All rights reserved.

PDF Datasheet Preview

Integrated Device Technology, Inc.

ICS1893CY-10

Document Type Data Sheet Document Stage Preliminary Release
3.3-V 10Base-T/100Base-TX Integrated PHYceiver

General

The ICS1893CY-10 is a low-power, physical-layer device PHY that supports the ISO/IEC 10Base-T and 100Base-TX Carrier-Sense Multiple Access/Collision Detection CSMA/CD Ethernet standards. The ICS1893CY-10 supports managed or unmanaged node, repeater, and switch applications.

The ICS1893CY-10 is intended for MII, Node applications that require the Auto-MIDIX feature that automatically corrects crossover errors in plant wiring.

The ICS1893CY-10 incorporates digital signal processing DSP in its Physical Medium Dependent PMD sublayer. As a result, it can transmit and receive data on unshielded twisted-pair UTP category 5 cables with attenuation in excess of 24 dB at 100 MHz. With this ICS-patented technology, the ICS1893CY-10 can virtually eliminate errors from killer packets.

The ICS1893CY-10 provides a Serial Management Interface for exchanging command and status information with a Station Management STA entity.

The ICS1893CY-10 Media Dependent Interface MDI can be configured to provide either half- or full-duplex operation at data rates of 10 MHz or 100 MHz. The MDI configuration can be established manually with input pins or control register settings or automatically using the Auto-Negotiation features . When the ICS1893CY-10 Auto-Negotiation sublayer is enabled, it exchanges technology capability data with its remote link partner and automatically selects the highest-performance operating mode they have in common.
• Supports category 5 cables with attenuation in excess of
24 dB at 100 MHz
• Fully integrated, DSP-based PMD includes:

Adaptive equalization and baseline wander correction

Transmit wave shaping and stream cipher scrambler

MLT-3 encoder and NRZ/NRZI encoder
• Low-power, 0.35-micron CMOS typically 400 mW
• Power-down mode typically 21mW
• Single 3.3-V power supply.
• Single-chip, fully integrated PHY provides PCS, PMA,

PMD, and AUTONEG sublayers of IEEE standard
• 10Base-T and 100Base-TX IEEE compliant
• Highly configurable design supports:

Node, repeater, and switch applications

Managed and unmanaged applications 10M or 100M half- and full-duplex modes

Parallel detection

Auto-negotiation, with Next Page capabilities Auto-MDI/MDIX crossover correction
• MAC/Repeater Interface can be configured as:
10M or 100M Media Independent Interface
100M Symbol Interface bypasses the PCS
10M 7-wire Serial Interface
• Clock and crystal supported
• Small Footprint 64-pin Thin Quad Flat Pack TQFP
• Available in Industrial Temperature and Lead-Free

ICS1893CY-10 Block Diagram
10/100 MII or Alternate

MAC/Repeater Interface

Interface MUX

PCS
• Frame
• CRS/COL

Detection
• Parallel to Serial
• 4B/5B

MII Serial Management

Interface

MII Extended Register

Low-Jitter Clock

Synthesizer

Clock
100Base-T
Physical Dimensions of ICS1893CY-10 141 Ordering 142

Copyright 2007, Integrated Device Technology, Inc. All rights reserved.

ICS1893CY-10 - Release

Copyright 2007, Integrated Device Technology, Inc. All rights reserved.

ICS1893CY-10 Data Sheet - Release

Chapter 1 Abbreviations and Acronyms

Chapter 1 Abbreviations and Acronyms

Table 1-1 lists and interprets the abbreviations and acronyms used throughout this data sheet.

Table Abbreviations and Acronyms

Abbreviation / Acronym

Interpretation
4B/5B
4-Bit / 5-Bit Encoding/Decoding

ANSI

American National Standards Institute

CMOS
complimentary metal-oxide semiconductor

CSMA/CD

Carrier Sense Multiple Access with Collision Detection

Command Override Write
digital signal processing

End-of-Stream Delimiter

FDDI

Fiber Distributed Data Interface
frequency-locked loop

Fast Link Pulse

A ‘dead’ time on the link following a 10Base-T packet, not to be confused with idle

International Electrotechnical Commission

IEEE

Institute of Electrical and Electronic Engineers

International Standards Organization

Latching High

Latching Low

Latching Maximum

Media Access Control

Max.
maximum

Mbps

Megabits per second

Media Dependent Interface

Management Frame
Chapter 11 Ordering Information
Chapter 11 Ordering Information
Figure ICS1893CY-10 Ordering Information

Part / Order Number ICS1893CY-10 ICS1893CYI-10

ICS1893CY-10LF ICS1893CYI-10LF

Marking 1893CY-10 1893CYI-10 1893CY-10LF 1893CYI-10LF

Package

Temperature
10x10 TQFP Thin Quad Flat Pack 0° C to 70° C
10x10 TQFP Thin Quad Flat Pack -40° C to 85° C
10x10 TQFP Lead Free
0° C to 70° C
10x10 TQFP Lead Free
-40° C to 85° C

Copyright 2007, Integrated Device Technology, Inc. All rights reserved.

ICS1893CY-10 - Release
Chapter 11 Ordering Information

Integrated Device Technology, Inc.

Corporate Headquarters:
6024 Silver Creek Valley Rd. San Jose, CA 95138

Copyright 2007, Integrated Device Technology, Inc. All rights reserved.

ICS1893CY-10 Data Sheet - Release
Chapter 11 Ordering Information

Copyright 2006, Integrated Device Technology, Inc. All rights reserved.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived ICS1893CYI-10LFT Datasheet file may be downloaded here without warranties.

Datasheet ID: ICS1893CYI-10LFT 636960