PEF 22554 HT V3.1
PEF 22554 HT V3.1 Datasheet
Four-channel E1/T1/J1 Framer and Line Interface Component PEF 22554
| Part | Datasheet |
|---|---|
PEF 22554 HT V3.1 |
PEF 22554 HT V3.1 (pdf) |
| Related Parts | Information |
|---|---|
PEF 22554 E V3.1 |
PEF 22554 E V3.1 |
PEF 22554 E V2.1-G |
PEF 22554 E V2.1-G |
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PEF 22554 HT V2.1 |
PEF 22554 HT V2.1 |
PEF 22554 E V2.1 |
PEF 22554 E V2.1 |
| PDF Datasheet Preview |
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| Four-channel E1/T1/J1 Framer and Line Interface Component PEF 22554 The is an addition to Infineon's market leading family of advanced E1/T1/J1 Framer And Line Interface Unit LIU components. As a four port E1/T1/J1 framer and line interface unit LIU ,QuadFALC is optimized for a range of network equipment including Radio network Controllers, Node B line cards, PBX or SDH/SONET ADMs. The QuadFALC features a unique clock generation unit that accepts any reference clock between andd 20 MHz as well as integrated analog switches for impedance matching or protection switching. Using industry leading QuadFALC Evaluation support tools, system developers can shorten design cycles while creating a wide range of highly flexible, low BOM E1/T1/J1 line cards. • Programmable frame formats E1 Double- & CRC Multi-frame T1 F4, F12 D4 , Ext. Super Frame ESF , F72 SLC96 • Detects and generates LOS, AIS and RAI alarms • CRC-4 performance monitoring • PRBS generation and monitoring • Detects & generates LOS, AIS & RAI alarms • System bus data rate scalable from Mbit/s up to 16 Mbit/s • Synchronization Supply Message SSM generation and extreaction • Wireless base stations • Router • Multi-service access platforms, • Digital loop carriers • Remote access servers/concentrators • SONET/SDH Add/Drop multiplexers Analog Line Interfaces • Four independent E1/T1/J1 long haul/short haul line interface units • Software programmable T1/E1/J1 • Integrated analog switch for impedance matching E1-75/120, T1-100 , J1-110 and protection switching only PG-LBGA-160 package • Crystal-less wander and jitter attenuation/compensation according to TR 62411 and ETS-TBR 12/13 • Clock generation unit accepts any frequency reference clock from MHz to 20 MHz • Programmable transmit pulse shape for flexible pulse generation • Receiver sensitivity exceeds -36 kHz and -43 kHz • Clock signal generation & extraction according to ITU-T G.703 Sec. 13 Frame Aligners • ITU-T G.704 frame alignment/synthesis for Mbit/s HDLC Controllers • 12 HDLC controllers three per channel including 128-byte deep FIFO buffers each • CAS controller with micro-processor or system interface serial access • Supports signaling system #7 • ANSI T1.403 Bit-Oriented Messages BOM , generates periodical performance reports General Features • Software and pin compatible to previous QuadFALC versions • or type 8/16-bit microprocessor interface • Serial SPI bus and serial SCI bus slave interfaces • Low power operation 150mW / channel typical • Dual voltage V/3.3 V or single voltage V power supply • PG-LBGA-160, 15x15 mm with mm ball pitch • PG-TQFP-144, 20x20 mm, 0,5 mm pitch • -40°C to +85°C operation • Rohs compliant packages w. i n f i n e o n c o m / f a l c C O M U N I C AT I O N Never stop thinking. Transmission Line Local Loop Remote Loop Payload Loop Switching Network QuadFALC PEF 22554 Block Diagram Long/Short Haul Receive Line Interface Transmit Line Interface Clock Receive Framer Alarm Detection PRBS Monitor Line Decoder Receive System Interface Ordering No. B000-H0000-X-X-7600 Printed in Germany PS 0505 |
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