DLP-HS-FPGA

DLP-HS-FPGA Datasheet

DLP-HS-FPGA

Part	Datasheet
DLP-HS-FPGA	DLP-HS-FPGA (pdf)

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DLP-HS-FPGA LEAD-FREE USB - FPGA MODULE PRELIMINARY APPLICATIONS: - Rapid Prototyping - Educational Tool - Industrial / Process Control - Data Acquisition / Processing - Embedded Processor FEATURES: - Xilinx XC3S200A-4FTG256C FPGA - Micron 32M x 8 DDR2 SDRAM Memory - Built-In Configuration Bit File Directly to SPI Flash via High Speed USB Interface - 63 User I/O Channels 24 Differential Pairs, 8 Global Clocks - High Speed USB Interface - 66 MHz oscillator - 133 MHz DDR2 interface reference design provided - USB Port Powered or 5V External Power Barrel Jack - USB and Compatible Interface - Small Footprint x Inch PCB - Standard 50-Pin, 0.9-Inch DIP Interface DLP Design, Inc. INTRODUCTION The DLP-HS-FPGA Module is a low-cost, compact prototyping module that can be used for rapid proof of concept or for educational environments. The module is based on the Xilinx Spartan 3A and Future Technology Devices International’s FT2232H Dual-Channel High Speed USB IC. The DLP-HS-FPGA provides both the beginner as well as the experienced engineer with a rapid path to developing FPGA-based designs. When combined with the free ISE WebPACK Tools from Xilinx, this module is more than sufficient for creating anything from basic logical functions to a highly complex system controller. As a bonus feature, one channel of the dual-channel USB interface is used to load user bit files directly to the SPI external programmer is required. This represents a savings of as much as in that no additional programming cable is required for configuring the FPGA. All that is needed to load bit files to the DLP-HS-FPGA is a Windows software utility free with purchase , a Windows PC and a USB cable. The module can also be programmed from within the Xilinx ISE tool environment using a Xilinx programming cable purchased separately . The DLP-HS-FPGA is fully compatible with the free ISE WebPACK tools from Xilinx. ISE WebPACK offers the ideal development environment for FPGA designs with HDL synthesis and simulation, implementation, device fitting and JTAG programming. The DLP-HS-FPGA has on-board voltage regulators that generate all required power supply voltages from a single 5-volt source. Power for the module can be taken from either the host USB port or from a user-supplied, external 5-volt power supply via an on board standard barrel connector. Connection to user electronics is made via a 50-pin, 0.9-inch wide, industry-standard square inch post DIP header on the bottom of the board, and a 26 pin, inch wide top side 2x13 header. The bottom side 50 pin header provides access to 41 of the FPGA user input/output pins. The top side header provides access to 22 of the FPGA user input/output pins. The bottom side header mates with a user supplied standard 50 pin inch spaced DIP socket. The top side header mates with a user supplied inch spaced 2x13 connector such as the FFSD-13-D-xx.xx-01 xx.xx = cable length ribbon cable assembly from Samtec. DIP Socket Ribbon Cable Other on-board features include a 32M x 8 DDR2 SDRAM memory IC for user projects, and both JTAG and SPI Flash interface ports for connection to Xilinx programming tools. DLP Design, Inc. REFERENCE DESIGN A 10,000 line reference design is available for the Spartan 3A FPGA on the DLP-HS-FPGA to those that purchase the module. The design was written in VHDL and built using the free Xilinx ISE WebPACK tools. The reference design consists of the following blocks: It contains a USB interface block, a User I/0 block, a DDR2 SDRAM interface, a Heartbeat pulse generator, and a clock generator. The SPI Flash is used to store the design’s FPGA configuration file. The USB interface captures, interprets, and returns command and data information sent from the host PC through the FTDI USB interface to the FPGA. Commands include ping, return status, loopback data, set a User I/O pin high or low, read a User I/O pin, initialize the DDR2 SDRAM memory, and read or write the DDR2 SDRAM memory. Section 10 explains these in detail. The User I/O block controls access to the 63 User I/O pins accessible through the top and bottom side headers. Every one of these pins can be either an input or an output. The User I/O block can configure these pins as inputs and read their state, or as outputs and drive them high or low. As a side note 48 of these User I/O pins can be configured as 24 differential pairs, 8 can be configured as global clock inputs, and 6 can be configured as regional clock inputs. The DDR2 SDRAM interface block manages the memory’s initialization, the refresh cycle, and the read and write access. Read and write access is available in 4 byte bursts. The traces between the DDR2 SDRAM and FPGA are matched within 10 mils to accommodate reliable data transfer at 266 Mbit/s clocked at 133MHz . The interface creates and aligns the Data Strobes DQS based on an external feedback trace that matches two times the trace length between the FPGA and the DDR2 SDRAM. The initialization, read, and write commands are initiated by the USB interface block, and executed by the DDR2 SDRAM interface block. The Heartbeat pulse generator takes the internal system clock and divides it down so that the on board Heartbeat LED will be turned on and off at a duration of approximately one half second. The clock generator block receives the 66 MHz clock, and produces both the 133 MHz clocks required to run the DDR2 SDRAM memory device, and the 100 MHz clock for the remaining internal logic in the FPGA. It also handles reset and lock synchronization between internal DCM blocks. DLP Design, Inc. The design occupies the following FPGA resources: More reference designs are planned. Please contact DLP Design if you have any specific requests. FPGA SPECIFICATIONS The FPGA device used on the DLP-HS-FPGA is the Xilinx Spartan 3A XC3S200A-4FTG256 • Part Number: XC3S200A-4FTG256C • System Gates: 200,000 • Equivalent Logic Cells 4,032 • CLB Array

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DLP-HS-FPGA

LEAD-FREE

USB - FPGA MODULE PRELIMINARY

APPLICATIONS:
- Rapid Prototyping - Educational Tool - Industrial / Process

Control - Data Acquisition /

Processing - Embedded

Processor

FEATURES:
- Xilinx XC3S200A-4FTG256C FPGA - Micron 32M x 8 DDR2 SDRAM Memory - Built-In Configuration Bit File Directly
to SPI Flash via High Speed USB Interface - 63 User I/O Channels 24 Differential Pairs, 8 Global Clocks - High Speed USB Interface - 66 MHz oscillator - 133 MHz DDR2 interface reference design provided - USB Port Powered or 5V External Power Barrel Jack - USB and Compatible Interface - Small Footprint x Inch PCB - Standard 50-Pin, 0.9-Inch DIP Interface

DLP Design, Inc.

INTRODUCTION

The DLP-HS-FPGA Module is a low-cost, compact prototyping module that can be used for rapid proof of concept or for educational environments. The module is based on the Xilinx Spartan 3A and Future Technology Devices International’s FT2232H Dual-Channel High Speed USB IC. The DLP-HS-FPGA provides both the beginner as well as the experienced engineer with a rapid path to developing FPGA-based designs. When combined with the free ISE WebPACK Tools from Xilinx, this module is more than sufficient for creating anything from basic logical functions to a highly complex system controller.

As a bonus feature, one channel of the dual-channel USB interface is used to load user bit files directly to the SPI external programmer is required. This represents a savings of as much as in that no additional programming cable is required for configuring the FPGA. All that is needed to load bit files to the DLP-HS-FPGA is a Windows software utility free with purchase , a Windows PC and a USB cable. The module can also be programmed from within the Xilinx ISE tool environment using a Xilinx programming cable purchased separately .

The DLP-HS-FPGA is fully compatible with the free ISE WebPACK tools from Xilinx. ISE WebPACK offers the ideal development environment for FPGA designs with HDL synthesis and simulation, implementation, device fitting and JTAG programming.

The DLP-HS-FPGA has on-board voltage regulators that generate all required power supply voltages from a single 5-volt source. Power for the module can be taken from either the host USB port or from a user-supplied, external 5-volt power supply via an on board standard barrel connector.

Connection to user electronics is made via a 50-pin, 0.9-inch wide, industry-standard square inch post DIP header on the bottom of the board, and a 26 pin, inch wide top side 2x13 header. The bottom side 50 pin header provides access to 41 of the FPGA user input/output pins. The top side header provides access to 22 of the FPGA user input/output pins. The bottom side header mates with a user supplied standard 50 pin inch spaced DIP socket. The top side header mates with a user supplied inch spaced 2x13 connector such as the FFSD-13-D-xx.xx-01 xx.xx = cable length ribbon cable assembly from Samtec.

DIP Socket

Ribbon Cable

Other on-board features include a 32M x 8 DDR2 SDRAM memory IC for user projects, and both JTAG and SPI Flash interface ports for connection to Xilinx programming tools.

DLP Design, Inc.

REFERENCE DESIGN

A 10,000 line reference design is available for the Spartan 3A FPGA on the DLP-HS-FPGA to those that purchase the module. The design was written in VHDL and built using the free Xilinx ISE WebPACK tools. The reference design consists of the following blocks:

It contains a USB interface block, a User I/0 block, a DDR2 SDRAM interface, a Heartbeat pulse generator, and a clock generator. The SPI Flash is used to store the design’s FPGA configuration file.

The USB interface captures, interprets, and returns command and data information sent from the host PC through the FTDI USB interface to the FPGA. Commands include ping, return status, loopback data, set a User I/O pin high or low, read a User I/O pin, initialize the DDR2 SDRAM memory, and read or write the DDR2 SDRAM memory. Section 10 explains these in detail.

The User I/O block controls access to the 63 User I/O pins accessible through the top and bottom side headers. Every one of these pins can be either an input or an output. The User I/O block can configure these pins as inputs and read their state, or as outputs and drive them high or low. As a side note 48 of these User I/O pins can be configured as 24 differential pairs, 8 can be configured as global clock inputs, and 6 can be configured as regional clock inputs.

The DDR2 SDRAM interface block manages the memory’s initialization, the refresh cycle, and the read and write access. Read and write access is available in 4 byte bursts. The traces between the DDR2 SDRAM and FPGA are matched within 10 mils to accommodate reliable data transfer at 266 Mbit/s clocked at 133MHz . The interface creates and aligns the Data Strobes DQS based on an external feedback trace that matches two times the trace length between the FPGA and the DDR2 SDRAM. The initialization, read, and write commands are initiated by the USB interface block, and executed by the DDR2 SDRAM interface block.

The Heartbeat pulse generator takes the internal system clock and divides it down so that the on board Heartbeat LED will be turned on and off at a duration of approximately one half second.

The clock generator block receives the 66 MHz clock, and produces both the 133 MHz clocks required to run the DDR2 SDRAM memory device, and the 100 MHz clock for the remaining internal logic in the FPGA. It also handles reset and lock synchronization between internal DCM blocks.

DLP Design, Inc.

The design occupies the following FPGA resources:

More reference designs are planned. Please contact DLP Design if you have any specific requests.

FPGA SPECIFICATIONS

The FPGA device used on the DLP-HS-FPGA is the Xilinx Spartan 3A XC3S200A-4FTG256
• Part Number:

XC3S200A-4FTG256C
• System Gates:
200,000
• Equivalent Logic Cells 4,032
• CLB Array

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived DLP-HS-FPGA Datasheet file may be downloaded here without warranties.

Datasheet ID: DLP-HS-FPGA 510280