CY7B9940V-5AXIT

CY7B9940V-5AXIT Datasheet

RoboClockII Junior, CY7B9930V, CY7B9940V

Part	Datasheet
CY7B9940V-5AXIT	CY7B9940V-5AXIT (pdf)

Related Parts	Information
CY7B9940V-2AXI	CY7B9940V-2AXI
CY7B9940V-2AXIT	CY7B9940V-2AXIT
CY7B9940V-5AXI	CY7B9940V-5AXI

PDF Datasheet Preview
RoboClockII Junior, CY7B9930V, CY7B9940V High Speed Multifrequency PLL Clock Buffer • MHz CY7B9930V , or MHz CY7B9940V input/output operation • Matched pair output skew < 200 ps • Zero input-to-output delay • 10 LVTTL 50% duty-cycle outputs capable of driving termi- nated lines • Commercial temperature range with eight outputs at 200 MHz • Industrial temperature range with eight outputs at 200 MHz • 3.3V LVTTL/LV differential LVPECL , fault-tolerant and hot insertable reference inputs • Multiply ratios of 8, 10, 12 • Operation up to 12x input frequency • Individual output bank disable for aggressive power management and EMI reduction • Output high impedance option for testing purposes • Fully integrated PLL with lock indicator • Low cycle-to-cycle jitter <100 ps peak-peak • Single 3.3V ± 10% supply • 44-pin TQFP package Functional Description The CY7B9930V and CY7B9940V High-Speed Multifrequency PLL Clock Buffers offer user-selectable control over system clock functions. This multiple output clock driver provides the system integrator with functions necessary to optimize the timing of high performance computer or communication systems. Ten configurable outputs can each drive terminated transmission lines with impedances as low as 50Ω while delivering minimal and specified output skews at LVTTL levels. The outputs are arranged in three banks. The FB feedback bank consists of two outputs, which allows divide-by functionality from 1 to Any one of these ten outputs can be connected to the feedback input as well as driving other inputs. Selectable reference input is a fault tolerance feature that allows smooth change over to secondary clock source, when the primary clock source is not in operation. The reference inputs are configurable to accommodate both LVTTL or differential LVPECL inputs. The completely integrated PLL reduces jitter and simplifies board layout. Logic Block Diagram FBKA REFA+ REFB+ REFSEL Phase Freq. Detector Filter FS 3 Output_Mode 3 Feedback Bank FBDS0 3 FBDS1 3 Divide Matrix Bank 2 DIS2 Bank 1 DIS1 Control Logic Divide Generator LOCK QFA0 QFA1 2QA0 2QA1 2QB0 2QB1 1QA0 1QA1 1QB0 1QB1 • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback RoboClockII Junior, CY7B9930V, CY7B9940V Contents Features Functional Description Logic Block Diagram Contents Logic Block Diagram Description Phase Frequency Detector and Filter VCO, Control Logic, and Divide Generator Divide Matrix Output Disable Description Lock Detect Output Description Factory Test Mode Description Pin Definitions Absolute Maximum Conditions Operating Range Electrical Characteristics Over the Operating Range Capacitance Switching Characteristics AC Timing Diagrams Ordering Information Package Diagram Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions Page 2 of 12 [+] Feedback RoboClockII Junior, CY7B9930V, CY7B9940V Logic Block Diagram Description Phase Frequency Detector and Filter These two blocks accept signals from the REF inputs REFA+, REFB+ or and the FB input FBKA . Correction information is then generated to control the frequency of the Voltage Controlled Oscillator VCO . These two blocks, along with the VCO, form a Phase-Locked Loop PLL that tracks the incoming REF signal. The RoboClockII Junior has a flexible REF input scheme. These inputs allow the use of either differential LVPECL or single ended LVTTL inputs. To configure as single ended LVTTL inputs, leave the complementary pin to 1.5V , then use the other input pin as an LVTTL input. The REF inputs are also tolerant to hot insertion. The REF inputs can be changed dynamically. When changing from one reference input to the other reference input of the same frequency, the PLL is optimized to ensure that the clock outputs period is not less than the calculated system budget tMIN = tREF nominal reference clock period tCCJ cycle-to-cycle jitter tPDEV max. period deviation while reacquiring lock. VCO, Control Logic, and Divide Generator The VCO accepts analog control inputs from the PLL filter block. The FS control pin setting determines the nominal operational frequency range of the divide by one output fNOM of the device. fNOM is directly related to the VCO frequency. There are two versions of the RoboClockII Junior, a low speed device CY7B9930V where fNOM ranges from 12 MHz to 100 MHz, and a high speed device CY7B9940V , which ranges from 24 MHz to 200 MHz. The FS setting for each device is shown in Table The fNOM frequency is seen on “divide-by-one” outputs. Table Frequency Range Select FS[1] LOW MID HIGH CY7B9930V fNOM MHz Min. Max. CY7B9940V fNOM MHz Min. Max. 200[2] Divide Matrix The Divide Matrix is comprised of three independent banks two banks of clock outputs and one bank for feedback. Each clock output bank has two pairs of low-skew, high fanout output buffers [1:2]Q[A:B][0:1] , and an output disable DIS[1:2] . The feedback bank has one pair of low-skew, high fanout output buffers QFA[0:1] . One of these outputs may connect to the selected feedback input FBKA+ . This feedback bank also has two divider function selects FBDS[0:1]. The divide capabilities for each bank are shown in Table Table Output Divider Function Function Selects FBDS1 FBDS0 LOW MID HIGH LOW MID HIGH LOW MID HIGH LOW MID HIGH Output Divider Function Bank 1 /1 /1 /1 /1 /1 /1 /1 /1 /1 Bank 2 /1 /1 /1 /1 /1 /1 /1 /1 /1 Feedback Bank /1 /2 /3 /4 /5 /6 /8 /10 /12 Output Disable Description Ordering Information Propagation Delay ps Pb-free 500 250 Max Speed MHz 100 200 Ordering Code CY7B9930V-5AXC CY7B9930V-5AXCT CY7B9940V-5AXC CY7B9940V-5AXCT CY7B9940V-5AXI CY7B9940V-5AXIT CY7B9940V-2AXC CY7B9940V-2AXCT CY7B9940V-2AXI CY7B9940V-2AXIT Package Type 44-Lead Thin Quad Flat Pack 44-Lead Thin Quad Flat and Reel 44-Lead Thin Quad Flat Pack 44-Lead Thin Quad Flat and Reel 44-Lead Thin Quad Flat Pack 44-Lead Thin Quad Flat and Reel 44-Lead Thin Quad Flat Pack 44-Lead Thin Quad Flat and Reel 44-Lead Thin Quad Flat Pack 44-Lead Thin Quad Flat and Reel Operating Range Commercial Industrial Commercial Industrial Package Diagram Figure 44-Pin TQFP Package Outline 51-85064 D Page 10 of 12 [+] Feedback RoboClockII Junior, CY7B9930V, CY7B9940V Document History Page Document Title RoboClockII Junior, CY7B9930V, CY7B9940V High Speed Multifrequency PLL Clock Buffer Document Number 38-07271 ECN No. Submission Date Orig. of Change Description of Change 110536 12/02/01 SZV Change from Spec number 38-01141 115109 7/03/02 HWT Add 44TQFP package for both CY7B9930/40V Industrial Operating Range 128463 7/29/03 Added clock input frequency fin specifications in the switching characteristics table. Added Min. values for the clock output frequency fout in the switching characteristics table. C 1346903 8/8/07 WWZ/VED/ Update the ordering info to reflect the current status and Pb-free part numbers. ARI Implemented new template. Updated the package diagram. D 2894960 03/18/2010 Added Table of Contents Removed part numbers CY7B9930V-5AC, CY7B9930V-5AI, CY7B9940V-5AC, CY7B9940V-5AI, CY7B9930V-2AC, CY7B9930V-2AI and CY7B9940V-2AI in ordering information table. Updated package diagram Added Sales, Solutions, and Legal Information E 2906750 04/07/2010 KVM Removed inactive part from Ordering Information table. Page 11 of 12 [+] Feedback RoboClockII Junior, CY7B9930V, CY7B9940V Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 \| PSoC 3 \| PSoC 5 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. RoboClock II is a trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Page 12 of 12 [+] Feedback

PDF Datasheet Preview

RoboClockII Junior, CY7B9930V, CY7B9940V

High Speed Multifrequency PLL Clock Buffer
• MHz CY7B9930V , or MHz CY7B9940V input/output operation
• Matched pair output skew < 200 ps
• Zero input-to-output delay
• 10 LVTTL 50% duty-cycle outputs capable of driving termi-
nated lines
• Commercial temperature range with eight outputs at 200 MHz
• Industrial temperature range with eight outputs at 200 MHz
• 3.3V LVTTL/LV differential LVPECL , fault-tolerant and hot
insertable reference inputs
• Multiply ratios of 8, 10, 12
• Operation up to 12x input frequency
• Individual output bank disable for aggressive power
management and EMI reduction
• Output high impedance option for testing purposes
• Fully integrated PLL with lock indicator
• Low cycle-to-cycle jitter <100 ps peak-peak
• Single 3.3V ± 10% supply
• 44-pin TQFP package

Functional Description

The CY7B9930V and CY7B9940V High-Speed Multifrequency PLL Clock Buffers offer user-selectable control over system clock functions. This multiple output clock driver provides the system integrator with functions necessary to optimize the timing of high performance computer or communication systems.

Ten configurable outputs can each drive terminated transmission lines with impedances as low as 50Ω while delivering minimal and specified output skews at LVTTL levels. The outputs are arranged in three banks. The FB feedback bank consists of two outputs, which allows divide-by functionality from 1 to Any one of these ten outputs can be connected to the feedback input as well as driving other inputs.

Selectable reference input is a fault tolerance feature that allows smooth change over to secondary clock source, when the primary clock source is not in operation. The reference inputs are configurable to accommodate both LVTTL or differential LVPECL inputs. The completely integrated PLL reduces jitter and simplifies board layout.

Logic Block Diagram

FBKA

REFA+ REFB+ REFSEL

Phase Freq. Detector

Filter

FS 3 Output_Mode 3

Feedback Bank FBDS0 3

FBDS1 3

Divide Matrix

Bank 2

DIS2

Bank 1

DIS1

Control Logic Divide Generator

LOCK

QFA0 QFA1
2QA0 2QA1 2QB0 2QB1
1QA0 1QA1 1QB0 1QB1
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

RoboClockII Junior, CY7B9930V, CY7B9940V

Contents

Features Functional Description Logic Block Diagram Contents Logic Block Diagram Description

Phase Frequency Detector and Filter VCO, Control Logic, and Divide Generator Divide Matrix Output Disable Description Lock Detect Output Description Factory Test Mode Description Pin Definitions Absolute Maximum Conditions
Operating Range Electrical Characteristics Over the Operating Range Capacitance Switching Characteristics AC Timing Diagrams Ordering Information Package Diagram Document History Page Sales, Solutions, and Legal Information

Worldwide Sales and Design Support Products PSoC Solutions

Page 2 of 12 [+] Feedback

RoboClockII Junior, CY7B9930V, CY7B9940V

Logic Block Diagram Description

Phase Frequency Detector and Filter

These two blocks accept signals from the REF inputs REFA+, REFB+ or and the FB input FBKA . Correction information is then generated to control the frequency of the Voltage Controlled Oscillator VCO . These two blocks, along with the VCO, form a Phase-Locked Loop PLL that tracks the incoming REF signal.

The RoboClockII Junior has a flexible REF input scheme. These inputs allow the use of either differential LVPECL or single ended LVTTL inputs. To configure as single ended LVTTL inputs, leave the complementary pin to 1.5V , then use the other input pin as an LVTTL input. The REF inputs are also tolerant to hot insertion.

The REF inputs can be changed dynamically. When changing from one reference input to the other reference input of the same frequency, the PLL is optimized to ensure that the clock outputs period is not less than the calculated system budget tMIN = tREF nominal reference clock period tCCJ cycle-to-cycle jitter tPDEV max. period deviation while reacquiring lock.

VCO, Control Logic, and Divide Generator

The VCO accepts analog control inputs from the PLL filter block. The FS control pin setting determines the nominal operational frequency range of the divide by one output fNOM of the device. fNOM is directly related to the VCO frequency. There are two versions of the RoboClockII Junior, a low speed device CY7B9930V where fNOM ranges from 12 MHz to 100 MHz, and a high speed device CY7B9940V , which ranges from 24 MHz to 200 MHz. The FS setting for each device is shown in Table The fNOM frequency is seen on “divide-by-one” outputs.

Table Frequency Range Select

FS[1]

LOW MID HIGH

CY7B9930V
fNOM MHz

Min.

Max.

CY7B9940V
fNOM MHz

Min.

Max.
200[2]

Divide Matrix

The Divide Matrix is comprised of three independent banks two banks of clock outputs and one bank for feedback. Each clock output bank has two pairs of low-skew, high fanout output buffers [1:2]Q[A:B][0:1] , and an output disable DIS[1:2] .

The feedback bank has one pair of low-skew, high fanout output buffers QFA[0:1] . One of these outputs may connect to the selected feedback input FBKA+ . This feedback bank also has two divider function selects FBDS[0:1].

The divide capabilities for each bank are shown in Table

Table Output Divider Function

Function Selects

FBDS1

FBDS0

LOW MID HIGH

LOW MID HIGH LOW MID HIGH LOW MID HIGH

Output Divider Function

Bank 1
/1 /1 /1 /1 /1 /1 /1 /1 /1

Bank 2
/1 /1 /1 /1 /1 /1 /1 /1 /1

Feedback Bank
/1 /2 /3 /4 /5 /6 /8 /10 /12

Output Disable Description
Ordering Information

Propagation Delay ps

Pb-free 500 250

Max Speed MHz
100 200
Ordering Code

CY7B9930V-5AXC CY7B9930V-5AXCT CY7B9940V-5AXC CY7B9940V-5AXCT CY7B9940V-5AXI CY7B9940V-5AXIT CY7B9940V-2AXC CY7B9940V-2AXCT CY7B9940V-2AXI CY7B9940V-2AXIT

Package Type
44-Lead Thin Quad Flat Pack 44-Lead Thin Quad Flat and Reel 44-Lead Thin Quad Flat Pack 44-Lead Thin Quad Flat and Reel 44-Lead Thin Quad Flat Pack 44-Lead Thin Quad Flat and Reel 44-Lead Thin Quad Flat Pack 44-Lead Thin Quad Flat and Reel 44-Lead Thin Quad Flat Pack 44-Lead Thin Quad Flat and Reel

Operating Range

Commercial

Industrial

Commercial Industrial

Package Diagram

Figure 44-Pin TQFP Package Outline
51-85064 *D

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RoboClockII Junior, CY7B9930V, CY7B9940V

Document History Page

Document Title RoboClockII Junior, CY7B9930V, CY7B9940V High Speed Multifrequency PLL Clock Buffer Document Number 38-07271

ECN No.

Submission Date

Orig. of Change

Description of Change
110536
12/02/01

SZV Change from Spec number 38-01141
115109
7/03/02

HWT Add 44TQFP package for both CY7B9930/40V Industrial Operating Range
128463
7/29/03

Added clock input frequency fin specifications in the switching characteristics table. Added Min. values for the clock output frequency fout in the switching characteristics table.
*C 1346903
8/8/07
WWZ/VED/ Update the ordering info to reflect the current status and Pb-free part numbers. ARI Implemented new template. Updated the package diagram.
*D 2894960 03/18/2010
Added Table of Contents Removed part numbers CY7B9930V-5AC, CY7B9930V-5AI, CY7B9940V-5AC, CY7B9940V-5AI, CY7B9930V-2AC, CY7B9930V-2AI and CY7B9940V-2AI in ordering information table. Updated package diagram Added Sales, Solutions, and Legal Information
*E 2906750 04/07/2010
KVM Removed inactive part from Ordering Information table.

Page 11 of 12 [+] Feedback

RoboClockII Junior, CY7B9930V, CY7B9940V

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products Automotive Clocks & Buffers Interface Lighting & Power Control

Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF
cypress.com/go/automotive cypress.com/go/clocks
cypress.com/go/interface cypress.com/go/powerpsoc
cypress.com/go/plc cypress.com/go/memory
cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB
cypress.com/go/wireless

PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

RoboClock II is a trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations.

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Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7B9940V-5AXIT Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7B9940V-5AXIT 507838