PI7C8150BEVB

PI7C8150BEVB Datasheet

PI7C8150B

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PI7C8150BEVB	PI7C8150BEVB (pdf)

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PI7C8150BND	PI7C8150BND
PI7C8150BNDI	PI7C8150BNDI

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PI7C8150B Asynchronous 2-Port PCI-to-PCI Bridge 15-0048 1545 Barber Lane Milpitas, CA 95035 Telephone 408-232-9100 Fax 408-434-1040 Internet: PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE LIFE SUPPORT POLICY Pericom Semiconductor Corporation’s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of PSC. 1 Life support devices or system are devices or systems which a Are intended for surgical implant into the body or b Support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Pericom Semiconductor Corporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom Semiconductor does not assume any responsibility for use of any circuitry described other than the circuitry embodied in a Pericom Semiconductor product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Pericom Semiconductor Corporation. All other trademarks are of their respective companies. 15-0048 Page 2 of 107 PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE Date 03/26/03 05/14/03 06/10/03 06/25/03 07/31/03 10/20/03 02/13/04 05/20/04 07/06/04 08/12/04 09/23/04 01/10/05 04/05/06 04/1715 15-0048 Page 3 of 107 PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE This page intentionally left blank. 15-0048 Page 4 of 107 PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE TABLE OF CONTENTS 1 INTRODUCTION 2 SIGNAL DEFINITIONS SIGNAL TYPES SIGNALS PRIMARY BUS INTERFACE SIGNALS CLOCK SIGNALS MISCELLANEOUS GENERAL PURPOSE I/O INTERFACE SIGNALS JTAG BOUNDARY SCAN SIGNALS POWER AND PIN LIST 208-PIN FQFP PIN LIST 256-BALL 3 PCI BUS OPERATION TYPES OF TRANSACTIONS SINGLE ADDRESS DEVICE SELECT DEVSEL_L DATA WRITE TRANSACTIONS MEMORY WRITE MEMORY WRITE AND INVALIDATE DELAYED WRITE TRANSACTION ADDRESS BUFFERING MULTIPLE WRITE FAST BACK-TO-BACK TRANSACTIONS READ TRANSACTIONS PREFETCHABLE READ NON-PREFETCHABLE READ TRANSACTIONS READ PREFETCH ADDRESS BOUNDARIES DELAYED READ REQUESTS DELAYED READ COMPLETION WITH TARGET DELAYED READ COMPLETION ON INITIATOR FAST BACK-TO-BACK READ TRANSACTION CONFIGURATION TRANSACTIONS TYPE 0 ACCESS TO TYPE 1 TO TYPE 0 CONVERSION TYPE 1 TO TYPE 1 FORWARDING SPECIAL CYCLES TRANSACTION MASTER TERMINATION INITIATED BY PI7C8150B MASTER ABORT RECEIVED BY PI7C8150B TARGET TERMINATION RECEIVED BY PI7C8150B TARGET TERMINATION INITIATED BY 4 ADDRESS ADDRESS RANGES I/O ADDRESS DECODING I/O BASE AND LIMIT ADDRESS REGISTER ISA MEMORY ADDRESS MEMORY-MAPPED I/O BASE AND LIMIT ADDRESS REGISTERS 15-0048 Page 5 of 107 PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE PREFETCHABLE MEMORY BASE AND LIMIT ADDRESS REGISTERS VGA SUPPORT VGA MODE VGA SNOOP 5 TRANSACTION TRANSACTIONS GOVERNED BY ORDERING RULES GENERAL ORDERING RULES DATA SYNCHRONIZATION 6 ERROR ADDRESS PARITY DATA PARITY CONFIGURATION WRITE TRANSACTIONS TO CONFIGURATION SPACE READ TRANSACTIONS DELAYED WRITE POSTED WRITE TRANSACTIONS DATA PARITY ERROR REPORTING SUMMARY SYSTEM ERROR SERR_L REPORTING 7 EXCLUSIVE ACCESS CONCURRENT LOCKS ACQUIRING EXCLUSIVE ACCESS ACROSS PI7C8150B LOCKED TRANSACTIONS IN DOWNSTREAM DIRECTION LOCKED TRANSACTION IN UPSTREAM DIRECTION ENDING EXCLUSIVE ACCESS 8 PCI BUS ARBITRATION PRIMARY PCI BUS SECONDARY PCI BUS SECONDARY BUS ARBITRATION USING THE INTERNAL ARBITER PREEMPTION SECONDARY BUS ARBITRATION USING AN EXTERNAL ARBITER.......................65 BUS 9 CLOCKS PRIMARY CLOCK INPUTS SECONDARY CLOCK ASYNCHRONOUS MODE 10 GENERAL PURPOSE I/O GPIO CONTROL REGISTERS SECONDARY CLOCK CONTROL LIVE INSERTION 11 PCI POWER MANAGEMENT 12 RESET PRIMARY INTERFACE RESET SECONDARY INTERFACE RESET CHIP RESET 13 SUPPORTED PRIMARY INTERFACE 15-0048 Page 6 of 107 PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE SECONDARY INTERFACE 14 CONFIGURATION CONFIGURATION VENDOR ID REGISTER OFFSET 00h DEVICE ID REGISTER OFFSET 00h COMMAND REGISTER OFFSET 04h STATUS REGISTER OFFSET 04h CLASS CODE REGISTER OFFSET CACHE LINE SIZE REGISTER OFFSET 0Ch PRIMARY LATENCY TIMER REGISTER OFFSET 0Ch HEADER TYPE REGISTER OFFSET PRIMARY BUS NUMBER REGISTSER OFFSET 18h SECONDARY BUS NUMBER REGISTER OFFSET 18h SUBORDINATE BUS NUMBER REGISTER OFFSET SECONDARY LATENCY TIMER REGISTER OFFSET 18h I/O BASE REGISTER OFFSET I/O LIMIT REGISTER OFFSET 1Ch SECONDARY STATUS REGISTER OFFSET MEMORY BASE REGISTER OFFSET 20h 208-PIN FQFP PACKAGE 256-BALL PBGA PACKAGE PART NUMBER ORDERING INFORMATION 15-0048 Page 8 of 107 PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE LIST OF TABLES TABLE PIN LIST 208-PIN TABLE PIN LIST 256-PIN TABLE PCI TABLE WRITE TRANSACTION FORWARDING TABLE WRITE TRANSACTION DISCONNECT ADDRESS BOUNDARIES TABLE READ PREFETCH ADDRESS TABLE READ TRANSACTION PREFETCHING TABLE DEVICE NUMBER TO IDSEL S_AD PIN MAPPING TABLE DELAYED WRITE TARGET TERMINATION RESPONSE TABLE RESPONSE TO POSTED WRITE TARGET TERMINATION TABLE RESPONSE TO DELAYED READ TARGET TABLE SUMMARY OF TRANSACTION ORDERING TABLE SETTING THE PRIMARY INTERFACE DETECTED PARITY ERROR TABLE SETTING SECONDARY INTERFACE DETECTED PARITY ERROR TABLE SETTING PRIMARY INTERFACE MASTER DATA PARITY ERROR DETECTED BIT TABLE SETTING SECONDARY INTERFACE MASTER DATA PARITY ERROR DETECTED BIT TABLE ASSERTION OF P_PERR_L TABLE ASSERTION OF S_PERR_L TABLE ASSERTION OF P_SERR_L FOR DATA PARITY TABLE GPIO OPERATION TABLE GPIO SERIAL DATA FORMAT TABLE POWER MANAGEMENT TRANSITIONS TABLE TAP PINS TABLE JTAG BOUNDARY REGISTER LIST OF FIGURES FIGURE 8-1 SECONDARY ARBITER EXAMPLE FIGURE 16-1 TEST ACCESS PORT BLOCK DIAGRAM FIGURE 17-1 PCI SIGNAL TIMING MEASUREMENT FIGURE 18-1 208-PIN FQFP PACKAGE OUTLINE FIGURE 18-2 256-PIN PBGA PACKAGE 15-0048 Page 9 of 107 PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE This page intentionally left blank. 15-0048 Page 10 of 107 15-0048 PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE INTRODUCTION Product Description Product Features Supported modes of asynchronous operation Primary MHz PI7C8150B 25MHz to 66MHz PI7C8150B-33 25MHz to 33MHz Secondary MHz 25MHz to 66MHz 25MHz to 33MHz Supported modes of synchronous operation Primary MHz PI7C8150B PI7C8150B PI7C8150B PI7C8150B PI7C8150B-33 PI7C8150B-33 Secondary MHz 66 33 50 25 • Provides internal arbitration for one set of nine secondary bus masters Programmable 2-level priority arbiter Disable control for use of external arbiter • Supports posted write buffers in all directions • Four 128 byte FIFO’s for delay transactions • Two 128 byte FIFO’s for posted memory transactions • Enhanced address decoding • Temperature support Extended Commercial range 0°C to 85°C Industrial range -40°C to 85°C • IEEE JTAG interface support • 3.3V core 3.3V and 5V signaling • Packaging 208-pin FQFP and 256-pin PBGA Pb-free & Green Page 11 of 107 PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE SIGNAL DEFINITIONS Signal Types Signal Type I O P TS STS Description Input Only Output Only Power Tri-State bi-directional Sustained Tri-State. Active LOW signal must be pulled HIGH for 1 cycle when deasserting. Open Drain Signals Note Signal names that end with “_L” are active LOW. When a write transaction is first detected on the initiator bus, and PI7C8150B forwards it as a delayed transaction, PI7C8150B claims the access by asserting DEVSEL_L and returns a target retry to the initiator. During the address phase, PI7C8150B samples the bus command, address, and address parity one cycle later. After IRDY_L is asserted, PI7C8150B also samples the first data DWORD, byte enable bits, and data parity. This information is placed into the delayed transaction queue. The transaction is queued only if no other existing delayed transactions have the same address and command, and if the delayed transaction queue is not full. When the delayed write transaction moves to the head of the delayed transaction queue and all ordering constraints with posted data are satisfied. The PI7C8150B initiates the transaction on the target bus. PI7C8150B transfers the write data to the target. If PI7C8150B receives a target retry in response to the write transaction on the target bus, it continues to repeat the write transaction until the data transfer is completed, or until an error condition is encountered. If PI7C8150B is unable to deliver write data after 224 default or 232 maximum attempts, PI7C8150B will report a system error. PI7C8150B also asserts P_SERR_L if the primary SERR_L enable bit is set in the command register. See Section for information on the assertion of P_SERR_L. When the initiator repeats the same write transaction same command, address, byte enable bits, and data , and the completed delayed transaction is at the head of the queue, the PI7C8150B claims the access by asserting DEVSEL_L and returns TRDY_L to the initiator, to indicate that the write data was transferred. If the initiator requests multiple DWORD, PI7C8150B also asserts STOP_L in conjunction with TRDY_L to signal a target disconnect. Note that only those bytes of write data with valid byte enable bits are compared. If any of the byte enable bits are turned off driven HIGH , the corresponding byte of write data is not compared. If the initiator repeats the write transaction before the data has been transferred to the target, PI7C8150B returns a target retry to the initiator. PI7C8150B continues to return a target retry to the initiator until write data is delivered to the target, or until an error condition is encountered. When the write transaction is repeated, PI7C8150B does not make a new entry into the delayed transaction queue. Section provides detailed information about how PI7C8150B responds to target termination during delayed write transactions. PI7C8150B implements a discard timer that starts counting when the delayed write completion is at the head of the delayed transaction completion queue. The initial value of this timer can be set to the retry counter register offset 78h. If the initiator does not repeat the delayed write transaction before the discard Page 25 of 107 PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE timer expires, PI7C8150B discards the delayed write completion from the delayed transaction completion queue. PI7C8150B also conditionally asserts P_SERR_L see Section WRITE TRANSACTION ADDRESS BOUNDARIES PI7C8150B imposes internal address boundaries when accepting write data. The aligned address boundaries are used to prevent PI7C8150B from continuing a transaction over a device address boundary and to provide an upper limit on maximum latency. PI7C78150 returns a target disconnect to the initiator when it reaches the aligned address boundaries under conditions shown in Table Table Write Transaction Disconnect Address Boundaries Type of Transaction Condition Aligned Address Boundary Delayed Write Disconnects after one data transfer Posted Memory Write Memory write disconnect control 4KB aligned address boundary bit = 0 1 Posted Memory Write Memory write disconnect control Disconnects at cache line boundary bit = 1 Posted Memory Write and Cache line size 1, 2, 4, 8, 16 4KB aligned address boundary Invalidate Posted Memory Write and Cache line size = 1, 2, 4, 8, 16 Cache line boundary if posted memory Invalidate write data FIFO does not have enough space for the cache line Note Memory write disconnect control bit is bit 1 of the chip control register at offset 40h in the configuration space. BUFFERING MULTIPLE WRITE TRANSACTIONS PI7C8150B continues to accept posted memory write transactions as long as space for at least one DWORD of data in the posted write data buffer remains. If the posted write data buffer fills before the initiator terminates the write transaction, PI7C8150B returns a target disconnect to the initiator. Delayed write transactions are posted as long as at least one open entry in the delayed transaction queue exists. Therefore, several posted and delayed write transactions can exist in data buffers at the same time. See Chapter 6 for information about how multiple posted and delayed write transactions are ordered. FAST BACK-TO-BACK TRANSACTIONS PI7C8150B can recognize and post fast back-to-back write transactions. When PI7C8150B cannot accept the second transaction because of buffer space limitations, it returns a target retry to the initiator. The fast back-to-back enable bit must be set in the command register for upstream write transactions, and in the bridge control register for downstream write transactions. 15-0048 Page 26 of 107 15-0048 PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE READ TRANSACTIONS Delayed read forwarding is used for all read transactions crossing PI7C8150B. Delayed read transactions are treated as either prefetchable or non-prefetchable. Table 3-5 shows the read behavior, prefetchable or non-prefetchable, for each type of read operation. When the transaction has been completed on the target bus, and the delayed read data is at the head of the read data queue, and all ordering constraints with posted write transactions have been satisfied, the PI7C8150B transfers the data to the initiator when the initiator repeats the transaction. For memory read transactions, PI7C8150B aliases the memory read, memory read line, and memory read multiple bus commands when matching the bus command of the transaction to the bus command in the delayed transaction queue. PI7C8150B returns a target disconnect along with the transfer of the last DWORD of read data to the initiator. If PI7C8150B initiator terminates the transaction before all read data has been transferred, the remaining read data left in data buffers is discarded. When the master repeats the transaction and starts transferring prefetchable read data from data buffers while the read transaction on the target bus is still in progress and before a read boundary is reached on the target bus, the read transaction starts operating in flow-through mode. Because data is flowing through the data buffers from the target to the initiator, long read bursts can then be sustained. In this case, the read transaction is allowed to continue until the initiator terminates the transaction, or until an aligned 4KB address boundary is reached, or until the buffer fills, whichever comes first. When the buffer empties, PI7C8150B reflects the stalled condition to the initiator by disconnecting the initiator with data. The initiator may retry the transaction later if data are needed. If the initiator does not need any more data, the initiator will not continue the disconnected transaction. In this case, PI7C8150B will start the master timeout timer. The remaining read data will be discarded after the master timeout timer expires. To provide better latency, if there are any other Page 29 of 107 15-0048 PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE pending data for other transactions in the RDB Read Data Buffer , the remaining read data will be discarded even though the master timeout timer has not expired. PI7C8150B implements a master timeout timer that starts counting when the delayed read completion is at the head of the delayed transaction queue, and the read data is at the head of the read data queue. The initial value of this timer is programmable through configuration register. If the initiator does not repeat the read transaction and before the master timeout timer expires 215 default , PI7C8150B discards the read transaction and read data from its queues. PI7C8150B also conditionally asserts P_SERR_L see Section PI7C8150B has the capability to post multiple delayed read requests, up to a maximum of four in each direction. If an initiator starts a read transaction that matches the address and read command of a read transaction that is already queued, the current read command is not posted as it is already contained in the delayed transaction queue. See Section 5 for a discussion of how delayed read transactions are ordered when crossing PI7C8150B. FAST BACK-TO-BACK READ TRANSACTION PI7C8150B can recognize fast back-to-back read transactions. CONFIGURATION TRANSACTIONS Configuration transactions are used to initialize a PCI system. Every PCI device has a configuration space that is accessed by configuration commands. All registers are accessible in configuration space only. In addition to accepting configuration transactions for initialization of its own configuration space, the PI7C8150B also forwards configuration transactions for device initialization in hierarchical PCI systems, as well as for special cycle generation. To support hierarchical PCI bus systems, two types of configuration transactions are specified Type 0 and Type Type 0 configuration transactions are issued when the intended target resides on the same PCI bus as the initiator. A Type 0 configuration transaction is identified by the configuration command and the lowest two bits of the address set to 00b. Type 1 configuration transactions are issued when the intended target resides on another PCI bus, or when a special cycle is to be generated on another PCI bus. A Type 1 configuration command is identified by the configuration command and the lowest two address bits set to 01b. The register number is found in both Type 0 and Type 1 formats and gives the DWORD address of the configuration register to be accessed. The function number is also included in both Type 0 and Type 1 formats and indicates which function of a multifunction device is to be accessed. For single-function devices, this value is not decoded. The addresses of Type 1 configuration transaction include a 5-bit field designating the device number that identifies the device on the target PCI bus that is to be accessed. In addition, the bus number in Type 1 transactions specifies the PCI bus to which the transaction is targeted. Page 30 of 107 15-0048 PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE TYPE 0 ACCESS TO PI7C8150B The configuration space is accessed by a Type 0 configuration transaction on the primary interface. The configuration space cannot be accessed from the secondary bus. The PI7C8150B responds to a Type 0 configuration transaction by asserting P_DEVSEL_L when the following conditions are met during the address phase: • The bus command is a configuration read or configuration write transaction. • Lowest two address bits P_AD[1:0] must be 00b. • Signal P_IDSEL must be asserted. PI7C8150B limits all configuration access to a single DWORD data transfer and returns target-disconnect with the first data transfer if additional data phases are requested. Because read transactions to configuration space do not have side effects, all bytes in the requested DWORD are returned, regardless of the value of the byte enable bits. Type 0 configuration write and read transactions do not use data buffers that is, these transactions are completed immediately, regardless of the state of the data buffers. The PI7C8150B ignores all Type 0 transactions initiated on the secondary interface. TYPE 1 TO TYPE 0 CONVERSION Type 1 configuration transactions are used specifically for device configuration in a hierarchical PCI bus system. A PCI-to-PCI bridge is the only type of device that should respond to a Type 1 configuration command. Type 1 configuration commands are used when the configuration access is intended for a PCI device that resides on a PCI bus other than the one where the Type 1 transaction is generated. PI7C8150B performs a Type 1 to Type 0 translation when the Type 1 transaction is generated on the primary bus and is intended for a device attached directly to the secondary bus. PI7C8150B must convert the configuration command to a Type 0 format so that the secondary bus device can respond to it. Type 1 to Type 0 translations are performed only in the downstream direction that is, PI7C8150B generates a Type 0 transaction only on the secondary bus, and never on the primary bus. PI7C8150B responds to a Type 1 configuration transaction and translates it into a Type 0 transaction on the secondary bus when the following conditions are met during the address phase: • The lowest two address bits on P_AD[1:0] are 01b. • The bus number in address field P_AD[23:16] is equal to the value in the secondary bus number register in configuration space. • The bus command on P_CBE[3:0] is a configuration read or configuration write transaction. When PI7C8150B translates the Type 1 transaction to a Type 0 transaction on the secondary interface, it performs the following translations to the address: • Sets the lowest two address bits on S_AD[1:0]. Page 31 of 107 PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE • Decodes the device number and drives the bit pattern specified in Table 3-6 on S_AD[31:16] for the purpose of asserting the device’s IDSEL signal. • Sets S_AD[15:11] to TRANSACTION ORDERING 15-0048 Page 46 of 107 15-0048 PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE TRANSACTIONS GOVERNED BY ORDERING RULES Ordering relationships are established for the following classes of transactions crossing PI7C8150B: Posted write transactions, comprised of memory write and memory write and invalidate transactions. Posted write transactions complete at the source before they complete at the destination that is, data is written into intermediate data buffers before it reaches the target. Delayed write request transactions, comprised of I/O write and configuration write transactions. Delayed write requests are terminated by target retry on the initiator bus and are queued in the delayed transaction queue. A delayed write transaction must complete on the target bus before it completes on the initiator bus. Delayed write completion transactions, comprised of I/O write and configuration write transactions. Delayed write completion transactions complete on the target bus, and the target response is queued in the buffers. A delayed write completion transaction proceeds in the direction opposite that of the original delayed write request that is, a delayed write completion transaction proceeds from the target bus to the initiator bus. Delayed read request transactions, comprised of all memory read, I/O read, and configuration read transactions. Delayed read requests are terminated by target retry on the initiator bus and are queued in the delayed transaction queue. Delayed read completion transactions, comprised of all memory read, I/O read, & configuration read transactions. Delayed read completion transactions complete on the target bus, and the read data is queued in the read data buffers. A delayed read completion transaction proceeds in the direction opposite that of the original delayed read request that is, a delayed read completion transaction proceeds from the target bus to the initiator bus. PI7C8150B does not combine or merge write transactions: • PI7C8150B does not combine separate write transactions into a single write optimization is best implemented in the originating master. • PI7C8150B does not merge bytes on separate masked write transactions to the same DWORD optimization is also best implemented in the originating master. • PI7C8150B does not collapse sequential write transactions to the same address into a single write PCI Local Bus Specification does not permit this combining of transactions. GENERAL ORDERING GUIDELINES Independent transactions on primary and secondary buses have a relationship only when those transactions cross PI7C8150B. The following general ordering guidelines govern transactions crossing PI7C8150B: Page 47 of 107 PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE • The ordering relationship of a transaction with respect to other transactions is determined when the transaction completes, that is, when a transaction ends with a termination other than target retry. • Requests terminated with target retry can be accepted and completed in any order with respect to other transactions that have been terminated with target retry. If the order of completion of delayed requests is important, the initiator should not start a second delayed transaction until the first one has been completed. If more than one delayed transaction is initiated, the initiator should repeat all delayed transaction requests, using some fairness algorithm. Repeating a delayed transaction cannot be contingent on completion of another delayed transaction. Otherwise, a deadlock can occur. • Write transactions flowing in one direction have no ordering requirements with respect to write transactions flowing in the other direction. PI7C8150B can accept posted write transactions on both interfaces at the same time, as well as initiate posted write transactions on both interfaces at the same time. • The acceptance of a posted memory write transaction as a target can never be contingent on the completion of a non-locked, non-posted transaction as a master. This is true for PI7C8150B and must also be true for other bus agents. Otherwise, a deadlock can occur. • PI7C8150B accepts posted write transactions, regardless of the state of completion of any delayed transactions being forwarded across PI7C8150B. ORDERING RULES Table 5-1 shows the ordering relationships of all the transactions and refers by number to the ordering rules that follow. Table Summary of Transaction Ordering Pass Posted Delayed Delayed Delayed Read Delayed Write Write Read Write Completion Completion Request Request Posted Write Yes5 Yes5 Yes5 Yes5 Delayed Read Request Delayed Write Request Delayed Read Completion Delayed Write Completion Note The superscript accompanying some of the table entries refers to any applicable ordering rule listed in this section. Many entries are not governed by these ordering rules; therefore, the implementation can choose whether or not the transactions pass each other. The entries without superscripts reflect the PI7C8150B’s implementation choices. The following ordering rules describe the transaction relationships. Each ordering rule is followed by an explanation, and the ordering rules are referred to by number in Table These ordering rules apply to posted write transactions, delayed write and read requests, and delayed write and read completion transactions crossing PI7C8150B in the same direction. Note that delayed completion transactions cross PI7C8150B in the direction opposite that of the corresponding delayed requests. 15-0048 Page 48 of 107 PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE Posted write transactions must complete on the target bus in the order in which they were received on the initiator bus. The subsequent posted write transaction can be setting a flag that covers the data in the first posted write transaction if the second transaction were to complete before the first transaction, a device checking the flag could subsequently consume stale data. A delayed read request traveling in the same direction as a previously queued posted write transaction must push the posted write data ahead of it. The posted write transaction must complete on the target bus before the delayed read request can be attempted on the target bus. The read transaction can be to the same location as the write data, so if the read transaction were to pass the write transaction, it would return stale data. A delayed read completion must ‘‘pull’’ ahead of previously queued posted write data traveling in the same direction. In this case, the read data is traveling in the same direction as the write data, and the initiator of the read transaction is on the same side of PI7C8150B as the target of the write transaction. The posted write transaction must complete to the target before the read data is returned to the initiator. The read transaction can be a reading to a status register of the initiator of the posted write data and therefore should not complete until the write transaction is complete. Delayed write requests cannot pass previously queued posted write data. For posted memory write transactions, the delayed write transaction can set a flag that covers the data in the posted write transaction. If the delayed write request were to complete before the earlier posted write transaction, a device checking the flag could subsequently consume stale data. Posted write transactions must be given opportunities to pass delayed read and write requests and completions. Otherwise, deadlocks may occur when some bridges which support delayed transactions and other bridges which do not support delayed transactions are being used in the same system. A fairness algorithm is used to arbitrate between the posted write queue and the delayed transaction queue. DATA SYNCHRONIZATION • The device signaling the interrupt performs a read of the data just written software . • The device driver performs a read operation to any register in the interrupting device before accessing data written by the device software . • System hardware guarantees that write buffers are flushed before interrupts are forwarded. PI7C8150B does not have a hardware mechanism to guarantee data synchronization for posted write transactions. Therefore, all posted write transactions must be followed by a read operation, either from the device to the location just written or some other location along the same path , or from the device driver to one of the device registers. 15-0048 Page 49 of 107 15-0048 PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE ERROR HANDLING PI7C8150B checks, forwards, and generates parity on both the primary and secondary interfaces. To maintain transparency, PI7C8150B always tries to forward the existing parity condition on one bus to the other bus, along with address and data. PI7C8150B always attempts to be transparent when reporting errors, but this is not always possible, given the presence of posted data and delayed transactions. To support error reporting on the PCI bus, PI7C8150B implements the following: • PERR_L and SERR_L signals on both the primary and secondary interfaces • Primary status and secondary status registers • The device-specific P_SERR_L event disable register This chapter provides detailed information about how PI7C8150B handles errors. It also describes error status reporting and error operation disabling. ADDRESS PARITY ERRORS PI7C8150B checks address parity for all transactions on both buses, for all address and all bus commands. When PI7C8150B detects an address parity error on the primary interface, the following events occur: • If the parity error response bit is set in the command register, PI7C8150B does not claim the transaction with P_DEVSEL_L this may allow the transaction to terminate in a master abort. If parity error response bit is not set, PI7C8150B proceeds normally and accepts the transaction if it is directed to or across PI7C8150B. • PI7C8150B sets the detected parity error bit in the status register. • PI7C8150B asserts P_SERR_L and sets signaled system error bit in the status register, if both the following conditions are met: • The SERR_L enable bit is set in the command register. • The parity error response bit is set in the command register. When PI7C8150B detects an address parity error on the secondary interface, the following events occur: • If the parity error response bit is set in the bridge control register, PI7C8150B does not claim the transaction with S_DEVSEL_L this may allow the transaction to terminate in a master abort. If parity error response bit is not set, PI7C8150B proceeds normally and accepts transaction if it is directed to or across PI7C8150B. • PI7C8150B sets the detected parity error bit in the secondary status register. • PI7C8150B asserts P_SERR_L and sets signaled system error bit in status register, if both of the following conditions are met: • The SERR_L enable bit is set in the command register. Page 50 of 107 15-0048 PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE • The parity error response bit is set in the bridge control register. PART NUMBER ORDERING INFORMATION Part Number PI7C8150BMA PI7C8150BND PI7C8150BMA-33 PI7C8150BND-33 PI7C8150BMAE PI7C8150BNDE PI7C8150BMAI PI7C8150BNDI PI7C8150BMAI-33 PI7C8150BNDI-33 PI7C8150BMAIE PI7C8150BNDIE Speed 66 MHz 66 MHz 33 MHz 33 MHz 66 MHz 66 MHz 66 MHz 66 MHz 33 MHz 33 MHz 66 MHz 66 MHz Pin Package 208 FQFP 256 PBGA 208 FQFP 256 PBGA 208 FQFP Pb-free & Green 256 PBGA Pb-free & Green 208 FQFP 256 PBGA 208 FQFP 256 PBGA 208 FQFP Pb-free & Green 256 PBGA Pb-free & Green Temperature 0°C to 85°C 0°C to 85°C 0°C to 85°C 0°C to 85°C 0°C to 85°C 0°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C 15-0048 Page 106 of 107 PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE 15-0048 Page 107 of 107

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PI7C8150B

Asynchronous 2-Port PCI-to-PCI Bridge
15-0048
1545 Barber Lane Milpitas, CA 95035 Telephone 408-232-9100 Fax 408-434-1040

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PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

LIFE SUPPORT POLICY

Pericom Semiconductor Corporation’s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of PSC.
1 Life support devices or system are devices or systems which a Are intended for surgical implant into the body or b Support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Pericom Semiconductor Corporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom Semiconductor does not assume any responsibility for use of any circuitry described other than the circuitry embodied in a Pericom Semiconductor product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Pericom Semiconductor Corporation.

All other trademarks are of their respective companies.
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Date 03/26/03 05/14/03
06/10/03 06/25/03
07/31/03
10/20/03 02/13/04 05/20/04 07/06/04 08/12/04
09/23/04
01/10/05 04/05/06 04/1715
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TABLE OF CONTENTS
1 INTRODUCTION
2 SIGNAL DEFINITIONS

SIGNAL TYPES SIGNALS

PRIMARY BUS INTERFACE SIGNALS CLOCK SIGNALS MISCELLANEOUS GENERAL PURPOSE I/O INTERFACE SIGNALS JTAG BOUNDARY SCAN SIGNALS POWER AND PIN LIST 208-PIN FQFP PIN LIST 256-BALL
3 PCI BUS OPERATION

TYPES OF TRANSACTIONS SINGLE ADDRESS DEVICE SELECT DEVSEL_L DATA WRITE TRANSACTIONS

MEMORY WRITE MEMORY WRITE AND INVALIDATE DELAYED WRITE TRANSACTION ADDRESS BUFFERING MULTIPLE WRITE FAST BACK-TO-BACK TRANSACTIONS READ TRANSACTIONS PREFETCHABLE READ NON-PREFETCHABLE READ TRANSACTIONS READ PREFETCH ADDRESS BOUNDARIES DELAYED READ REQUESTS DELAYED READ COMPLETION WITH TARGET DELAYED READ COMPLETION ON INITIATOR FAST BACK-TO-BACK READ TRANSACTION CONFIGURATION TRANSACTIONS TYPE 0 ACCESS TO TYPE 1 TO TYPE 0 CONVERSION TYPE 1 TO TYPE 1 FORWARDING SPECIAL CYCLES TRANSACTION MASTER TERMINATION INITIATED BY PI7C8150B MASTER ABORT RECEIVED BY PI7C8150B TARGET TERMINATION RECEIVED BY PI7C8150B TARGET TERMINATION INITIATED BY
4 ADDRESS

ADDRESS RANGES I/O ADDRESS DECODING

I/O BASE AND LIMIT ADDRESS REGISTER ISA MEMORY ADDRESS MEMORY-MAPPED I/O BASE AND LIMIT ADDRESS REGISTERS
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PREFETCHABLE MEMORY BASE AND LIMIT ADDRESS REGISTERS VGA SUPPORT

VGA MODE VGA SNOOP
5 TRANSACTION
TRANSACTIONS GOVERNED BY ORDERING RULES GENERAL ORDERING RULES DATA SYNCHRONIZATION
6 ERROR

ADDRESS PARITY DATA PARITY

CONFIGURATION WRITE TRANSACTIONS TO CONFIGURATION SPACE READ TRANSACTIONS DELAYED WRITE POSTED WRITE TRANSACTIONS DATA PARITY ERROR REPORTING SUMMARY SYSTEM ERROR SERR_L REPORTING
7 EXCLUSIVE ACCESS

CONCURRENT LOCKS ACQUIRING EXCLUSIVE ACCESS ACROSS PI7C8150B

LOCKED TRANSACTIONS IN DOWNSTREAM DIRECTION LOCKED TRANSACTION IN UPSTREAM DIRECTION ENDING EXCLUSIVE ACCESS
8 PCI BUS ARBITRATION

PRIMARY PCI BUS SECONDARY PCI BUS

SECONDARY BUS ARBITRATION USING THE INTERNAL ARBITER PREEMPTION SECONDARY BUS ARBITRATION USING AN EXTERNAL ARBITER.......................65 BUS
9 CLOCKS

PRIMARY CLOCK INPUTS SECONDARY CLOCK ASYNCHRONOUS MODE
10 GENERAL PURPOSE I/O

GPIO CONTROL REGISTERS SECONDARY CLOCK CONTROL LIVE INSERTION
11 PCI POWER MANAGEMENT
12 RESET

PRIMARY INTERFACE RESET SECONDARY INTERFACE RESET CHIP RESET
13 SUPPORTED

PRIMARY INTERFACE
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SECONDARY INTERFACE
14 CONFIGURATION

CONFIGURATION

VENDOR ID REGISTER OFFSET 00h

DEVICE ID REGISTER OFFSET 00h

COMMAND REGISTER OFFSET 04h

STATUS REGISTER OFFSET 04h

CLASS CODE REGISTER OFFSET

CACHE LINE SIZE REGISTER OFFSET 0Ch

PRIMARY LATENCY TIMER REGISTER OFFSET 0Ch

HEADER TYPE REGISTER OFFSET

PRIMARY BUS NUMBER REGISTSER OFFSET 18h

SECONDARY BUS NUMBER REGISTER OFFSET 18h

SUBORDINATE BUS NUMBER REGISTER OFFSET

SECONDARY LATENCY TIMER REGISTER OFFSET 18h

I/O BASE REGISTER OFFSET

I/O LIMIT REGISTER OFFSET 1Ch

SECONDARY STATUS REGISTER OFFSET

MEMORY BASE REGISTER OFFSET 20h
208-PIN FQFP PACKAGE 256-BALL PBGA PACKAGE PART NUMBER ORDERING INFORMATION
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LIST OF TABLES
TABLE PIN LIST 208-PIN TABLE PIN LIST 256-PIN TABLE PCI TABLE WRITE TRANSACTION FORWARDING TABLE WRITE TRANSACTION DISCONNECT ADDRESS BOUNDARIES TABLE READ PREFETCH ADDRESS TABLE READ TRANSACTION PREFETCHING TABLE DEVICE NUMBER TO IDSEL S_AD PIN MAPPING TABLE DELAYED WRITE TARGET TERMINATION RESPONSE TABLE RESPONSE TO POSTED WRITE TARGET TERMINATION TABLE RESPONSE TO DELAYED READ TARGET TABLE SUMMARY OF TRANSACTION ORDERING TABLE SETTING THE PRIMARY INTERFACE DETECTED PARITY ERROR TABLE SETTING SECONDARY INTERFACE DETECTED PARITY ERROR TABLE SETTING PRIMARY INTERFACE MASTER DATA PARITY ERROR DETECTED BIT TABLE SETTING SECONDARY INTERFACE MASTER DATA PARITY ERROR DETECTED BIT TABLE ASSERTION OF P_PERR_L TABLE ASSERTION OF S_PERR_L TABLE ASSERTION OF P_SERR_L FOR DATA PARITY TABLE GPIO OPERATION TABLE GPIO SERIAL DATA FORMAT TABLE POWER MANAGEMENT TRANSITIONS TABLE TAP PINS TABLE JTAG BOUNDARY REGISTER

LIST OF FIGURES

FIGURE 8-1 SECONDARY ARBITER EXAMPLE FIGURE 16-1 TEST ACCESS PORT BLOCK DIAGRAM FIGURE 17-1 PCI SIGNAL TIMING MEASUREMENT FIGURE 18-1 208-PIN FQFP PACKAGE OUTLINE FIGURE 18-2 256-PIN PBGA PACKAGE
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INTRODUCTION

Product Description

Product Features

Supported modes of asynchronous operation

Primary MHz

PI7C8150B
25MHz to 66MHz

PI7C8150B-33
25MHz to 33MHz

Secondary MHz 25MHz to 66MHz 25MHz to 33MHz

Supported modes of synchronous operation

Primary MHz

PI7C8150B

PI7C8150B

PI7C8150B

PI7C8150B

PI7C8150B-33

PI7C8150B-33

Secondary MHz 66 33 50 25
• Provides internal arbitration for one set of nine secondary bus masters Programmable 2-level priority arbiter Disable control for use of external arbiter
• Supports posted write buffers in all directions
• Four 128 byte FIFO’s for delay transactions
• Two 128 byte FIFO’s for posted memory transactions
• Enhanced address decoding
• Temperature support

Extended Commercial range 0°C to 85°C Industrial range -40°C to 85°C
• IEEE JTAG interface support
• 3.3V core 3.3V and 5V signaling
• Packaging 208-pin FQFP and 256-pin PBGA Pb-free & Green

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SIGNAL DEFINITIONS

Signal Types

Signal Type I O P TS STS

Description Input Only Output Only Power Tri-State bi-directional Sustained Tri-State. Active LOW signal must be pulled HIGH for 1 cycle when deasserting. Open Drain

Signals

Note Signal names that end with “_L” are active LOW.
When a write transaction is first detected on the initiator bus, and PI7C8150B forwards it as a delayed transaction, PI7C8150B claims the access by asserting DEVSEL_L and returns a target retry to the initiator. During the address phase, PI7C8150B samples the bus command, address, and address parity one cycle later. After IRDY_L is asserted, PI7C8150B also samples the first data DWORD, byte enable bits, and data parity. This information is placed into the delayed transaction queue. The transaction is queued only if no other existing delayed transactions have the same address and command, and if the delayed transaction queue is not full. When the delayed write transaction moves to the head of the delayed transaction queue and all ordering constraints with posted data are satisfied. The PI7C8150B initiates the transaction on the target bus. PI7C8150B transfers the write data to the target. If PI7C8150B receives a target retry in response to the write transaction on the target bus, it continues to repeat the write transaction until the data transfer is completed, or until an error condition is encountered.

If PI7C8150B is unable to deliver write data after 224 default or 232 maximum attempts, PI7C8150B will report a system error. PI7C8150B also asserts P_SERR_L if the primary SERR_L enable bit is set in the command register. See Section for information on the assertion of P_SERR_L. When the initiator repeats the same write transaction same command, address, byte enable bits, and data , and the completed delayed transaction is at the head of the queue, the PI7C8150B claims the access by asserting DEVSEL_L and returns TRDY_L to the initiator, to indicate that the write data was transferred. If the initiator requests multiple DWORD, PI7C8150B also asserts STOP_L in conjunction with TRDY_L to signal a target disconnect. Note that only those bytes of write data with valid byte enable bits are compared. If any of the byte enable bits are turned off driven HIGH , the corresponding byte of write data is not compared.

If the initiator repeats the write transaction before the data has been transferred to the target, PI7C8150B returns a target retry to the initiator. PI7C8150B continues to return a target retry to the initiator until write data is delivered to the target, or until an error condition is encountered. When the write transaction is repeated, PI7C8150B does not make a new entry into the delayed transaction queue. Section provides detailed information about how PI7C8150B responds to target termination during delayed write transactions.

PI7C8150B implements a discard timer that starts counting when the delayed write completion is at the head of the delayed transaction completion queue. The initial value of this timer can be set to the retry counter register offset 78h.

If the initiator does not repeat the delayed write transaction before the discard

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timer expires, PI7C8150B discards the delayed write completion from the delayed transaction completion queue. PI7C8150B also conditionally asserts P_SERR_L see Section

WRITE TRANSACTION ADDRESS BOUNDARIES

PI7C8150B imposes internal address boundaries when accepting write data. The aligned address boundaries are used to prevent PI7C8150B from continuing a transaction over a device address boundary and to provide an upper limit on maximum latency. PI7C78150 returns a target disconnect to the initiator when it reaches the aligned address boundaries under conditions shown in Table

Table Write Transaction Disconnect Address Boundaries

Type of Transaction

Condition

Aligned Address Boundary

Delayed Write

Disconnects after one data transfer

Posted Memory Write

Memory write disconnect control 4KB aligned address boundary bit = 0 1

Posted Memory Write

Memory write disconnect control Disconnects at cache line boundary bit = 1

Posted Memory Write and Cache line size 1, 2, 4, 8, 16
4KB aligned address boundary

Invalidate

Posted Memory Write and Cache line size = 1, 2, 4, 8, 16

Cache line boundary if posted memory

Invalidate
write data FIFO does not have enough
space for the cache line

Note Memory write disconnect control bit is bit 1 of the chip control register at offset 40h in the
configuration space.

BUFFERING MULTIPLE WRITE TRANSACTIONS

PI7C8150B continues to accept posted memory write transactions as long as space for at least one DWORD of data in the posted write data buffer remains. If the posted write data buffer fills before the initiator terminates the write transaction, PI7C8150B returns a target disconnect to the initiator.

Delayed write transactions are posted as long as at least one open entry in the delayed transaction queue exists. Therefore, several posted and delayed write transactions can exist in data buffers at the same time. See Chapter 6 for information about how multiple posted and delayed write transactions are ordered.

FAST BACK-TO-BACK TRANSACTIONS

PI7C8150B can recognize and post fast back-to-back write transactions. When PI7C8150B cannot accept the second transaction because of buffer space limitations, it returns a target retry to the initiator. The fast back-to-back enable bit must be set in the command register for upstream write transactions, and in the bridge control register for downstream write transactions.
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READ TRANSACTIONS

Delayed read forwarding is used for all read transactions crossing PI7C8150B. Delayed read transactions are treated as either prefetchable or non-prefetchable. Table 3-5 shows the read behavior, prefetchable or non-prefetchable, for each type of read operation.
When the transaction has been completed on the target bus, and the delayed read data is at the head of the read data queue, and all ordering constraints with posted write transactions have been satisfied, the PI7C8150B transfers the data to the initiator when the initiator repeats the transaction. For memory read transactions, PI7C8150B aliases the memory read, memory read line, and memory read multiple bus commands when matching the bus command of the transaction to the bus command in the delayed transaction queue. PI7C8150B returns a target disconnect along with the transfer of the last DWORD of read data to the initiator. If PI7C8150B initiator terminates the transaction before all read data has been transferred, the remaining read data left in data buffers is discarded.

When the master repeats the transaction and starts transferring prefetchable read data from data buffers while the read transaction on the target bus is still in progress and before a read boundary is reached on the target bus, the read transaction starts operating in flow-through mode. Because data is flowing through the data buffers from the target to the initiator, long read bursts can then be sustained. In this case, the read transaction is allowed to continue until the initiator terminates the transaction, or until an aligned 4KB address boundary is reached, or until the buffer fills, whichever comes first. When the buffer empties, PI7C8150B reflects the stalled condition to the initiator by disconnecting the initiator with data. The initiator may retry the transaction later if data are needed. If the initiator does not need any more data, the initiator will not continue the disconnected transaction. In this case, PI7C8150B will start the master timeout timer. The remaining read data will be discarded after the master timeout timer expires. To provide better latency, if there are any other

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pending data for other transactions in the RDB Read Data Buffer , the remaining read data will be discarded even though the master timeout timer has not expired.

PI7C8150B implements a master timeout timer that starts counting when the delayed read completion is at the head of the delayed transaction queue, and the read data is at the head of the read data queue. The initial value of this timer is programmable through configuration register. If the initiator does not repeat the read transaction and before the master timeout timer expires 215 default , PI7C8150B discards the read transaction and read data from its queues. PI7C8150B also conditionally asserts P_SERR_L see Section

PI7C8150B has the capability to post multiple delayed read requests, up to a maximum of four in each direction. If an initiator starts a read transaction that matches the address and read command of a read transaction that is already queued, the current read command is not posted as it is already contained in the delayed transaction queue.

See Section 5 for a discussion of how delayed read transactions are ordered when crossing PI7C8150B.

FAST BACK-TO-BACK READ TRANSACTION

PI7C8150B can recognize fast back-to-back read transactions.

CONFIGURATION TRANSACTIONS

Configuration transactions are used to initialize a PCI system. Every PCI device has a configuration space that is accessed by configuration commands. All registers are accessible in configuration space only.

In addition to accepting configuration transactions for initialization of its own configuration space, the PI7C8150B also forwards configuration transactions for device initialization in hierarchical PCI systems, as well as for special cycle generation.

To support hierarchical PCI bus systems, two types of configuration transactions are specified Type 0 and Type

Type 0 configuration transactions are issued when the intended target resides on the same PCI bus as the initiator. A Type 0 configuration transaction is identified by the configuration command and the lowest two bits of the address set to 00b.

Type 1 configuration transactions are issued when the intended target resides on another PCI bus, or when a special cycle is to be generated on another PCI bus. A Type 1 configuration command is identified by the configuration command and the lowest two address bits set to 01b.

The register number is found in both Type 0 and Type 1 formats and gives the DWORD address of the configuration register to be accessed. The function number is also included in both Type 0 and Type 1 formats and indicates which function of a multifunction device is to be accessed. For single-function devices, this value is not decoded. The addresses of Type 1 configuration transaction include a 5-bit field designating the device number that identifies the device on the target PCI bus that is to be accessed. In addition, the bus number in Type 1 transactions specifies the PCI bus to which the transaction is targeted.

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TYPE 0 ACCESS TO PI7C8150B

The configuration space is accessed by a Type 0 configuration transaction on the primary interface. The configuration space cannot be accessed from the secondary bus. The PI7C8150B responds to a Type 0 configuration transaction by asserting P_DEVSEL_L when the following conditions are met during the address phase:
• The bus command is a configuration read or configuration write transaction.
• Lowest two address bits P_AD[1:0] must be 00b.
• Signal P_IDSEL must be asserted.

PI7C8150B limits all configuration access to a single DWORD data transfer and returns target-disconnect with the first data transfer if additional data phases are requested. Because read transactions to configuration space do not have side effects, all bytes in the requested DWORD are returned, regardless of the value of the byte enable bits.

Type 0 configuration write and read transactions do not use data buffers that is, these transactions are completed immediately, regardless of the state of the data buffers. The PI7C8150B ignores all Type 0 transactions initiated on the secondary interface.

TYPE 1 TO TYPE 0 CONVERSION

Type 1 configuration transactions are used specifically for device configuration in a hierarchical PCI bus system. A PCI-to-PCI bridge is the only type of device that should respond to a Type 1 configuration command. Type 1 configuration commands are used when the configuration access is intended for a PCI device that resides on a PCI bus other than the one where the Type 1 transaction is generated.

PI7C8150B performs a Type 1 to Type 0 translation when the Type 1 transaction is generated on the primary bus and is intended for a device attached directly to the secondary bus. PI7C8150B must convert the configuration command to a Type 0 format so that the secondary bus device can respond to it. Type 1 to Type 0 translations are performed only in the downstream direction that is, PI7C8150B generates a Type 0 transaction only on the secondary bus, and never on the primary bus.

PI7C8150B responds to a Type 1 configuration transaction and translates it into a Type 0 transaction on the secondary bus when the following conditions are met during the address phase:
• The lowest two address bits on P_AD[1:0] are 01b.
• The bus number in address field P_AD[23:16] is equal to the value in the secondary bus number register in configuration space.
• The bus command on P_CBE[3:0] is a configuration read or configuration write transaction.

When PI7C8150B translates the Type 1 transaction to a Type 0 transaction on the secondary interface, it performs the following translations to the address:
• Sets the lowest two address bits on S_AD[1:0].

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• Decodes the device number and drives the bit pattern specified in Table 3-6 on S_AD[31:16] for the purpose of asserting the device’s IDSEL signal.
• Sets S_AD[15:11] to
TRANSACTION ORDERING
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TRANSACTIONS GOVERNED BY ORDERING RULES
Ordering relationships are established for the following classes of transactions crossing PI7C8150B:

Posted write transactions, comprised of memory write and memory write and invalidate transactions. Posted write transactions complete at the source before they complete at the destination that is, data is written into intermediate data buffers before it reaches the target.

Delayed write request transactions, comprised of I/O write and configuration write transactions. Delayed write requests are terminated by target retry on the initiator bus and are queued in the delayed transaction queue. A delayed write transaction must complete on the target bus before it completes on the initiator bus.

Delayed write completion transactions, comprised of I/O write and configuration write transactions. Delayed write completion transactions complete on the target bus, and the target response is queued in the buffers. A delayed write completion transaction proceeds in the direction opposite that of the original delayed write request that is, a delayed write completion transaction proceeds from the target bus to the initiator bus.

Delayed read request transactions, comprised of all memory read, I/O read, and configuration read transactions. Delayed read requests are terminated by target retry on the initiator bus and are queued in the delayed transaction queue.

Delayed read completion transactions, comprised of all memory read, I/O read, & configuration read transactions. Delayed read completion transactions complete on the target bus, and the read data is queued in the read data buffers. A delayed read completion transaction proceeds in the direction opposite that of the original delayed read request that is, a delayed read completion transaction proceeds from the target bus to the initiator bus.

PI7C8150B does not combine or merge write transactions:
• PI7C8150B does not combine separate write transactions into a single write optimization is best implemented in the originating master.
• PI7C8150B does not merge bytes on separate masked write transactions to the same DWORD optimization is also best implemented in the originating master.
• PI7C8150B does not collapse sequential write transactions to the same address into a single write PCI Local Bus Specification does not permit this combining of transactions.
GENERAL ORDERING GUIDELINES

Independent transactions on primary and secondary buses have a relationship only when those transactions cross PI7C8150B.
The following general ordering guidelines govern transactions crossing PI7C8150B:

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• The ordering relationship of a transaction with respect to other transactions is determined when the transaction completes, that is, when a transaction ends with a termination other than target retry.
• Requests terminated with target retry can be accepted and completed in any order with respect to other transactions that have been terminated with target retry. If the order of completion of delayed requests is important, the initiator should not start a second delayed transaction until the first one has been completed. If more than one delayed transaction is initiated, the initiator should repeat all delayed transaction requests, using some fairness algorithm. Repeating a delayed transaction cannot be contingent on completion of another delayed transaction. Otherwise, a deadlock can occur.
• Write transactions flowing in one direction have no ordering requirements with respect to write transactions flowing in the other direction. PI7C8150B can accept posted write transactions on both interfaces at the same time, as well as initiate posted write transactions on both interfaces at the same time.
• The acceptance of a posted memory write transaction as a target can never be contingent on the completion of a non-locked, non-posted transaction as a master. This is true for PI7C8150B and must also be true for other bus agents. Otherwise, a deadlock can occur.
• PI7C8150B accepts posted write transactions, regardless of the state of completion of any delayed transactions being forwarded across PI7C8150B.
ORDERING RULES
Table 5-1 shows the ordering relationships of all the transactions and refers by number to the ordering rules that follow.
Table Summary of Transaction Ordering

Pass

Posted

Delayed

Delayed

Delayed Read Delayed Write

Write

Read

Write

Completion

Completion

Request

Request

Posted Write

Yes5

Yes5

Yes5

Yes5

Delayed Read Request

Delayed Write Request

Delayed Read

Completion

Delayed Write

Completion

Note The superscript accompanying some of the table entries refers to any applicable
ordering rule listed in this section. Many entries are not governed by these ordering rules;
therefore, the implementation can choose whether or not the transactions pass each other.

The entries without superscripts reflect the PI7C8150B’s implementation choices.
The following ordering rules describe the transaction relationships. Each ordering rule is followed by an explanation, and the ordering rules are referred to by number in Table These ordering rules apply to posted write transactions, delayed write and read requests, and delayed write and read completion transactions crossing PI7C8150B in the same direction. Note that delayed completion transactions cross PI7C8150B in the direction opposite that of the corresponding delayed requests.
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Posted write transactions must complete on the target bus in the order in which they were received on the initiator bus. The subsequent posted write transaction can be setting a flag that covers the data in the first posted write transaction if the second transaction were to complete before the first transaction, a device checking the flag could subsequently consume stale data.

A delayed read request traveling in the same direction as a previously queued posted write transaction must push the posted write data ahead of it. The posted write transaction must complete on the target bus before the delayed read request can be attempted on the target bus. The read transaction can be to the same location as the write data, so if the read transaction were to pass the write transaction, it would return stale data.

A delayed read completion must ‘‘pull’’ ahead of previously queued posted write data traveling in the same direction. In this case, the read data is traveling in the same direction as the write data, and the initiator of the read transaction is on the same side of PI7C8150B as the target of the write transaction. The posted write transaction must complete to the target before the read data is returned to the initiator. The read transaction can be a reading to a status register of the initiator of the posted write data and therefore should not complete until the write transaction is complete.

Delayed write requests cannot pass previously queued posted write data. For posted memory write transactions, the delayed write transaction can set a flag that covers the data in the posted write transaction. If the delayed write request were to complete before the earlier posted write transaction, a device checking the flag could subsequently consume stale data.

Posted write transactions must be given opportunities to pass delayed read and write requests and completions. Otherwise, deadlocks may occur when some bridges which support delayed transactions and other bridges which do not support delayed transactions are being used in the same system. A fairness algorithm is used to arbitrate between the posted write queue and the delayed transaction queue.

DATA SYNCHRONIZATION
• The device signaling the interrupt performs a read of the data just written software .
• The device driver performs a read operation to any register in the interrupting device before accessing data written by the device software .
• System hardware guarantees that write buffers are flushed before interrupts are forwarded.

PI7C8150B does not have a hardware mechanism to guarantee data synchronization for posted write transactions. Therefore, all posted write transactions must be followed by a read operation, either from the device to the location just written or some other location along the same path , or from the device driver to one of the device registers.
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ERROR HANDLING

PI7C8150B checks, forwards, and generates parity on both the primary and secondary interfaces. To maintain transparency, PI7C8150B always tries to forward the existing parity condition on one bus to the other bus, along with address and data. PI7C8150B always attempts to be transparent when reporting errors, but this is not always possible, given the presence of posted data and delayed transactions.

To support error reporting on the PCI bus, PI7C8150B implements the following:
• PERR_L and SERR_L signals on both the primary and secondary interfaces
• Primary status and secondary status registers
• The device-specific P_SERR_L event disable register

This chapter provides detailed information about how PI7C8150B handles errors. It also describes error status reporting and error operation disabling.

ADDRESS PARITY ERRORS

PI7C8150B checks address parity for all transactions on both buses, for all address and all bus commands. When PI7C8150B detects an address parity error on the primary interface, the following events occur:
• If the parity error response bit is set in the command register, PI7C8150B does not claim the transaction with P_DEVSEL_L this may allow the transaction to terminate in a master abort. If parity error response bit is not set, PI7C8150B proceeds normally and accepts the transaction if it is directed to or across PI7C8150B.
• PI7C8150B sets the detected parity error bit in the status register.
• PI7C8150B asserts P_SERR_L and sets signaled system error bit in the status register, if both the following conditions are met:
• The SERR_L enable bit is set in the command register.
• The parity error response bit is set in the command register.

When PI7C8150B detects an address parity error on the secondary interface, the following events occur:
• If the parity error response bit is set in the bridge control register, PI7C8150B does not claim the transaction with S_DEVSEL_L this may allow the transaction to terminate in a master abort. If parity error response bit is not set, PI7C8150B proceeds normally and accepts transaction if it is directed to or across PI7C8150B.
• PI7C8150B sets the detected parity error bit in the secondary status register.
• PI7C8150B asserts P_SERR_L and sets signaled system error bit in status register, if both of the following conditions are met:
• The SERR_L enable bit is set in the command register.

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• The parity error response bit is set in the bridge control register.
PART NUMBER ORDERING INFORMATION

Part Number PI7C8150BMA PI7C8150BND PI7C8150BMA-33 PI7C8150BND-33 PI7C8150BMAE PI7C8150BNDE PI7C8150BMAI PI7C8150BNDI PI7C8150BMAI-33 PI7C8150BNDI-33 PI7C8150BMAIE PI7C8150BNDIE

Speed 66 MHz 66 MHz 33 MHz 33 MHz 66 MHz 66 MHz 66 MHz 66 MHz 33 MHz 33 MHz 66 MHz 66 MHz

Pin Package 208 FQFP 256 PBGA 208 FQFP 256 PBGA 208 FQFP Pb-free & Green 256 PBGA Pb-free & Green 208 FQFP 256 PBGA 208 FQFP 256 PBGA 208 FQFP Pb-free & Green 256 PBGA Pb-free & Green

Temperature 0°C to 85°C 0°C to 85°C 0°C to 85°C 0°C to 85°C 0°C to 85°C 0°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C
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PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
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Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived PI7C8150BEVB Datasheet file may be downloaded here without warranties.

Datasheet ID: PI7C8150BEVB 510106