EPM9560RC240-15YY

EPM9560RC240-15YY Datasheet

EPM9320 EPM9320A

Part	Datasheet
EPM9560RC240-15YY	EPM9560RC240-15YY (pdf)

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June 2003, ver. MAX 9000 Includes MAX 9000A Programmable Logic Device Family Data Sheet Features... • High-performance CMOS EEPROM-based programmable logic devices PLDs built on third-generation Multiple Array MatriX architecture • 5.0-V in-system programmability ISP through built-in IEEE Std. Joint Test Action Group JTAG interface • Built-in JTAG boundary-scan test BST circuitry compliant with IEEE Std. • High-density erasable programmable logic device EPLD family ranging from 6,000 to 12,000 usable gates see Table 1 • 10-ns pin-to-pin logic delays with counter frequencies of up to 144 MHz • Dual-output macrocell for independent use of combinatorial and registered logic • Interconnect for fast, predictable interconnect delays • Input/output registers with clear and clock enable on all I/O pins • Programmable output slew-rate control to reduce switching noise • MultiVolt I/O interface operation, allowing devices to interface with 3.3-V and 5.0-V devices • Configurable expander product-term distribution allowing up to 32 product terms per macrocell • Programmable power-saving mode for more than 50% power reduction in each macrocell Table MAX 9000 Device Features Usable gates Flipflops Macrocells Logic array blocks LABs Maximum user I/O pins tPD1 ns tFSU ns tFCO ns fCNT MHz EPM9320 EPM9320A 6,000 484 320 20 168 10 144 Altera Corporation DS-M9000-6.5 EPM9400 8,000 580 400 25 159 15 5 7 118 EPM9480 10,000 676 480 30 175 10 144 EPM9560 EPM9560A 12,000 772 560 35 216 10 144 MAX 9000 Programmable Logic Device Family Data Sheet ...and More Features • Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls • Programmable security bit for protection of proprietary designs • Software design support and automatic place-and-route provided by Altera’s II development system on Windows-based PCs as well as Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000 workstations • Additional design entry and simulation support provided by EDIF 2 0 and 3 0 netlist files, library of parameterized modules LPM , Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest • Programming support with Altera’s Master Programming Unit MPU , BitBlasterTM serial download cable, ByteBlasterTM parallel port download cable, and ByteBlasterMVTM parallel port download cable, as well as programming hardware from third-party manufacturers • Offered in a variety of package options with 84 to 356 pins see Table 2 Table MAX 9000 Package Options & I/O Counts Note 1 Device EPM9320 EPM9320A EPM9400 EPM9480 EPM9560 EPM9560A 84-Pin PLCC 60 2 60 2 59 2 In-system programming can be accomplished with either an adaptive or constant algorithm. An adaptive algorithm reads information from the unit and adapts subsequent programming steps to achieve the fastest possible programming time for that unit. Because some in-circuit testers platforms have difficulties supporting an adaptive algorithm, Altera offers devices tested with a constant algorithm. Devices tested to the constant algorithm have an “F” suffix in the ordering code. Altera Corporation MAX 9000 Programmable Logic Device Family Data Sheet Programming Sequence During in-system programming, instructions, addresses, and data are shifted into the MAX 9000 device through the TDI input pin. Data is shifted out through the TDO output pin and compared against the expected data. Programming a pattern into the device requires the following six ISP stages. A stand-alone verification of a programmed pattern involves only stages 1, 2, 5, and Enter ISP. The enter ISP stage ensures that the I/O pins transition smoothly from user mode to ISP mode. The enter ISP stage requires 1 ms. Check ID. Before any program or verify process, the silicon ID is checked. The time required to read this silicon ID is relatively small compared to the overall programming time. Bulk Erase. Erasing the device in-system involves shifting in the instructions to erase the device and applying one erase pulse of 100 ms. Program. Programming the device in-system involves shifting in the address and data and then applying the programming pulse to program the EEPROM cells. This process is repeated for each EEPROM address. Verify. Verifying an Altera device in-system involves shifting in addresses, applying the read pulse to verify the EEPROM cells, and shifting out the data for comparison. This process is repeated for each EEPROM address. Exit ISP. An exit ISP stage ensures that the I/O pins transition smoothly from ISP mode to user mode. The exit ISP stage requires 1 ms. Programming Times The time required to implement each of the six programming stages can be broken into the following two elements: • A pulse time to erase, program, or read the EEPROM cells. • A shifting time based on the test clock TCK frequency and the number of TCK cycles to shift instructions, address, and data into the device. Altera Corporation MAX 9000 Programmable Logic Device Family Data Sheet By combining the pulse and shift times for each of the programming stages, the program or verify time can be derived as a function of the TCK frequency, the number of devices, and specific target device s . Because different ISP-capable devices have a different number of EEPROM cells, both the total fixed and total variable times are unique for a single device. Programming a Single MAX 9000 Device The time required to program a single MAX 9000 device in-system can be calculated from the following formula: tPR OG = tPP ULSE + where tPROG tPPULSE CyclePTCK fTCK = Programming time = Sum of the fixed times to erase, program, and verify the EEPROM cells = Number of TCK cycles to program a device = TCK frequency The ISP times for a stand-alone verification of a single MAX 9000 device can be calculated from the following formula: tVER = tVPULSE + where tVER = Verify time tVPULSE = Sum of the fixed times to verify the EEPROM cells CycleVTCK = Number of TCK cycles to verify a device Altera Corporation MAX 9000 Programmable Logic Device Family Data Sheet The programming times described in Tables 7 through 9 are associated with the worst-case method using the ISP algorithm. Table MAX 9000 tPULSE & CycleTCK Values Device Programming EPM9320 EPM9320A EPM9400 EPM9480 EPM9560 EPM9560A tPPULSE s

PDF Datasheet Preview

June 2003, ver.

MAX 9000

Includes

MAX 9000A

Programmable Logic

Device Family

Data Sheet

Features...
• High-performance CMOS EEPROM-based programmable logic devices PLDs built on third-generation Multiple Array MatriX architecture
• 5.0-V in-system programmability ISP through built-in IEEE Std. Joint Test Action Group JTAG interface
• Built-in JTAG boundary-scan test BST circuitry compliant with IEEE Std.
• High-density erasable programmable logic device EPLD family ranging from 6,000 to 12,000 usable gates see Table 1
• 10-ns pin-to-pin logic delays with counter frequencies of up to 144 MHz
• Dual-output macrocell for independent use of combinatorial and registered logic
• Interconnect for fast, predictable interconnect delays
• Input/output registers with clear and clock enable on all I/O pins
• Programmable output slew-rate control to reduce switching noise
• MultiVolt I/O interface operation, allowing devices to interface with
3.3-V and 5.0-V devices
• Configurable expander product-term distribution allowing up to 32
product terms per macrocell
• Programmable power-saving mode for more than 50% power
reduction in each macrocell

Table MAX 9000 Device Features

Usable gates Flipflops Macrocells Logic array blocks LABs Maximum user I/O pins tPD1 ns tFSU ns tFCO ns fCNT MHz

EPM9320 EPM9320A
6,000 484 320 20 168 10 144

Altera Corporation

DS-M9000-6.5

EPM9400
8,000 580 400 25 159 15
5 7 118

EPM9480
10,000 676 480 30 175 10 144

EPM9560 EPM9560A
12,000 772 560 35 216 10 144

MAX 9000 Programmable Logic Device Family Data Sheet
...and More Features
• Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls
• Programmable security bit for protection of proprietary designs
• Software design support and automatic place-and-route provided by

Altera’s II development system on Windows-based PCs as well as Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000 workstations
• Additional design entry and simulation support provided by EDIF 2 0 and 3 0 netlist files, library of parameterized modules LPM , Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest
• Programming support with Altera’s Master Programming Unit MPU , BitBlasterTM serial download cable, ByteBlasterTM parallel port download cable, and ByteBlasterMVTM parallel port download cable, as well as programming hardware from third-party manufacturers
• Offered in a variety of package options with 84 to 356 pins see Table 2

Table MAX 9000 Package Options & I/O Counts Note 1

Device

EPM9320 EPM9320A EPM9400 EPM9480 EPM9560 EPM9560A
84-Pin PLCC
60 2 60 2 59 2
In-system programming can be accomplished with either an adaptive or constant algorithm. An adaptive algorithm reads information from the unit and adapts subsequent programming steps to achieve the fastest possible programming time for that unit. Because some in-circuit testers platforms have difficulties supporting an adaptive algorithm, Altera offers devices tested with a constant algorithm. Devices tested to the constant algorithm have an “F” suffix in the ordering code.

Altera Corporation

MAX 9000 Programmable Logic Device Family Data Sheet

Programming Sequence

During in-system programming, instructions, addresses, and data are shifted into the MAX 9000 device through the TDI input pin. Data is shifted out through the TDO output pin and compared against the expected data.

Programming a pattern into the device requires the following six ISP stages. A stand-alone verification of a programmed pattern involves only stages 1, 2, 5, and

Enter ISP. The enter ISP stage ensures that the I/O pins transition smoothly from user mode to ISP mode. The enter ISP stage requires 1 ms.

Check ID. Before any program or verify process, the silicon ID is checked. The time required to read this silicon ID is relatively small compared to the overall programming time.

Bulk Erase. Erasing the device in-system involves shifting in the instructions to erase the device and applying one erase pulse of 100 ms.

Program. Programming the device in-system involves shifting in the address and data and then applying the programming pulse to program the EEPROM cells. This process is repeated for each EEPROM address.

Verify. Verifying an Altera device in-system involves shifting in addresses, applying the read pulse to verify the EEPROM cells, and shifting out the data for comparison. This process is repeated for each EEPROM address.

Exit ISP. An exit ISP stage ensures that the I/O pins transition smoothly from ISP mode to user mode. The exit ISP stage requires 1 ms.

Programming Times

The time required to implement each of the six programming stages can be broken into the following two elements:
• A pulse time to erase, program, or read the EEPROM cells.
• A shifting time based on the test clock TCK frequency and the
number of TCK cycles to shift instructions, address, and data into the device.

Altera Corporation

MAX 9000 Programmable Logic Device Family Data Sheet

By combining the pulse and shift times for each of the programming stages, the program or verify time can be derived as a function of the TCK frequency, the number of devices, and specific target device s . Because different ISP-capable devices have a different number of EEPROM cells, both the total fixed and total variable times are unique for a single device.

Programming a Single MAX 9000 Device

The time required to program a single MAX 9000 device in-system can be calculated from the following formula:
tPR OG = tPP ULSE +
where tPROG tPPULSE

CyclePTCK fTCK
= Programming time = Sum of the fixed times to erase, program, and
verify the EEPROM cells = Number of TCK cycles to program a device = TCK frequency

The ISP times for a stand-alone verification of a single MAX 9000 device can be calculated from the following formula:
tVER = tVPULSE +
where tVER
= Verify time
tVPULSE = Sum of the fixed times to verify the EEPROM cells

CycleVTCK = Number of TCK cycles to verify a device

Altera Corporation

MAX 9000 Programmable Logic Device Family Data Sheet

The programming times described in Tables 7 through 9 are associated with the worst-case method using the ISP algorithm.

Table MAX 9000 tPULSE & CycleTCK Values

Device

Programming

EPM9320 EPM9320A

EPM9400 EPM9480 EPM9560 EPM9560A
tPPULSE s

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Datasheet ID: EPM9560RC240-15YY 517149