CY7C60223-PXC

CY7C60223-PXC Datasheet

CY7C601xx, CY7C602xx

Part	Datasheet
CY7C60223-PXC	CY7C60223-PXC (pdf)

Related Parts	Information
CY7C60113-PVXC	CY7C60113-PVXC

PDF Datasheet Preview
CY7C601xx, CY7C602xx enCoRe II Low Voltage Microcontroller • enCoRe II Low Voltage enCoRe II Component Reduction Internal crystalless oscillator with support for optional external clock or external crystal or resonator Configurable I/O for real world interface without external components • Enhanced 8-bit Microcontroller Harvard architecture M8C CPU speed up to 12 MHz or sourced by an external crystal, resonator, or clock signal • Internal Memory 256 bytes of RAM 8 Kbytes of Flash including EEROM emulation • Low Power Consumption Typically mA at 3 MHz 5 uA sleep • In-system Reprogrammability Enables easy firmware update • General Purpose I/O Ports Up to 36 GPIO pins 2 mA source current on all GPIO pins. Configurable 8 or 50 mA per pin current sink on designated pins Each GPIO port supports high impedance inputs, configurable pull up, open drain output, CMOS and TTL inputs, and CMOS output Maskable interrupts on all I/O pins • SPI Serial Communication Master or slave operation Configurable up to 2 Mbit per second transfers Supports half duplex single data line mode for optical sensors • 2-channel 8-bit or 1-channel 16-bit Capture Timer Registers, which store both Rising and Falling Edge Times Two registers each for two input pins Separate registers for rising and falling edge capture Simplifies interface to RF inputs for wireless applications • Internal Low Power Wakeup Timer during Suspend Mode Periodic wakeup with no external components • Programmable Interval Timer Interrupts • Reduced RF Emissions at 27 MHz and 96 MHz • Watchdog Timer WDT • Low Voltage Detection with User Selectable Threshold Voltages • Improved Output Drivers to reduce EMI • Operating Voltage from 2.7V to 3.6V DC • Operating Temperature from 0 to 70°C • Available in 24 and 40-Pin PDIP, 24-Pin SOIC, 24-Pin QSOP and SSOP, 28-Pin SSOP, and 48-Pin SSOP • Advanced Development Tools based on Cypress Tools • Industry Standard Programmer Support Logic Block Diagram Interrupt Control 4 SPI/GPIO 16 Extended Pins I/O Pins 16 GPIO Pins Wakeup Timer Internal 12 MHz Oscillator Clock Control Crystal Oscillator CY7C601xx only POR / Low-Voltage Detect M8C CPU Watchdog Timer RAM 256 Byte Flash 8K Byte 12-bit Timer Capture Timers [+] Feedback CY7C601xx, CY7C602xx Ordering Information Ordering Code CY7C60123-PVXC CY7C60123-PXC CY7C60113-PVXC CY7C60223-PXC CY7C60223-SXC CY7C60223-QXC Flash Size 8K RAM Size 256 48-SSOP 40-PDIP 28-SSOP 24-PDIP 24-SOIC 24-QSOP Package Type Package Handling Some IC packages require baking before they are soldered onto a PCB to remove moisture that may have been absorbed after leaving the factory. A label on the packaging has details about actual bake temperature and the minimum bake time to remove this moisture. The maximum bake time is the aggregate time that the parts are exposed to the bake temperature. Exceeding this exposure time may degrade device reliability. Parameter TBAKETEMP TBAKETIME Description Bake Temperature Bake Time Min See package label Typical 125 Max See package label Unit °C hours Page 63 of 68 [+] Feedback CY7C601xx, CY7C602xx Package Diagrams Figure 24-Pin 300-Mil SOIC S13 PIN 1 ID NOTE JEDEC STD REF MO-119 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH,BUT DOES INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE MOLD PARTING LINE. MOLD PROTRUSION/END FLASH SHALL NOT EXCEED in mm PER SIDE DIMENSIONS IN INCHES PACKAGE WEIGHT 0.65gms MIN. MAX. PART # S24.3 STANDARD PKG. SZ24.3 LEAD FREE PKG. SEATING PLANE TYP. 51-85025 C Figure 24-Pin 300-Mil PDIP P13 51-85013-B Page 64 of 68 [+] Feedback CY7C601xx, CY7C602xx REF. Figure 24-Pin QSOP O241 PIN 1 ID DIMENSIONS IN INCHES MIN. MAX. SEATING PLANE BSC. Figure 28-Pin mm Shrunk Small Outline Package O28 0° -8° Updated Power consumption values Corrected Pin Assignment Table for 24 QSOP, 24 PDIP and 28 SSOP packages Minor text changes for clarification purposes Corrected INT_MSK0 and INT_MSK1 register address Corrected register bit definitions Corrected Protection Mode Settings in Table 10-7 Updated LVD Trip Point values Added Block diagrams for Timer functional timing Replaced TBD’s with actual values Added SPI Block Diagram Added Timing Block Diagrams Removed CY7C60123 DIE from Figure 5-1 Removed CY7C60123-WXC from Section Ordering Information Updated internal 24 MHz oscillator accuracy information Added information on sending/receiving data when using 32 KHz oscillator B 505222 See ECN Minor text changes GPIO capacitance and timing diagram included Method to clear Capture Interrupt Status bit discussed Sleep and Wakeup sequence documented PIT Timer registers’ R/W capability corrected to read only Modified Free Running Counter text in section C 524104 KKVTMP See ECN Change title from Wireless enCoRe II to enCoRe II Low Voltage D 1821746 VGT/FSU/AES See ECN Changed “High current drive” on GPIO pins to “2 mA source current on all GPIO pins”. Changed the storage temperature from -40C to 90C in “Absolute Maximum ratings” section. Added the line “The GPIOs interrupts are edge-triggered.” in Tables 19-2 and Made timing changes in Table Added Figure 12-1 SROM Table and text after it. Also modified Table 12-1 based on Figure 12-1 SROM Table . Changed “CAPx” to “TIOx” in Tables 18-8 and Changed “Capturex” to “TIOx” in Figure E 2620679 CMCC/PYRS 12/12/08 Added Package Handling information Formatted code in Clocking section, Removed reference to external crystal oscillator in Tables 12-2 and 12-4 *F 2761532 DVJA 09/09/2009 Changed default value of the Sleep Timer from 00 512 Hz to 01 64 Hz in the OSC_CR0 [0x1E0] register. Page 67 of 68 [+] Feedback CY7C601xx, CY7C602xx Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Page 68 of 68 PSoC is a registered trademark and enCoRe is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback

PDF Datasheet Preview

CY7C601xx, CY7C602xx
enCoRe II Low Voltage Microcontroller
• enCoRe II Low Voltage enCoRe II Component Reduction Internal crystalless oscillator with support for optional external clock or external crystal or resonator Configurable I/O for real world interface without external components
• Enhanced 8-bit Microcontroller Harvard architecture M8C CPU speed up to 12 MHz or sourced by an external crystal, resonator, or clock signal
• Internal Memory 256 bytes of RAM 8 Kbytes of Flash including EEROM emulation
• Low Power Consumption Typically mA at 3 MHz 5 uA sleep
• In-system Reprogrammability Enables easy firmware update
• General Purpose I/O Ports Up to 36 GPIO pins 2 mA source current on all GPIO pins. Configurable 8 or 50 mA per pin current sink on designated pins Each GPIO port supports high impedance inputs, configurable pull up, open drain output, CMOS and TTL inputs, and CMOS output Maskable interrupts on all I/O pins
• SPI Serial Communication Master or slave operation Configurable up to 2 Mbit per second transfers Supports half duplex single data line mode for optical sensors
• 2-channel 8-bit or 1-channel 16-bit Capture Timer Registers, which store both Rising and Falling Edge Times Two registers each for two input pins Separate registers for rising and falling edge capture Simplifies interface to RF inputs for wireless applications
• Internal Low Power Wakeup Timer during Suspend Mode Periodic wakeup with no external components
• Programmable Interval Timer Interrupts
• Reduced RF Emissions at 27 MHz and 96 MHz
• Watchdog Timer WDT
• Low Voltage Detection with User Selectable Threshold Voltages
• Improved Output Drivers to reduce EMI
• Operating Voltage from 2.7V to 3.6V DC
• Operating Temperature from 0 to 70°C
• Available in 24 and 40-Pin PDIP, 24-Pin SOIC, 24-Pin QSOP and SSOP, 28-Pin SSOP, and 48-Pin SSOP
• Advanced Development Tools based on Cypress Tools
• Industry Standard Programmer Support

Logic Block Diagram

Interrupt Control
4 SPI/GPIO 16 Extended

Pins

I/O Pins
16 GPIO Pins

Wakeup Timer

Internal 12 MHz Oscillator

Clock Control

Crystal Oscillator CY7C601xx only

POR / Low-Voltage

Detect

M8C CPU

Watchdog Timer

RAM 256 Byte

Flash 8K Byte
12-bit Timer

Capture Timers
[+] Feedback

CY7C601xx, CY7C602xx
Ordering Information
Ordering Code CY7C60123-PVXC CY7C60123-PXC CY7C60113-PVXC CY7C60223-PXC CY7C60223-SXC CY7C60223-QXC

Flash Size 8K

RAM Size 256
48-SSOP 40-PDIP 28-SSOP 24-PDIP 24-SOIC 24-QSOP

Package Type

Package Handling

Some IC packages require baking before they are soldered onto a PCB to remove moisture that may have been absorbed after leaving the factory. A label on the packaging has details about actual bake temperature and the minimum bake time to remove this moisture. The maximum bake time is the aggregate time that the parts are exposed to the bake temperature. Exceeding this exposure time may degrade device reliability.

Parameter TBAKETEMP TBAKETIME

Description Bake Temperature Bake Time

Min See package label

Typical 125

Max See package label

Unit °C hours

Page 63 of 68
[+] Feedback

CY7C601xx, CY7C602xx

Package Diagrams

Figure 24-Pin 300-Mil SOIC S13

PIN 1 ID

NOTE JEDEC STD REF MO-119 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH,BUT

DOES INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE MOLD PARTING LINE. MOLD PROTRUSION/END FLASH SHALL NOT EXCEED in mm PER SIDE

DIMENSIONS IN INCHES

PACKAGE WEIGHT 0.65gms

MIN. MAX.

PART # S24.3 STANDARD PKG. SZ24.3 LEAD FREE PKG.

SEATING PLANE

TYP.
51-85025 *C

Figure 24-Pin 300-Mil PDIP P13
51-85013-*B

Page 64 of 68
[+] Feedback

CY7C601xx, CY7C602xx

REF.

Figure 24-Pin QSOP O241

PIN 1 ID

DIMENSIONS IN INCHES MIN. MAX.

SEATING PLANE

BSC.

Figure 28-Pin mm Shrunk Small Outline Package O28
0° -8°
Updated Power consumption values Corrected Pin Assignment Table for 24 QSOP, 24 PDIP and 28 SSOP packages Minor text changes for clarification purposes Corrected INT_MSK0 and INT_MSK1 register address Corrected register bit definitions Corrected Protection Mode Settings in Table 10-7 Updated LVD Trip Point values Added Block diagrams for Timer functional timing Replaced TBD’s with actual values Added SPI Block Diagram Added Timing Block Diagrams Removed CY7C60123 DIE from Figure 5-1 Removed CY7C60123-WXC from Section Ordering Information Updated internal 24 MHz oscillator accuracy information Added information on sending/receiving data when using 32 KHz oscillator
*B 505222

See ECN

Minor text changes

GPIO capacitance and timing diagram included Method to clear Capture Interrupt Status bit discussed Sleep and Wakeup sequence documented PIT Timer registers’ R/W capability corrected to read only

Modified Free Running Counter text in section
*C 524104 KKVTMP

See ECN Change title from Wireless enCoRe II to enCoRe II Low Voltage
*D 1821746 VGT/FSU/AES See ECN Changed “High current drive” on GPIO pins to “2 mA source current on all GPIO
pins”.

Changed the storage temperature from -40C to 90C in “Absolute Maximum
ratings” section.

Added the line “The GPIOs interrupts are edge-triggered.” in Tables 19-2 and

Made timing changes in Table

Added Figure 12-1 SROM Table and text after it. Also modified Table 12-1
based on Figure 12-1 SROM Table .

Changed “CAPx” to “TIOx” in Tables 18-8 and

Changed “Capturex” to “TIOx” in Figure
*E 2620679 CMCC/PYRS 12/12/08 Added Package Handling information Formatted code in Clocking section, Removed reference to external crystal oscillator in Tables 12-2 and 12-4
*F 2761532

DVJA
09/09/2009 Changed default value of the Sleep Timer from 00 512 Hz to 01 64 Hz in the OSC_CR0 [0x1E0] register.

Page 67 of 68
[+] Feedback

CY7C601xx, CY7C602xx

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.

Products PSoC Clocks & Buffers Wireless Memories Image Sensors
psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Page 68 of 68

PSoC is a registered trademark and enCoRe is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders.
[+] Feedback

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Datasheet ID: CY7C60223-PXC 508117