PI7C8150ANDE-2017

PI7C8150ANDE-2017 Datasheet

PI7C8150A

Part	Datasheet
PI7C8150ANDE-2017	PI7C8150ANDE-2017 (pdf)

PDF Datasheet Preview
PI7C8150A 2-PORT PCI-to-PCI BRIDGE 06-0057 3545 North 1st Street, San Jose, CA 95134 Telephone 1-877-PERICOM, 1-877-737-4266 Fax 408-435-1100 Internet: PI7C8150A 2-PORT PCI-TO-PCI BRIDGE LIFE SUPPORT POLICY Pericom Semiconductor Corporation’s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of PSC. 1 Life support devices or system are devices or systems which a Are intended for surgical implant into the body or b Support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Pericom Semiconductor Corporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom Semiconductor does not assume any responsibility for use of any circuitry described other than the circuitry embodied in a Pericom Semiconductor product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Pericom Semiconductor Corporation. All other trademarks are of their respective companies. 06-0057 Page 2 of 111 PI7C8150A 2-PORT PCI-TO-PCI BRIDGE 10/15/03 05/20/05 Description First Release of Data Sheet Corrected VDD and VSS pin assignments in Section Removed pins 106 and 155 R16 and B14 as these should be MS1 and MS0 respectively. 04/20/06 Added Pb-free parts in the Ordering Information Removed ‘Advance Information’ from header Removed email link Changed logos 06-0057 Page 3 of 111 This page intentionally left blank. PI7C8150A 2-PORT PCI-TO-PCI BRIDGE 06-0057 Page 4 of 111 PI7C8150A 2-PORT PCI-TO-PCI BRIDGE TABLE OF CONTENTS 2 SIGNAL 12 SIGNAL 12 SIGNALS 12 PRIMARY BUS INTERFACE SIGNALS 12 CLOCK SIGNALS 15 MISCELLANEOUS 16 GENERAL PURPOSE I/O INTERFACE SIGNALS 17 JTAG BOUNDARY SCAN SIGNALS 17 POWER AND 17 PIN LIST 208-PIN FQFP 18 PIN LIST 256-BALL PBGA 20 3 PCI BUS 21 TYPES OF 22 SINGLE ADDRESS PHASE 22 DEVICE SELECT DEVSEL_L GENERATION 23 DATA PHASE 23 WRITE TRANSACTIONS 23 MEMORY WRITE 23 MEMORY WRITE AND INVALIDATE 24 DELAYED WRITE 25 WRITE TRANSACTION ADDRESS 26 BUFFERING MULTIPLE WRITE 26 FAST BACK-TO-BACK TRANSACTIONS 26 READ 27 PREFETCHABLE READ 27 NON-PREFETCHABLE READ 27 READ PREFETCH ADDRESS BOUNDARIES 28 DELAYED READ REQUESTS 28 DELAYED READ COMPLETION WITH TARGET 29 DELAYED READ COMPLETION ON INITIATOR 29 FAST BACK-TO-BACK READ TRANSACTION 30 CONFIGURATION TRANSACTIONS 30 TYPE 0 ACCESS TO 31 TYPE 1 TO TYPE 0 CONVERSION 31 TYPE 1 TO TYPE 1 33 SPECIAL CYCLES 34 TRANSACTION TERMINATION 34 MASTER TERMINATION INITIATED BY PI7C8150A 35 MASTER ABORT RECEIVED BY PI7C8150A 36 TARGET TERMINATION RECEIVED BY 36 DELAYED WRITE TARGET TERMINATION 37 POSTED WRITE TARGET TERMINATION RESPONSE 37 DELAYED READ TARGET TERMINATION RESPONSE 38 TARGET TERMINATION INITIATED BY 39 TARGET RETRY 39 06-0057 Page 5 of 111 PI7C8150A 2-PORT PCI-TO-PCI BRIDGE TARGET DISCONNECT 40 TARGET ABORT 40 4 ADDRESS 41 ADDRESS RANGES 41 I/O ADDRESS 41 I/O BASE AND LIMIT ADDRESS 42 ISA 43 MEMORY ADDRESS DECODING 43 MEMORY-MAPPED I/O BASE AND LIMIT ADDRESS REGISTERS 44 PREFETCHABLE MEMORY BASE AND LIMIT ADDRESS REGISTERS 45 VGA 46 VGA 46 VGA SNOOP 46 5 TRANSACTION ORDERING 47 TRANSACTIONS GOVERNED BY ORDERING RULES 47 GENERAL ORDERING GUIDELINES 48 ORDERING 48 DATA SYNCHRONIZATION 51 6 ERROR HANDLING 52 ADDRESS PARITY ERRORS 52 DATA PARITY ERRORS 53 CONFIGURATION WRITE TRANSACTIONS TO CONFIGURATION SPACE.......... 53 READ TRANSACTIONS 53 DELAYED WRITE 54 POSTED WRITE 57 DATA PARITY ERROR REPORTING 58 SYSTEM ERROR SERR_L 62 7 EXCLUSIVE ACCESS 63 CONCURRENT LOCKS 63 ACQUIRING EXCLUSIVE ACCESS ACROSS PI7C8150A 63 LOCKED TRANSACTIONS IN DOWNSTREAM DIRECTION 63 LOCKED TRANSACTION IN UPSTREAM DIRECTION 65 ENDING EXCLUSIVE 65 8 PCI BUS ARBITRATION 66 PRIMARY PCI BUS ARBITRATION 66 SECONDARY PCI BUS 66 SECONDARY BUS ARBITRATION USING THE INTERNAL ARBITER.................... 66 PREEMPTION 68 SECONDARY BUS ARBITRATION USING AN EXTERNAL ARBITER...................... 68 BUS 68 PRIMARY CLOCK 69 SECONDARY CLOCK OUTPUTS 69 10 GENERAL PURPOSE I/O 69 06-0057 Page 6 of 111 PI7C8150A 2-PORT PCI-TO-PCI BRIDGE GPIO CONTROL 70 SECONDARY CLOCK 70 LIVE INSERTION 72 11 PCI POWER MANAGEMENT 72 12 RESET 73 PRIMARY INTERFACE RESET 73 SECONDARY INTERFACE 74 CHIP 74 13 SUPPORTED 74 PRIMARY INTERFACE 74 SECONDARY 76 14 CONFIGURATION 77 06-0057 Page 7 of 111 PI7C8150A 2-PORT PCI-TO-PCI BRIDGE SECONDARY BUS ARBITER PREEMPTION CONTROL REGISTER OFFSET 89 UPSTREAM S TO P MEMORY BASE REGISTER OFFSET 50h 89 UPSTREAM S TO P MEMORY LIMIT REGISTER OFFSET 50h....................... 90 UPSTREAM S TO P MEMORY BASE UPPER 32-BITS REGISTER OFFSET 54h 90 UPSTREAM S TO P MEMORY LIMIT UPPER 32-BITS REGISTER OFFSET 90 P_SERR_L EVENT DISABLE REGISTER OFFSET 90 GPIO DATA AND CONTROL REGISTER OFFSET 64h 91 SECONDARY CLOCK CONTROL REGISTER OFFSET 68h 92 P_SERR_L STATUS REGISTER OFFSET 68h 92 PORT OPTION REGISTER OFFSET 74h 93 RETRY COUNTER REGISTER OFFSET 78h 95 PRIMARY MASTER TIMEOUT COUNTER OFFSET 80h 95 SECONDARY MASTER TIMEOUT COUNTER OFFSET 80h 95 CAPABILITY ID REGISTER OFFSET B0h 95 NEXT POINTER REGISTER OFFSET B0h 95 SLOT NUMBER REGISTER OFFSET B0h 96 CHASSIS NUMBER REGISTER OFFSET B0h 96 CAPABILITY ID REGISTER OFFSET 96 NEXT ITEM POINTER REGISTER OFFSET DCh 96 POWER MANAGEMENT CAPABILITIES REGISTER OFFSET DCh 96 POWER MANAGEMENT DATA REGISTER OFFSET E0h................................... 97 CAPABILITY ID REGISTER OFFSET E4h 97 NEXT POINTER REGISTER OFFSET E4h 97 15 BRIDGE BEHAVIOR 97 BRIDGE ACTIONS FOR VARIOUS CYCLE 98 ABNORMAL TERMINATION INITIATED BY BRIDGE MASTER ................................ 98 MASTER 98 PARITY AND ERROR REPORTING 98 REPORTING PARITY ERRORS 99 SECONDARY IDSEL MAPPING 99 16 IEEE COMPATIBLE JTAG CONTROLLER 99 BOUNDARY SCAN 99 TAP PINS 100 INSTRUCTION REGISTER 100 BOUNDARY SCAN INSTRUCTION SET 101 TAP TEST DATA 102 BYPASS REGISTER 102 BOUNDARY-SCAN 102 TAP CONTROLLER 102 17 ELECTRICAL AND TIMING 106 MAXIMUM RATINGS 106 DC SPECIFICATIONS 106 AC 107 66MHZ 108 33MHZ 108 POWER CONSUMPTION 108 06-0057 Page 8 of 111 PI7C8150A 2-PORT PCI-TO-PCI BRIDGE 18 PACKAGE 109 208-PIN FQFP PACKAGE DIAGRAM 109 256-BALL PBGA PACKAGE DIAGRAM 110 PART NUMBER ORDERING 110 LIST OF TABLES TABLE PIN LIST 208-PIN FQFP 18 TABLE PIN LIST 256-PIN PBGA 20 TABLE PCI TRANSACTIONS 22 TABLE WRITE TRANSACTION 23 TABLE WRITE TRANSACTION DISCONNECT ADDRESS BOUNDARIES 26 TABLE READ PREFETCH ADDRESS BOUNDARIES 28 TABLE READ TRANSACTION PREFETCHING 28 TABLE DEVICE NUMBER TO IDSEL S_AD PIN 32 TABLE DELAYED WRITE TARGET TERMINATION 37 TABLE RESPONSE TO POSTED WRITE TARGET 38 TABLE RESPONSE TO DELAYED READ TARGET TERMINATION 38 TABLE SUMMARY OF TRANSACTION ORDERING 50 TABLE SETTING THE PRIMARY INTERFACE DETECTED PARITY ERROR BIT 58 TABLE SETTING SECONDARY INTERFACE DETECTED PARITY ERROR BIT 59 TABLE SETTING PRIMARY INTERFACE MASTER DATA PARITY ERROR DETECTED BIT......................... 59 TABLE SETTING SECONDARY INTERFACE MASTER DATA PARITY ERROR DETECTED BIT 60 TABLE ASSERTION OF 60 TABLE ASSERTION OF 61 TABLE ASSERTION OF P_SERR_L FOR DATA PARITY ERRORS 61 TABLE GPIO OPERATION 71 TABLE GPIO SERIAL DATA 71 TABLE POWER MANAGEMENT TRANSITIONS 73 TABLE TAP PINS 101 TABLE JTAG BOUNDARY REGISTER ORDER 103 LIST OF FIGURES FIGURE 8-1 SECONDARY ARBITER 67 FIGURE 16-1 TEST ACCESS PORT BLOCK DIAGRAM 100 FIGURE 17-1 PCI SIGNAL TIMING MEASUREMENT CONDITIONS 107 FIGURE 18-1 208-PIN FQFP PACKAGE 109 FIGURE 18-2 256-PIN PBGA PACKAGE 110 06-0057 Page 9 of 111 This page intentionally left blank. PI7C8150A 2-PORT PCI-TO-PCI BRIDGE 06-0057 Page 10 of 111 PI7C8150A 2-PORT PCI-TO-PCI BRIDGE INTRODUCTION Product Description Product Features 06-0057 Page 11 of 111 PI7C8150A 2-PORT PCI-TO-PCI BRIDGE SIGNAL DEFINITIONS Signal Types Signal Type I O P TS STS Description Input Only Output Only Power Tri-State bi-directional Sustained Tri-State. Active LOW signal must be pulled HIGH for 1 cycle when deasserting. Open Drain Signals Note Signal names that end with “_L” are active LOW. PRIMARY BUS INTERFACE SIGNALS Name P_AD[31:0] P_CBE[3:0] P_PAR Pin # 49, 50, 55, 57, 58, 60, 61, 63, 67, 68, 70, 71, 73, 74, 76, 77, 93, 95, 96, 98, 99, 101, 107, 109, 112, 113, 115, 116, 118, 119, 121, 122 64, 79, 92, 110 Pin # N3, T2, T4, N5, P5, T5, N6, R5, T6, P7, T7, R7, T8, P8, R8, T9, R12, P12, T14, R13, N12, T15, P16, N15, M14, M13, M15, L13, M16, L14, L15, L16 R6, R9, T13, N16 Type TS Description Primary Address / Data Multiplexed address and data bus. Address is indicated by P_FRAME_L assertion. Write data is stable and valid when P_IRDY_L is asserted and read data is stable and valid when P_TRDY_L is asserted. Data is transferred on rising clock edges when both P_IRDY_L and P_TRDY_L are asserted. During bus idle, PI7C8150A drives P_AD to a valid logic level when P_GNT_L is asserted. TS Primary Command/Byte Enables Multiplexed command field and byte enable field. During address phase, the initiator drives the transaction type on these pins. After that, the initiator drives the byte enables during data phases. During bus idle, PI7C8150A drives P_CBE[3:0] to a valid logic level when P_GNT_L is asserted. TS Primary Parity. Parity is even across P_AD[31:0], P_CBE[3:0], and P_PAR i.e. an even number of 1’s . P_PAR is an input and is valid and stable one cycle after the address phase indicated by assertion of P_FRAME_L for address parity. For write data phases, P_PAR is an input and is valid one clock after P_IRDY_L is asserted. For read data phase, P_PAR is an output and is valid one clock after P_TRDY_L is asserted. Signal P_PAR is tri-stated one cycle after the P_AD lines are tri-stated. During bus idle, PI7C8150A drives P_PAR to a valid logic level when P_GNT_L is asserted. 06-0057 Page 12 of 111 06-0057 Name P_FRAME_L Pin # 80 P_IRDY_L P_TRDY_L P_DEVSEL_L P_STOP_L When a write transaction is first detected on the initiator bus, and PI7C8150A forwards it as a delayed transaction, PI7C8150A claims the access by asserting DEVSEL_L and returns a target retry to the initiator. During the address phase, PI7C8150A samples the bus command, address, and address parity one cycle later. After IRDY_L is asserted, PI7C8150A also samples the first data DWORD, byte enable bits, and data parity. This information is placed into the delayed transaction queue. The transaction is queued only if no other existing delayed transactions have the same address and command, and if the delayed transaction queue is not full. When the delayed write transaction moves to the head of the delayed transaction queue and all ordering constraints with posted data are satisfied. The PI7C8150A initiates the transaction on the target bus. PI7C8150A transfers the write data to the target. If PI7C8150A receives a target retry in response to the write transaction on the target bus, it continues to repeat the write transaction until the data transfer is completed, or until an error condition is encountered. If PI7C8150A is unable to deliver write data after 224 default or 232 maximum attempts, PI7C8150A will report a system error. PI7C8150A also asserts P_SERR_L if the primary SERR_L enable bit is set in the command register. See Section for information on the assertion of P_SERR_L. When the initiator repeats the same write transaction same command, address, byte enable bits, and data , and the completed delayed transaction is at the head of the queue, the PI7C8150A claims the access by asserting DEVSEL_L and returns TRDY_L to the initiator, to indicate that the write data was transferred. If the initiator requests multiple DWORD, PI7C8150A also asserts STOP_L in conjunction with TRDY_L to signal a target disconnect. Note that only those bytes of write data with valid byte enable bits are compared. If any of the byte enable bits are turned off driven HIGH , the corresponding byte of write data is not compared. If the initiator repeats the write transaction before the data has been transferred to the target, PI7C8150A returns a target retry to the initiator. PI7C8150A continues to return a target retry to the initiator until write data is delivered to the target, or until an error condition is encountered. When the write transaction is repeated, PI7C8150A does not make a new entry into the delayed transaction queue. Section provides detailed information about how PI7C8150A responds to target termination during delayed write transactions. 06-0057 Page 25 of 111 PI7C8150A 2-PORT PCI-TO-PCI BRIDGE PI7C8150A implements a discard timer that starts counting when the delayed write completion is at the head of the delayed transaction completion queue. The initial value of this timer can be set to the retry counter register offset 78h. If the initiator does not repeat the delayed write transaction before the discard timer expires, PI7C8150A discards the delayed write completion from the delayed transaction completion queue. PI7C8150A also conditionally asserts P_SERR_L see Section WRITE TRANSACTION ADDRESS BOUNDARIES PI7C8150A imposes internal address boundaries when accepting write data. The aligned address boundaries are used to prevent PI7C8150A from continuing a transaction over a device address boundary and to provide an upper limit on maximum latency. PI7C78150A returns a target disconnect to the initiator when it reaches the aligned address boundaries under conditions shown in Table Table Write Transaction Disconnect Address Boundaries Type of Transaction Condition Aligned Address Boundary Delayed Write Disconnects after one data transfer Posted Memory Write Memory write disconnect control 4KB aligned address boundary bit = 0 1 Posted Memory Write Memory write disconnect control Disconnects at cache line boundary bit = 1 Posted Memory Write and Cache line size 1, 2, 4, 8, 16 4KB aligned address boundary Invalidate Posted Memory Write and Cache line size = 1, 2, 4, 8, 16 Cache line boundary if posted memory Invalidate write data FIFO does not have enough space for the cache line Note Memory write disconnect control bit is bit 1 of the chip control register at offset 40h in the configuration space. BUFFERING MULTIPLE WRITE TRANSACTIONS PI7C8150A continues to accept posted memory write transactions as long as space for at least one DWORD of data in the posted write data buffer remains. If the posted write data buffer fills before the initiator terminates the write transaction, PI7C8150A returns a target disconnect to the initiator. Delayed write transactions are posted as long as at least one open entry in the delayed transaction queue exists. Therefore, several posted and delayed write transactions can exist in data buffers at the same time. See Chapter 6 for information about how multiple posted and delayed write transactions are ordered. FAST BACK-TO-BACK TRANSACTIONS PI7C8150A can recognize and post fast back-to-back write transactions. When PI7C8150A cannot accept the second transaction because of buffer space limitations, it returns a target retry to the initiator. The fast back-to-back enable bit must be set in the command register for upstream write transactions, and in the bridge control register for downstream write transactions. 06-0057 Page 26 of 111 PI7C8150A 2-PORT PCI-TO-PCI BRIDGE READ TRANSACTIONS Delayed read forwarding is used for all read transactions crossing PI7C8150A. Delayed read transactions are treated as either prefetchable or non-prefetchable. Table 3-5 shows the read behavior, prefetchable or non-prefetchable, for each type of read operation. PREFETCHABLE READ TRANSACTIONS When the transaction has been completed on the target bus, and the delayed read data is at the head of the read data queue, and all ordering constraints with posted write transactions have been satisfied, the PI7C8150A transfers the data to the initiator when the initiator repeats the transaction. For memory read transactions, PI7C8150A aliases the memory read, memory read line, and memory read multiple bus commands when matching the bus command of the transaction to the bus command in the delayed transaction queue. PI7C8150A returns a target disconnect along with the transfer of the last DWORD of read data to the initiator. If PI7C8150A initiator terminates the transaction before all read data has been transferred, the remaining read data left in data buffers is discarded. 06-0057 Page 29 of 111 PI7C8150A 2-PORT PCI-TO-PCI BRIDGE When the master repeats the transaction and starts transferring prefetchable read data from data buffers while the read transaction on the target bus is still in progress and before a read boundary is reached on the target bus, the read transaction starts operating in flow-through mode. Because data is flowing through the data buffers from the target to the initiator, long read bursts can then be sustained. In this case, the read transaction is allowed to continue until the initiator terminates the transaction, or until an aligned 4KB address boundary is reached, or until the buffer fills, whichever comes first. When the buffer empties, PI7C8150A reflects the stalled condition to the initiator by disconnecting the initiator with data. The initiator may retry the transaction later if data are needed. If the initiator does not need any more data, the initiator will not continue the disconnected transaction. In this case, PI7C8150A will start the master timeout timer. The remaining read data will be discarded after the master timeout timer expires. To provide better latency, if there are any other pending data for other transactions in the RDB Read Data Buffer , the remaining read data will be discarded even though the master timeout timer has not expired. PI7C8150A implements a master timeout timer that starts counting when the delayed read completion is at the head of the delayed transaction queue, and the read data is at the head of the read data queue. The initial value of this timer is programmable through configuration register. If the initiator does not repeat the read transaction and before the master timeout timer expires 215 default , PI7C8150A discards the read transaction and read data from its queues. PI7C8150A also conditionally asserts P_SERR_L see Section PI7C8150A has the capability to post multiple delayed read requests, up to a maximum of four in each direction. If an initiator starts a read transaction that matches the address and read command of a read transaction that is already queued, the current read command is not posted as it is already contained in the delayed transaction queue. See Section 5 for a discussion of how delayed read transactions are ordered when crossing PI7C8150A. FAST BACK-TO-BACK READ TRANSACTION PI7C8150A can recognize fast back-to-back read transactions. CONFIGURATION TRANSACTIONS Configuration transactions are used to initialize a PCI system. Every PCI device has a configuration space that is accessed by configuration commands. All registers are accessible in configuration space only. In addition to accepting configuration transactions for initialization of its own configuration space, the PI7C8150A also forwards configuration transactions for device initialization in hierarchical PCI systems, as well as for special cycle generation. To support hierarchical PCI bus systems, two types of configuration transactions are specified Type 0 and Type 06-0057 Page 30 of 111 PI7C8150A 2-PORT PCI-TO-PCI BRIDGE 06-0057 Type 0 configuration transactions are issued when the intended target resides on the same PCI bus as the initiator. A Type 0 configuration transaction is identified by the configuration command and the lowest two bits of the address set to 00b. Type 1 configuration transactions are issued when the intended target resides on another PCI bus, or when a special cycle is to be generated on another PCI bus. A Type 1 configuration command is identified by the configuration command and the lowest two address bits set to 01b. The register number is found in both Type 0 and Type 1 formats and gives the DWORD address of the configuration register to be accessed. The function number is also included in both Type 0 and Type 1 formats and indicates which function of a multifunction device is to be accessed. For single-function devices, this value is not decoded. The addresses of Type 1 configuration transaction include a 5-bit field designating the device number that identifies the device on the target PCI bus that is to be accessed. In addition, the bus number in Type 1 transactions specifies the PCI bus to which the transaction is targeted. TYPE 0 ACCESS TO PI7C8150A The configuration space is accessed by a Type 0 configuration transaction on the primary interface. The configuration space cannot be accessed from the secondary bus. The PI7C8150A responds to a Type 0 configuration transaction by asserting P_DEVSEL_L when the following conditions are met during the address phase: The bus command is a configuration read or configuration write transaction. Lowest two address bits P_AD[1:0] must be 00b. Signal P_IDSEL must be asserted. PI7C8150A limits all configuration access to a single DWORD data transfer and returns target-disconnect with the first data transfer if additional data phases are requested. Because read transactions to configuration space do not have side effects, all bytes in the requested DWORD are returned, regardless of the value of the byte enable bits. Type 0 configuration write and read transactions do not use data buffers that is, these transactions are completed immediately, regardless of the state of the data buffers. The PI7C8150A ignores all Type 0 transactions initiated on the secondary interface. TYPE 1 TO TYPE 0 CONVERSION Type 1 configuration transactions are used specifically for device configuration in a hierarchical PCI bus system. A PCI-to-PCI bridge is the only type of device that should respond to a Type 1 configuration command. Type 1 configuration commands are used when the configuration access is intended for a PCI device that resides on a PCI bus other than the one where the Type 1 transaction is generated. PI7C8150A performs a Type 1 to Type 0 translation when the Type 1 transaction is generated on the primary bus and is intended for a device attached directly to the secondary bus. PI7C8150A must convert the configuration command to a Type 0 format so that the Page 31 of 111 PI7C8150A 2-PORT PCI-TO-PCI BRIDGE secondary bus device can respond to it. Type 1 to Type 0 translations are performed only in the downstream direction that is, PI7C8150A generates a Type 0 transaction only on the secondary bus, and never on the primary bus. PI7C8150A responds to a Type 1 configuration transaction and translates it into a Type 0 transaction on the secondary bus when the following conditions are met during the address phase: The lowest two address bits on P_AD[1:0] are 01b. The bus number in address field P_AD[23:16] is equal to the value in the secondary bus number register in configuration space. The bus command on P_CBE[3:0] is a configuration read or configuration write transaction. When PI7C8150A translates the Type 1 transaction to a Type 0 transaction on the secondary interface, it performs the following translations to the address: Sets the lowest two address bits on S_AD[1:0]. Decodes the device number and drives the bit pattern specified in Table 3-6 on S_AD[31:16] for the purpose of asserting the device’s IDSEL signal. TRANSACTION ORDERING TRANSACTIONS GOVERNED BY ORDERING RULES Ordering relationships are established for the following classes of transactions crossing PI7C8150A: Posted write transactions, comprised of memory write and memory write and invalidate transactions. Posted write transactions complete at the source before they complete at the destination that is, data is written into intermediate data buffers before it reaches the target. Delayed write request transactions, comprised of I/O write and configuration write transactions. Delayed write requests are terminated by target retry on the initiator bus and are queued in the delayed transaction queue. A delayed write transaction must complete on the target bus before it completes on the initiator bus. Delayed write completion transactions, comprised of I/O write and configuration write transactions. Delayed write completion transactions complete on the target bus, and the target response is queued in the buffers. A delayed write completion transaction proceeds in the direction opposite that of the original delayed write request that is, a delayed write completion transaction proceeds from the target bus to the initiator bus. Delayed read request transactions, comprised of all memory read, I/O read, and configuration read transactions. Delayed read requests are terminated by target retry on the initiator bus and are queued in the delayed transaction queue. Delayed read completion transactions, comprised of all memory read, I/O read, & configuration read transactions. Delayed read completion transactions complete on the target bus, and the read data is queued in the read data buffers. A delayed read completion transaction proceeds in the direction opposite that of the original delayed read request that is, a delayed read completion transaction proceeds from the target bus to the initiator bus. PI7C8150A does not combine or merge write transactions: PI7C8150A does not combine separate write transactions into a single write optimization is best implemented in the originating master. 06-0057 Page 47 of 111 PI7C8150A 2-PORT PCI-TO-PCI BRIDGE PI7C8150A does not merge bytes on separate masked write transactions to the same DWORD optimization is also best implemented in the originating master. PI7C8150A does not collapse sequential write transactions to the same address into a single write PCI Local Bus Specification does not permit this combining of transactions. GENERAL ORDERING GUIDELINES Independent transactions on primary and secondary buses have a relationship only when those transactions cross PI7C8150A. The following general ordering guidelines govern transactions crossing PI7C8150A: The ordering relationship of a transaction with respect to other transactions is determined when the transaction completes, that is, when a transaction ends with a termination other than target retry. Requests terminated with target retry can be accepted and completed in any order with respect to other transactions that have been terminated with target retry. If the order of completion of delayed requests is important, the initiator should not start a second delayed transaction until the first one has been completed. If more than one delayed transaction is initiated, the initiator should repeat all delayed transaction requests, using some fairness algorithm. Repeating a delayed transaction cannot be contingent on completion of another delayed transaction. Otherwise, a deadlock can occur. Write transactions flowing in one direction have no ordering requirements with respect to write transactions flowing in the other direction. PI7C8150A can accept posted write transactions on both interfaces at the same time, as well as initiate posted write transactions on both interfaces at the same time. The acceptance of a posted memory write transaction as a target can never be contingent on the completion of a non-locked, non-posted transaction as a master. This is true for PI7C8150A and must also be true for other bus agents. Otherwise, a deadlock can occur. PI7C8150A accepts posted write transactions, regardless of the state of completion of any delayed transactions being forwarded across PI7C8150A. ORDERING RULES 06-0057 Page 48 of 111 PI7C8150A 2-PORT PCI-TO-PCI BRIDGE Table 5-1 shows the ordering relationships of all the transactions and refers by number to the ordering rules that follow. 06-0057 Page 49 of 111 PI7C8150A 2-PORT PCI-TO-PCI BRIDGE Table Summary of Transaction Ordering Pass Posted Delayed Delayed Delayed Read Delayed Write Write Read Write Completion Completion Request Request Posted Write Yes5 Yes5 Yes5 Yes5 Delayed Read Request Delayed Write Request Delayed Read Completion Delayed Write Completion Note The superscript accompanying some of the table entries refers to any applicable ordering rule listed in this section. Many entries are not governed by these ordering rules; therefore, the implementation can choose whether or not the transactions pass each other. The entries without superscripts reflect the PI7C8150A’s implementation choices. The following ordering rules describe the transaction relationships. Each ordering rule is followed by an explanation, and the ordering rules are referred to by number in 06-0057 Page 50 of 111 06-0057 PI7C8150A 2-PORT PCI-TO-PCI BRIDGE Table These ordering rules apply to posted write transactions, delayed write and read requests, and delayed write and read completion transactions crossing PI7C8150A in the same direction. Note that delayed completion transactions cross PI7C8150A in the direction opposite that of the corresponding delayed requests. Posted write transactions must complete on the target bus in the order in which they were received on the initiator bus. The subsequent posted write transaction can be setting a flag that covers the data in the first posted write transaction if the second transaction were to complete before the first transaction, a device checking the flag could subsequently consume stale data. A delayed read request traveling in the same direction as a previously queued posted write transaction must push the posted write data ahead of it. The posted write transaction must complete on the target bus before the delayed read request can be attempted on the target bus. The read transaction can be to the same location as the write data, so if the read transaction were to pass the write transaction, it would return stale data. A delayed read completion must ‘‘pull’’ ahead of previously queued posted write data traveling in the same direction. In this case, the read data is traveling in the same direction as the write data, and the initiator of the read transaction is on the same side of PI7C8150A as the target of the write transaction. The posted write transaction must complete to the target before the read data is returned to the initiator. The read transaction can be a reading to a status register of the initiator of the posted write data and therefore should not complete until the write transaction is complete. Delayed write requests cannot pass previously queued posted write data. For posted memory write transactions, the delayed write transaction can set a flag that covers the data in the posted write transaction. If the delayed write request were to complete before the earlier posted write transaction, a device checking the flag could subsequently consume stale data. Posted write transactions must be given opportunities to pass delayed read and write requests and completions. Otherwise, deadlocks may occur when some bridges which support delayed transactions and other bridges which do not support delayed transactions are being used in the same system. A fairness algorithm is used to arbitrate between the posted write queue and the delayed transaction queue. DATA SYNCHRONIZATION The device signaling the interrupt performs a read of the data just written software . The device driver performs a read operation to any register in the interrupting device before accessing data written by the device software . System hardware guarantees that write buffers are flushed before interrupts are forwarded. Page 51 of 111 PI7C8150A 2-PORT PCI-TO-PCI BRIDGE PI7C8150A does not have a hardware mechanism to guarantee data synchronization for posted write transactions. Therefore, all posted write transactions must be followed by a read operation, either from the device to the location just written or some other location along the same path , or from the device driver to one of the device registers. ERROR HANDLING PI7C8150A checks, forwards, and generates parity on both the primary and secondary interfaces. To maintain transparency, PI7C8150A always tries to forward the existing parity condition on one bus to the other bus, along with address and data. PI7C8150A always attempts to be transparent when reporting errors, but this is not always possible, given the presence of posted data and delayed transactions. To support error reporting on the PCI bus, PI7C8150A implements the following: PERR_L and SERR_L signals on both the primary and secondary interfaces Primary status and secondary status registers The device-specific P_SERR_L event disable register This chapter provides detailed information about how PI7C8150A handles errors. It also describes error status reporting and error operation disabling. ADDRESS PARITY ERRORS PI7C8150A checks address parity for all transactions on both buses, for all address and all bus commands. When PI7C8150A detects an address parity error on the primary interface, the following events occur: If the parity error response bit is set in the command register, PI7C8150A does not claim the transaction with P_DEVSEL_L this may allow the transaction to terminate in a master abort. If parity error response bit is not set, PI7C8150A proceeds normally and accepts the transaction if it is directed to or across PI7C8150A. PI7C8150A sets the detected parity error bit in the status register. PI7C8150A asserts P_SERR_L and sets signaled system error bit in the status register, if both the following conditions are met: The SERR_L enable bit is set in the command register. The parity error response bit is set in the command register. When PI7C8150A detects an address parity error on the secondary interface, the following events occur: 06-0057 Page 52 of 111 PI7C8150A 2-PORT PCI-TO-PCI BRIDGE If the parity error response bit is set in the bridge control register, PI7C8150A does not claim the transaction with S_DEVSEL_L this may allow the transaction to terminate in a master abort. If parity error response bit is not set, PI7C8150A proceeds normally and accepts transaction if it is directed to or across PI7C8150A. PI7C8150A sets the detected parity error bit in the secondary status register. PI7C8150A asserts P_SERR_L and sets signaled system error bit in status register, if both of the following conditions are met: The SERR_L enable bit is set in the command register. The parity error response bit is set in the bridge control register. DATA PARITY ERRORS When forwarding transactions, PI7C8150A attempts to pass the data parity condition from one interface to the other unchanged, whenever possible, to allow the master and target devices to handle the error condition. The following sections describe, for each type of transaction, the sequence of events that occurs when a parity error is detected and the way in which the parity condition is forwarded across PI7C8150A. CONFIGURATION WRITE TRANSACTIONS TO CONFIGURATION SPACE When PI7C8150A detects a data parity error during a Type 0 configuration write transaction to PI7C8150A configuration space, the following events occur: PART NUMBER ORDERING INFORMATION Part Number PI7C8150AMA PI7C8150AND PI7C8150AMA-33 PI7C8150AND-33 PI7C8150AMAE PI7C8150ANDE PI7C8150AMAE-33 Speed 66MHz 33MHz 66MHz 33MHz Pin Package 208 FQFP 256 PBGA 208 FQFP 256 PBGA 208 FQFP Pb-free & Green 256 PBGA Pb-free & Green 208 FQFP Pb-free & Green Temperature 0°C to 85°C 0°C to 85°C 0°C to 85°C 0°C to 85°C 0°C to 85°C 0°C to 85°C 0°C to 85°C 06-0057 Page 110 of 111 PI7C8150A 2-PORT PCI-TO-PCI BRIDGE 06-0057 Page 111 of 111

PDF Datasheet Preview

PI7C8150A
2-PORT PCI-to-PCI BRIDGE
06-0057
3545 North 1st Street, San Jose, CA 95134 Telephone 1-877-PERICOM, 1-877-737-4266

Fax 408-435-1100 Internet:

PI7C8150A 2-PORT PCI-TO-PCI BRIDGE

LIFE SUPPORT POLICY

Pericom Semiconductor Corporation’s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of PSC.
1 Life support devices or system are devices or systems which a Are intended for surgical implant into the body or b Support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Pericom Semiconductor Corporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom Semiconductor does not assume any responsibility for use of any circuitry described other than the circuitry embodied in a Pericom Semiconductor product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Pericom Semiconductor Corporation.

All other trademarks are of their respective companies.
06-0057

Page 2 of 111

PI7C8150A 2-PORT PCI-TO-PCI BRIDGE
10/15/03
05/20/05

Description First Release of Data Sheet Corrected VDD and VSS pin assignments in Section Removed pins 106 and 155 R16 and B14 as these should be MS1 and MS0 respectively.
04/20/06
Added Pb-free parts in the Ordering Information Removed ‘Advance Information’ from header

Removed email link

Changed logos
06-0057

Page 3 of 111

This page intentionally left blank.

PI7C8150A 2-PORT PCI-TO-PCI BRIDGE
06-0057

Page 4 of 111

PI7C8150A 2-PORT PCI-TO-PCI BRIDGE

TABLE OF CONTENTS
2 SIGNAL 12

SIGNAL 12 SIGNALS 12

PRIMARY BUS INTERFACE SIGNALS 12 CLOCK SIGNALS 15 MISCELLANEOUS 16 GENERAL PURPOSE I/O INTERFACE SIGNALS 17 JTAG BOUNDARY SCAN SIGNALS 17 POWER AND 17 PIN LIST 208-PIN FQFP 18 PIN LIST 256-BALL PBGA 20
3 PCI BUS 21

TYPES OF 22 SINGLE ADDRESS PHASE 22 DEVICE SELECT DEVSEL_L GENERATION 23 DATA PHASE 23 WRITE TRANSACTIONS 23

MEMORY WRITE 23 MEMORY WRITE AND INVALIDATE 24 DELAYED WRITE 25 WRITE TRANSACTION ADDRESS 26 BUFFERING MULTIPLE WRITE 26 FAST BACK-TO-BACK TRANSACTIONS 26 READ 27 PREFETCHABLE READ 27 NON-PREFETCHABLE READ 27 READ PREFETCH ADDRESS BOUNDARIES 28 DELAYED READ REQUESTS 28 DELAYED READ COMPLETION WITH TARGET 29 DELAYED READ COMPLETION ON INITIATOR 29 FAST BACK-TO-BACK READ TRANSACTION 30 CONFIGURATION TRANSACTIONS 30 TYPE 0 ACCESS TO 31 TYPE 1 TO TYPE 0 CONVERSION 31 TYPE 1 TO TYPE 1 33 SPECIAL CYCLES 34 TRANSACTION TERMINATION 34 MASTER TERMINATION INITIATED BY PI7C8150A 35 MASTER ABORT RECEIVED BY PI7C8150A 36 TARGET TERMINATION RECEIVED BY 36

DELAYED WRITE TARGET TERMINATION 37 POSTED WRITE TARGET TERMINATION RESPONSE 37 DELAYED READ TARGET TERMINATION RESPONSE 38 TARGET TERMINATION INITIATED BY 39 TARGET RETRY 39
06-0057

Page 5 of 111

PI7C8150A 2-PORT PCI-TO-PCI BRIDGE

TARGET DISCONNECT 40 TARGET ABORT 40
4 ADDRESS 41

ADDRESS RANGES 41 I/O ADDRESS 41

I/O BASE AND LIMIT ADDRESS 42 ISA 43 MEMORY ADDRESS DECODING 43 MEMORY-MAPPED I/O BASE AND LIMIT ADDRESS REGISTERS 44 PREFETCHABLE MEMORY BASE AND LIMIT ADDRESS REGISTERS 45 VGA 46 VGA 46 VGA SNOOP 46
5 TRANSACTION ORDERING 47
TRANSACTIONS GOVERNED BY ORDERING RULES 47 GENERAL ORDERING GUIDELINES 48 ORDERING 48 DATA SYNCHRONIZATION 51
6 ERROR HANDLING 52

ADDRESS PARITY ERRORS 52 DATA PARITY ERRORS 53

CONFIGURATION WRITE TRANSACTIONS TO CONFIGURATION SPACE.......... 53 READ TRANSACTIONS 53 DELAYED WRITE 54 POSTED WRITE 57 DATA PARITY ERROR REPORTING 58 SYSTEM ERROR SERR_L 62
7 EXCLUSIVE ACCESS 63

CONCURRENT LOCKS 63 ACQUIRING EXCLUSIVE ACCESS ACROSS PI7C8150A 63

LOCKED TRANSACTIONS IN DOWNSTREAM DIRECTION 63 LOCKED TRANSACTION IN UPSTREAM DIRECTION 65 ENDING EXCLUSIVE 65
8 PCI BUS ARBITRATION 66

PRIMARY PCI BUS ARBITRATION 66 SECONDARY PCI BUS 66

SECONDARY BUS ARBITRATION USING THE INTERNAL ARBITER.................... 66 PREEMPTION 68 SECONDARY BUS ARBITRATION USING AN EXTERNAL ARBITER...................... 68 BUS 68

PRIMARY CLOCK 69 SECONDARY CLOCK OUTPUTS 69
10 GENERAL PURPOSE I/O 69
06-0057

Page 6 of 111

PI7C8150A 2-PORT PCI-TO-PCI BRIDGE

GPIO CONTROL 70 SECONDARY CLOCK 70 LIVE INSERTION 72
11 PCI POWER MANAGEMENT 72
12 RESET 73

PRIMARY INTERFACE RESET 73 SECONDARY INTERFACE 74 CHIP 74
13 SUPPORTED 74

PRIMARY INTERFACE 74 SECONDARY 76
14 CONFIGURATION 77
06-0057

Page 7 of 111

PI7C8150A 2-PORT PCI-TO-PCI BRIDGE

SECONDARY BUS ARBITER PREEMPTION CONTROL REGISTER OFFSET 89 UPSTREAM S TO P MEMORY BASE REGISTER OFFSET 50h 89 UPSTREAM S TO P MEMORY LIMIT REGISTER OFFSET 50h....................... 90 UPSTREAM S TO P MEMORY BASE UPPER 32-BITS REGISTER OFFSET 54h 90 UPSTREAM S TO P MEMORY LIMIT UPPER 32-BITS REGISTER OFFSET 90 P_SERR_L EVENT DISABLE REGISTER OFFSET 90 GPIO DATA AND CONTROL REGISTER OFFSET 64h 91 SECONDARY CLOCK CONTROL REGISTER OFFSET 68h 92 P_SERR_L STATUS REGISTER OFFSET 68h 92 PORT OPTION REGISTER OFFSET 74h 93 RETRY COUNTER REGISTER OFFSET 78h 95 PRIMARY MASTER TIMEOUT COUNTER OFFSET 80h 95 SECONDARY MASTER TIMEOUT COUNTER OFFSET 80h 95 CAPABILITY ID REGISTER OFFSET B0h 95 NEXT POINTER REGISTER OFFSET B0h 95 SLOT NUMBER REGISTER OFFSET B0h 96 CHASSIS NUMBER REGISTER OFFSET B0h 96 CAPABILITY ID REGISTER OFFSET 96 NEXT ITEM POINTER REGISTER OFFSET DCh 96 POWER MANAGEMENT CAPABILITIES REGISTER OFFSET DCh 96 POWER MANAGEMENT DATA REGISTER OFFSET E0h................................... 97 CAPABILITY ID REGISTER OFFSET E4h 97 NEXT POINTER REGISTER OFFSET E4h 97
15 BRIDGE BEHAVIOR 97

BRIDGE ACTIONS FOR VARIOUS CYCLE 98 ABNORMAL TERMINATION INITIATED BY BRIDGE MASTER ................................ 98

MASTER 98 PARITY AND ERROR REPORTING 98 REPORTING PARITY ERRORS 99 SECONDARY IDSEL MAPPING 99
16 IEEE COMPATIBLE JTAG CONTROLLER 99

BOUNDARY SCAN 99 TAP PINS 100 INSTRUCTION REGISTER 100

BOUNDARY SCAN INSTRUCTION SET 101 TAP TEST DATA 102 BYPASS REGISTER 102 BOUNDARY-SCAN 102 TAP CONTROLLER 102
17 ELECTRICAL AND TIMING 106

MAXIMUM RATINGS 106 DC SPECIFICATIONS 106 AC 107 66MHZ 108 33MHZ 108 POWER CONSUMPTION 108
06-0057

Page 8 of 111

PI7C8150A 2-PORT PCI-TO-PCI BRIDGE
18 PACKAGE 109
208-PIN FQFP PACKAGE DIAGRAM 109 256-BALL PBGA PACKAGE DIAGRAM 110 PART NUMBER ORDERING 110

LIST OF TABLES
TABLE PIN LIST 208-PIN FQFP 18 TABLE PIN LIST 256-PIN PBGA 20 TABLE PCI TRANSACTIONS 22 TABLE WRITE TRANSACTION 23 TABLE WRITE TRANSACTION DISCONNECT ADDRESS BOUNDARIES 26 TABLE READ PREFETCH ADDRESS BOUNDARIES 28 TABLE READ TRANSACTION PREFETCHING 28 TABLE DEVICE NUMBER TO IDSEL S_AD PIN 32 TABLE DELAYED WRITE TARGET TERMINATION 37 TABLE RESPONSE TO POSTED WRITE TARGET 38 TABLE RESPONSE TO DELAYED READ TARGET TERMINATION 38 TABLE SUMMARY OF TRANSACTION ORDERING 50 TABLE SETTING THE PRIMARY INTERFACE DETECTED PARITY ERROR BIT 58 TABLE SETTING SECONDARY INTERFACE DETECTED PARITY ERROR BIT 59 TABLE SETTING PRIMARY INTERFACE MASTER DATA PARITY ERROR DETECTED BIT......................... 59 TABLE SETTING SECONDARY INTERFACE MASTER DATA PARITY ERROR DETECTED BIT 60 TABLE ASSERTION OF 60 TABLE ASSERTION OF 61 TABLE ASSERTION OF P_SERR_L FOR DATA PARITY ERRORS 61 TABLE GPIO OPERATION 71 TABLE GPIO SERIAL DATA 71 TABLE POWER MANAGEMENT TRANSITIONS 73 TABLE TAP PINS 101 TABLE JTAG BOUNDARY REGISTER ORDER 103

LIST OF FIGURES

FIGURE 8-1 SECONDARY ARBITER 67 FIGURE 16-1 TEST ACCESS PORT BLOCK DIAGRAM 100 FIGURE 17-1 PCI SIGNAL TIMING MEASUREMENT CONDITIONS 107 FIGURE 18-1 208-PIN FQFP PACKAGE 109 FIGURE 18-2 256-PIN PBGA PACKAGE 110
06-0057

Page 9 of 111

This page intentionally left blank.

PI7C8150A 2-PORT PCI-TO-PCI BRIDGE
06-0057

Page 10 of 111

PI7C8150A 2-PORT PCI-TO-PCI BRIDGE

INTRODUCTION

Product Description

Product Features
06-0057

Page 11 of 111

PI7C8150A 2-PORT PCI-TO-PCI BRIDGE

SIGNAL DEFINITIONS

Signal Types

Signal Type I O P TS STS

Description Input Only Output Only Power Tri-State bi-directional Sustained Tri-State. Active LOW signal must be pulled HIGH for 1 cycle when deasserting. Open Drain

Signals

Note Signal names that end with “_L” are active LOW.

PRIMARY BUS INTERFACE SIGNALS

Name P_AD[31:0]

P_CBE[3:0] P_PAR

Pin # 49, 50, 55, 57, 58, 60, 61, 63, 67, 68, 70, 71, 73, 74, 76, 77, 93, 95, 96, 98, 99, 101, 107, 109, 112, 113, 115, 116, 118, 119, 121, 122
64, 79, 92, 110

Pin # N3, T2, T4, N5, P5, T5, N6, R5, T6, P7, T7, R7, T8, P8, R8, T9, R12, P12, T14, R13, N12, T15, P16, N15, M14, M13, M15, L13, M16, L14, L15, L16 R6, R9, T13, N16

Type TS

Description Primary Address / Data Multiplexed address and data bus. Address is indicated by P_FRAME_L assertion. Write data is stable and valid when P_IRDY_L is asserted and read data is stable and valid when P_TRDY_L is asserted. Data is transferred on rising clock edges when both P_IRDY_L and P_TRDY_L are asserted. During bus idle, PI7C8150A drives P_AD to a valid logic level when P_GNT_L is asserted.

TS Primary Command/Byte Enables Multiplexed command field and byte enable field. During address phase, the initiator drives the transaction type on these pins. After that, the initiator drives the byte enables during data phases. During bus idle, PI7C8150A drives P_CBE[3:0] to a valid logic level when P_GNT_L is asserted.

TS Primary Parity. Parity is even across P_AD[31:0], P_CBE[3:0], and P_PAR i.e. an even number of 1’s . P_PAR is an input and is valid and stable one cycle after the address phase indicated by assertion of P_FRAME_L for address parity. For write data phases, P_PAR is an input and is valid one clock after P_IRDY_L is asserted. For read data phase, P_PAR is an output and is valid one clock after P_TRDY_L is asserted. Signal P_PAR is tri-stated one cycle after the P_AD lines are tri-stated. During bus idle, PI7C8150A drives P_PAR to a valid logic level when P_GNT_L is asserted.
06-0057

Page 12 of 111
06-0057

Name P_FRAME_L

Pin # 80

P_IRDY_L

P_TRDY_L

P_DEVSEL_L

P_STOP_L
When a write transaction is first detected on the initiator bus, and PI7C8150A forwards it as a delayed transaction, PI7C8150A claims the access by asserting DEVSEL_L and returns a target retry to the initiator. During the address phase, PI7C8150A samples the bus command, address, and address parity one cycle later. After IRDY_L is asserted, PI7C8150A also samples the first data DWORD, byte enable bits, and data parity. This information is placed into the delayed transaction queue. The transaction is queued only if no other existing delayed transactions have the same address and command, and if the delayed transaction queue is not full. When the delayed write transaction moves to the head of the delayed transaction queue and all ordering constraints with posted data are satisfied. The PI7C8150A initiates the transaction on the target bus. PI7C8150A transfers the write data to the target. If PI7C8150A receives a target retry in response to the write transaction on the target bus, it continues to repeat the write transaction until the data transfer is completed, or until an error condition is encountered.

If PI7C8150A is unable to deliver write data after 224 default or 232 maximum attempts, PI7C8150A will report a system error. PI7C8150A also asserts P_SERR_L if the primary SERR_L enable bit is set in the command register. See Section for information on the assertion of P_SERR_L. When the initiator repeats the same write transaction same command, address, byte enable bits, and data , and the completed delayed transaction is at the head of the queue, the PI7C8150A claims the access by asserting DEVSEL_L and returns TRDY_L to the initiator, to indicate that the write data was transferred. If the initiator requests multiple DWORD, PI7C8150A also asserts STOP_L in conjunction with TRDY_L to signal a target disconnect. Note that only those bytes of write data with valid byte enable bits are compared. If any of the byte enable bits are turned off driven HIGH , the corresponding byte of write data is not compared.

If the initiator repeats the write transaction before the data has been transferred to the target, PI7C8150A returns a target retry to the initiator. PI7C8150A continues to return a target retry to the initiator until write data is delivered to the target, or until an error condition is encountered. When the write transaction is repeated, PI7C8150A does not make a new entry into the delayed transaction queue. Section provides detailed information about how PI7C8150A responds to target termination during delayed write transactions.
06-0057

Page 25 of 111

PI7C8150A 2-PORT PCI-TO-PCI BRIDGE

PI7C8150A implements a discard timer that starts counting when the delayed write completion is at the head of the delayed transaction completion queue. The initial value of this timer can be set to the retry counter register offset 78h.

If the initiator does not repeat the delayed write transaction before the discard timer expires, PI7C8150A discards the delayed write completion from the delayed transaction completion queue. PI7C8150A also conditionally asserts P_SERR_L see Section

WRITE TRANSACTION ADDRESS BOUNDARIES

PI7C8150A imposes internal address boundaries when accepting write data. The aligned address boundaries are used to prevent PI7C8150A from continuing a transaction over a device address boundary and to provide an upper limit on maximum latency. PI7C78150A returns a target disconnect to the initiator when it reaches the aligned address boundaries under conditions shown in Table

Table Write Transaction Disconnect Address Boundaries

Type of Transaction

Condition

Aligned Address Boundary

Delayed Write

Disconnects after one data transfer

Posted Memory Write

Memory write disconnect control 4KB aligned address boundary bit = 0 1

Posted Memory Write

Memory write disconnect control Disconnects at cache line boundary bit = 1

Posted Memory Write and Cache line size 1, 2, 4, 8, 16
4KB aligned address boundary

Invalidate

Posted Memory Write and Cache line size = 1, 2, 4, 8, 16

Cache line boundary if posted memory

Invalidate
write data FIFO does not have enough
space for the cache line

Note Memory write disconnect control bit is bit 1 of the chip control register at offset 40h in the
configuration space.

BUFFERING MULTIPLE WRITE TRANSACTIONS

PI7C8150A continues to accept posted memory write transactions as long as space for at least one DWORD of data in the posted write data buffer remains. If the posted write data buffer fills before the initiator terminates the write transaction, PI7C8150A returns a target disconnect to the initiator.

Delayed write transactions are posted as long as at least one open entry in the delayed transaction queue exists. Therefore, several posted and delayed write transactions can exist in data buffers at the same time. See Chapter 6 for information about how multiple posted and delayed write transactions are ordered.

FAST BACK-TO-BACK TRANSACTIONS

PI7C8150A can recognize and post fast back-to-back write transactions. When PI7C8150A cannot accept the second transaction because of buffer space limitations, it returns a target retry to the initiator. The fast back-to-back enable bit must be set in the command register for upstream write transactions, and in the bridge control register for downstream write transactions.
06-0057

Page 26 of 111

PI7C8150A 2-PORT PCI-TO-PCI BRIDGE

READ TRANSACTIONS

Delayed read forwarding is used for all read transactions crossing PI7C8150A. Delayed read transactions are treated as either prefetchable or non-prefetchable. Table 3-5 shows the read behavior, prefetchable or non-prefetchable, for each type of read operation.

PREFETCHABLE READ TRANSACTIONS
When the transaction has been completed on the target bus, and the delayed read data is at the head of the read data queue, and all ordering constraints with posted write transactions have been satisfied, the PI7C8150A transfers the data to the initiator when the initiator repeats the transaction. For memory read transactions, PI7C8150A aliases the memory read, memory read line, and memory read multiple bus commands when matching the bus command of the transaction to the bus command in the delayed transaction queue. PI7C8150A returns a target disconnect along with the transfer of the last DWORD of read data to the initiator. If PI7C8150A initiator terminates the transaction before all read data has been transferred, the remaining read data left in data buffers is discarded.
06-0057

Page 29 of 111

PI7C8150A 2-PORT PCI-TO-PCI BRIDGE

When the master repeats the transaction and starts transferring prefetchable read data from data buffers while the read transaction on the target bus is still in progress and before a read boundary is reached on the target bus, the read transaction starts operating in flow-through mode. Because data is flowing through the data buffers from the target to the initiator, long read bursts can then be sustained. In this case, the read transaction is allowed to continue until the initiator terminates the transaction, or until an aligned 4KB address boundary is reached, or until the buffer fills, whichever comes first. When the buffer empties, PI7C8150A reflects the stalled condition to the initiator by disconnecting the initiator with data. The initiator may retry the transaction later if data are needed. If the initiator does not need any more data, the initiator will not continue the disconnected transaction. In this case, PI7C8150A will start the master timeout timer. The remaining read data will be discarded after the master timeout timer expires. To provide better latency, if there are any other pending data for other transactions in the RDB Read Data Buffer , the remaining read data will be discarded even though the master timeout timer has not expired.

PI7C8150A implements a master timeout timer that starts counting when the delayed read completion is at the head of the delayed transaction queue, and the read data is at the head of the read data queue. The initial value of this timer is programmable through configuration register. If the initiator does not repeat the read transaction and before the master timeout timer expires 215 default , PI7C8150A discards the read transaction and read data from its queues. PI7C8150A also conditionally asserts P_SERR_L see Section

PI7C8150A has the capability to post multiple delayed read requests, up to a maximum of four in each direction. If an initiator starts a read transaction that matches the address and read command of a read transaction that is already queued, the current read command is not posted as it is already contained in the delayed transaction queue.

See Section 5 for a discussion of how delayed read transactions are ordered when crossing PI7C8150A.

FAST BACK-TO-BACK READ TRANSACTION

PI7C8150A can recognize fast back-to-back read transactions.

CONFIGURATION TRANSACTIONS

Configuration transactions are used to initialize a PCI system. Every PCI device has a configuration space that is accessed by configuration commands. All registers are accessible in configuration space only.

In addition to accepting configuration transactions for initialization of its own configuration space, the PI7C8150A also forwards configuration transactions for device initialization in hierarchical PCI systems, as well as for special cycle generation.

To support hierarchical PCI bus systems, two types of configuration transactions are specified Type 0 and Type
06-0057

Page 30 of 111

PI7C8150A 2-PORT PCI-TO-PCI BRIDGE
06-0057

Type 0 configuration transactions are issued when the intended target resides on the same PCI bus as the initiator. A Type 0 configuration transaction is identified by the configuration command and the lowest two bits of the address set to 00b.

Type 1 configuration transactions are issued when the intended target resides on another PCI bus, or when a special cycle is to be generated on another PCI bus. A Type 1 configuration command is identified by the configuration command and the lowest two address bits set to 01b.

The register number is found in both Type 0 and Type 1 formats and gives the DWORD address of the configuration register to be accessed. The function number is also included in both Type 0 and Type 1 formats and indicates which function of a multifunction device is to be accessed. For single-function devices, this value is not decoded. The addresses of Type 1 configuration transaction include a 5-bit field designating the device number that identifies the device on the target PCI bus that is to be accessed. In addition, the bus number in Type 1 transactions specifies the PCI bus to which the transaction is targeted.

TYPE 0 ACCESS TO PI7C8150A

The configuration space is accessed by a Type 0 configuration transaction on the primary interface. The configuration space cannot be accessed from the secondary bus. The PI7C8150A responds to a Type 0 configuration transaction by asserting P_DEVSEL_L when the following conditions are met during the address phase:

The bus command is a configuration read or configuration write transaction.

Lowest two address bits P_AD[1:0] must be 00b.

Signal P_IDSEL must be asserted.

PI7C8150A limits all configuration access to a single DWORD data transfer and returns target-disconnect with the first data transfer if additional data phases are requested. Because read transactions to configuration space do not have side effects, all bytes in the requested DWORD are returned, regardless of the value of the byte enable bits.

Type 0 configuration write and read transactions do not use data buffers that is, these transactions are completed immediately, regardless of the state of the data buffers. The PI7C8150A ignores all Type 0 transactions initiated on the secondary interface.

TYPE 1 TO TYPE 0 CONVERSION

Type 1 configuration transactions are used specifically for device configuration in a hierarchical PCI bus system. A PCI-to-PCI bridge is the only type of device that should respond to a Type 1 configuration command. Type 1 configuration commands are used when the configuration access is intended for a PCI device that resides on a PCI bus other than the one where the Type 1 transaction is generated.

PI7C8150A performs a Type 1 to Type 0 translation when the Type 1 transaction is generated on the primary bus and is intended for a device attached directly to the secondary bus. PI7C8150A must convert the configuration command to a Type 0 format so that the

Page 31 of 111

PI7C8150A 2-PORT PCI-TO-PCI BRIDGE
secondary bus device can respond to it. Type 1 to Type 0 translations are performed only in the downstream direction that is, PI7C8150A generates a Type 0 transaction only on the secondary bus, and never on the primary bus.

PI7C8150A responds to a Type 1 configuration transaction and translates it into a Type 0 transaction on the secondary bus when the following conditions are met during the address phase:

The lowest two address bits on P_AD[1:0] are 01b.

The bus number in address field P_AD[23:16] is equal to the value in the secondary bus number register in configuration space.

The bus command on P_CBE[3:0] is a configuration read or configuration write transaction.

When PI7C8150A translates the Type 1 transaction to a Type 0 transaction on the secondary interface, it performs the following translations to the address:

Sets the lowest two address bits on S_AD[1:0].

Decodes the device number and drives the bit pattern specified in Table 3-6 on S_AD[31:16] for the purpose of asserting the device’s IDSEL signal.
TRANSACTION ORDERING
TRANSACTIONS GOVERNED BY ORDERING RULES
Ordering relationships are established for the following classes of transactions crossing PI7C8150A:

Posted write transactions, comprised of memory write and memory write and invalidate transactions. Posted write transactions complete at the source before they complete at the destination that is, data is written into intermediate data buffers before it reaches the target.

Delayed write request transactions, comprised of I/O write and configuration write transactions. Delayed write requests are terminated by target retry on the initiator bus and are queued in the delayed transaction queue. A delayed write transaction must complete on the target bus before it completes on the initiator bus.

Delayed write completion transactions, comprised of I/O write and configuration write transactions. Delayed write completion transactions complete on the target bus, and the target response is queued in the buffers. A delayed write completion transaction proceeds in the direction opposite that of the original delayed write request that is, a delayed write completion transaction proceeds from the target bus to the initiator bus.

Delayed read request transactions, comprised of all memory read, I/O read, and configuration read transactions. Delayed read requests are terminated by target retry on the initiator bus and are queued in the delayed transaction queue.

Delayed read completion transactions, comprised of all memory read, I/O read, & configuration read transactions. Delayed read completion transactions complete on the target bus, and the read data is queued in the read data buffers. A delayed read completion transaction proceeds in the direction opposite that of the original delayed read request that is, a delayed read completion transaction proceeds from the target bus to the initiator bus.

PI7C8150A does not combine or merge write transactions:

PI7C8150A does not combine separate write transactions into a single write optimization is best implemented in the originating master.
06-0057

Page 47 of 111

PI7C8150A 2-PORT PCI-TO-PCI BRIDGE

PI7C8150A does not merge bytes on separate masked write transactions to the same DWORD optimization is also best implemented in the originating master.

PI7C8150A does not collapse sequential write transactions to the same address into a single write PCI Local Bus Specification does not permit this combining of transactions.
GENERAL ORDERING GUIDELINES

Independent transactions on primary and secondary buses have a relationship only when those transactions cross PI7C8150A.
The following general ordering guidelines govern transactions crossing PI7C8150A:
The ordering relationship of a transaction with respect to other transactions is determined when the transaction completes, that is, when a transaction ends with a termination other than target retry.

Requests terminated with target retry can be accepted and completed in any order with respect to other transactions that have been terminated with target retry. If the order of completion of delayed requests is important, the initiator should not start a second delayed transaction until the first one has been completed. If more than one delayed transaction is initiated, the initiator should repeat all delayed transaction requests, using some fairness algorithm. Repeating a delayed transaction cannot be contingent on completion of another delayed transaction. Otherwise, a deadlock can occur.
Write transactions flowing in one direction have no ordering requirements with respect to write transactions flowing in the other direction. PI7C8150A can accept posted write transactions on both interfaces at the same time, as well as initiate posted write transactions on both interfaces at the same time.

The acceptance of a posted memory write transaction as a target can never be contingent on the completion of a non-locked, non-posted transaction as a master. This is true for PI7C8150A and must also be true for other bus agents. Otherwise, a deadlock can occur.

PI7C8150A accepts posted write transactions, regardless of the state of completion of any delayed transactions being forwarded across PI7C8150A.
ORDERING RULES
06-0057

Page 48 of 111

PI7C8150A 2-PORT PCI-TO-PCI BRIDGE
Table 5-1 shows the ordering relationships of all the transactions and refers by number to the ordering rules that follow.
06-0057

Page 49 of 111

PI7C8150A 2-PORT PCI-TO-PCI BRIDGE
Table Summary of Transaction Ordering

Pass

Posted

Delayed

Delayed

Delayed Read Delayed Write

Write

Read

Write

Completion

Completion

Request

Request

Posted Write

Yes5

Yes5

Yes5

Yes5

Delayed Read Request

Delayed Write Request

Delayed Read

Completion

Delayed Write

Completion

Note The superscript accompanying some of the table entries refers to any applicable
ordering rule listed in this section. Many entries are not governed by these ordering rules;
therefore, the implementation can choose whether or not the transactions pass each other.

The entries without superscripts reflect the PI7C8150A’s implementation choices.
The following ordering rules describe the transaction relationships. Each ordering rule is followed by an explanation, and the ordering rules are referred to by number in
06-0057

Page 50 of 111
06-0057

PI7C8150A 2-PORT PCI-TO-PCI BRIDGE
Table These ordering rules apply to posted write transactions, delayed write and read requests, and delayed write and read completion transactions crossing PI7C8150A in the same direction. Note that delayed completion transactions cross PI7C8150A in the direction opposite that of the corresponding delayed requests.

Posted write transactions must complete on the target bus in the order in which they were received on the initiator bus. The subsequent posted write transaction can be setting a flag that covers the data in the first posted write transaction if the second transaction were to complete before the first transaction, a device checking the flag could subsequently consume stale data.

A delayed read request traveling in the same direction as a previously queued posted write transaction must push the posted write data ahead of it. The posted write transaction must complete on the target bus before the delayed read request can be attempted on the target bus. The read transaction can be to the same location as the write data, so if the read transaction were to pass the write transaction, it would return stale data.

A delayed read completion must ‘‘pull’’ ahead of previously queued posted write data traveling in the same direction. In this case, the read data is traveling in the same direction as the write data, and the initiator of the read transaction is on the same side of PI7C8150A as the target of the write transaction. The posted write transaction must complete to the target before the read data is returned to the initiator. The read transaction can be a reading to a status register of the initiator of the posted write data and therefore should not complete until the write transaction is complete.

Delayed write requests cannot pass previously queued posted write data. For posted memory write transactions, the delayed write transaction can set a flag that covers the data in the posted write transaction. If the delayed write request were to complete before the earlier posted write transaction, a device checking the flag could subsequently consume stale data.

Posted write transactions must be given opportunities to pass delayed read and write requests and completions. Otherwise, deadlocks may occur when some bridges which support delayed transactions and other bridges which do not support delayed transactions are being used in the same system. A fairness algorithm is used to arbitrate between the posted write queue and the delayed transaction queue.

DATA SYNCHRONIZATION

The device signaling the interrupt performs a read of the data just written software .

The device driver performs a read operation to any register in the interrupting device before accessing data written by the device software .

System hardware guarantees that write buffers are flushed before interrupts are forwarded.

Page 51 of 111

PI7C8150A 2-PORT PCI-TO-PCI BRIDGE

PI7C8150A does not have a hardware mechanism to guarantee data synchronization for posted write transactions. Therefore, all posted write transactions must be followed by a read operation, either from the device to the location just written or some other location along the same path , or from the device driver to one of the device registers.

ERROR HANDLING

PI7C8150A checks, forwards, and generates parity on both the primary and secondary interfaces. To maintain transparency, PI7C8150A always tries to forward the existing parity condition on one bus to the other bus, along with address and data. PI7C8150A always attempts to be transparent when reporting errors, but this is not always possible, given the presence of posted data and delayed transactions.

To support error reporting on the PCI bus, PI7C8150A implements the following:

PERR_L and SERR_L signals on both the primary and secondary interfaces

Primary status and secondary status registers

The device-specific P_SERR_L event disable register

This chapter provides detailed information about how PI7C8150A handles errors. It also describes error status reporting and error operation disabling.

ADDRESS PARITY ERRORS

PI7C8150A checks address parity for all transactions on both buses, for all address and all bus commands. When PI7C8150A detects an address parity error on the primary interface, the following events occur:

If the parity error response bit is set in the command register, PI7C8150A does not claim the transaction with P_DEVSEL_L this may allow the transaction to terminate in a master abort. If parity error response bit is not set, PI7C8150A proceeds normally and accepts the transaction if it is directed to or across PI7C8150A.

PI7C8150A sets the detected parity error bit in the status register.

PI7C8150A asserts P_SERR_L and sets signaled system error bit in the status register, if both the following conditions are met:

The SERR_L enable bit is set in the command register.

The parity error response bit is set in the command register.

When PI7C8150A detects an address parity error on the secondary interface, the following events occur:
06-0057

Page 52 of 111

PI7C8150A 2-PORT PCI-TO-PCI BRIDGE

If the parity error response bit is set in the bridge control register, PI7C8150A does not claim the transaction with S_DEVSEL_L this may allow the transaction to terminate in a master abort. If parity error response bit is not set, PI7C8150A proceeds normally and accepts transaction if it is directed to or across PI7C8150A.

PI7C8150A sets the detected parity error bit in the secondary status register.

PI7C8150A asserts P_SERR_L and sets signaled system error bit in status register, if both of the following conditions are met:

The SERR_L enable bit is set in the command register.

The parity error response bit is set in the bridge control register.

DATA PARITY ERRORS

When forwarding transactions, PI7C8150A attempts to pass the data parity condition from one interface to the other unchanged, whenever possible, to allow the master and target devices to handle the error condition.

The following sections describe, for each type of transaction, the sequence of events that occurs when a parity error is detected and the way in which the parity condition is forwarded across PI7C8150A.

CONFIGURATION WRITE TRANSACTIONS TO CONFIGURATION SPACE

When PI7C8150A detects a data parity error during a Type 0 configuration write transaction to PI7C8150A configuration space, the following events occur:
PART NUMBER ORDERING INFORMATION

Part Number PI7C8150AMA PI7C8150AND PI7C8150AMA-33 PI7C8150AND-33 PI7C8150AMAE PI7C8150ANDE PI7C8150AMAE-33

Speed 66MHz 33MHz 66MHz 33MHz

Pin Package 208 FQFP 256 PBGA 208 FQFP 256 PBGA 208 FQFP Pb-free & Green 256 PBGA Pb-free & Green 208 FQFP Pb-free & Green

Temperature 0°C to 85°C 0°C to 85°C 0°C to 85°C 0°C to 85°C 0°C to 85°C 0°C to 85°C 0°C to 85°C
06-0057

Page 110 of 111

PI7C8150A 2-PORT PCI-TO-PCI BRIDGE
06-0057

Page 111 of 111

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived PI7C8150ANDE-2017 Datasheet file may be downloaded here without warranties.

Datasheet ID: PI7C8150ANDE-2017 510104