CYW20713A1KUBXGT

CYW20713A1KUBXGT Datasheet

CYW20713

Part	Datasheet
CYW20713A1KUBXGT	CYW20713A1KUBXGT (pdf)

Related Parts	Information
CYW20713A1KUFBXG	CYW20713A1KUFBXG

PDF Datasheet Preview
CYW20713 Single-Chip Bluetooth Transceiver and Baseband Processor The Cypress CYW20713 is a monolithic, single-chip, Bluetooth compliant, stand-alone baseband processor with an integrated GHz transceiver. Manufactured using the industry's most advanced 65 nm CMOS low-power process, the CYW20713 employs the highest level of integration, eliminating all critical external components, and thereby minimizing the device’s footprint and costs associated with the implementation of Bluetooth solutions. The CYW20713 brings the latest mobile connectivity technology to automotive radio and industrial Bluetooth applications. Offering automotive Grade 3 to +85°C temperature performance, the CYW20713 is tested to AECQ100 environmental stress guidelines and manufactured in ISO9001 and TS16949 certified facilities. Cypress Part Numbering Scheme Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion, there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides Cypress ordering part number that matches an existing IoT part number. Table Mapping Table for Part Number between Broadcom and Cypress Broadcom Part Number BCM20713 BCM20713A1KUBG BCM20713A1KUFBXG Cypress Part Number CYW20713 CYW20713A1KUBG CYW20713A1KUFBXG Acronyms and Abbreviations In most cases, acronyms and abbreviations are defined on first use. For a comprehensive list of acronyms and other terms used in Cypress documents, go to: • Bluetooth + EDR compliant. • Class 1 capable with built-in PA. • Programmable output power control meets Class 1, Class 2, or Class 3 requirements. • Use supply voltages up to 5.5V.Supports Cypress wide-band speech, SBC codec, and packet loss concealment. • Fractional-N synthesizer supports frequency references from 12 MHz to 52 MHz. • Automatic frequency detection for standard crystal and TCXO values when an external kHz reference clock is provided. • Ultra-low power consumption. • Supports serial flash interfaces. • Available in 42-bump WLBGA and 50-ball FPBGA packages. • microprocessor with integrated ROM and RAM. • Supports patch RAM download without external memory. • Automotive handsfree radios • Automotive data communication • Industrial appliances • San Jose, CA 95134-1709 • 408-943-2600 PCM UART GPIO Memory SPI I2S TCXO LPO Figure System Block Diagram CYW20713 High-Speed Peripheral Transport Unit PTU Radio Transceiver Microprocessor and Memory Unit uPU Bluetooth Baseband Core BBC CYW20713 IoT Resources Cypress provides a wealth of data at to help you to select the right IoT device for your design, and quickly and effectively integrate the device into your design. Cypress provides customer access to a wide range of information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software updates. Customers can acquire technical documentation and software from the Cypress Support Community website Page 2 of 52 CYW20713 Contents Overview 4 Major Features 4 Block Diagram 6 Usage Model 7 Integrated Radio Transceiver 8 Transmitter Path 8 Receiver Path 8 Local Oscillator Generation 8 Calibration 8 Internal LDO Regulator 9 Bluetooth Baseband Core 10 Transmit and Receive Functions 10 Bluetooth + EDR Features 10 Frequency Hopping Generator 10 Link Control Layer 11 Test Mode Support 11 Power Management Unit 11 Adaptive Frequency Hopping 13 Collaborative Coexistence 13 Serial Enhanced Coexistence Interface 14 Microprocessor Unit 15 NVRAM Configuration Data and Storage 15 EEPROM 15 External Reset 15 One-Time Programmable Memory 16 Peripheral Transport Unit 17 PCM Interface 17 HCI Transport Detection Configuration 19 UART Interface 19 SPI 19 Frequency References 20 Crystal Interface and Clock Generation 20 Crystal Oscillator 21 External Frequency Reference 21 Frequency Selection 23 Frequency Trimming 23 LPO Clock Interface 24 Pin Information 25 Pin Descriptions 25 Ball Maps 27 Electrical Characteristics 29 Electrostatic Discharge Specifications 31 RF Specifications 34 Timing and AC Characteristics 37 I2S Interface 44 Mechanical Information 47 Tape, Reel, and Packing Specification 49 Ordering Information 50 Document History 51 Page 3 of 52 CYW20713 Overview The Cypress CYW20713 complies with the Bluetooth Core Specification, version and is designed for use with a standard host controller interface HCI UART. The combination of the Bluetooth baseband core BBC , a Peripheral Transport Unit PTU , and an ARM-based microprocessor with on-chip ROM provides a complete lower layer Bluetooth protocol stack, including the link controller LC , link manager LM , and HCI. Major Features Major features of the CYW20713 include: • Support for Bluetooth + EDR, including the following options Whitelist size of 25 Enhanced Power Control HCI Read Encryption Key Size command • Full support for Bluetooth + EDR additional features Secure simple pairing SSP Encryption pause resume EPR Enhance inquiry response EIR Link supervision time out LSTO Sniff subrating SSR Erroneous data ED Packet boundary flag PBF • Built-in low drop-out LDO regulators 2 to 5.5V input voltage range to 3.3V intermediate programmable output voltage • Integrated RF section Single-ended, 50 ohm RF interface Built-in TX/RX switch functionality TX Class 1 output power capability -88 dBm RX sensitivity basic rate • Supports maximum Bluetooth data rates over HCI UART and SPI interfaces • Multipoint operation, with up to seven active slaves Maximum of seven simultaneous active ACL links Maximum of three simultaneous active SCO and eSCO links, with Scatternet support • Scatternet operation, with up to four active piconets with background scan and support for ScatterMode • High-speed HCI UART transport support H4 five-wire UART four signal wires, one ground wire H5 three-wire UART two signal wires, one ground wire Maximum UART baud rates of 4 Mbps Low-power out-of-band BT_WAKE and HOST_WAKE signaling VSC from host transport to UART Proprietary compressing scheme allows more than two simultaneous A2DP packets and up to five devices at a time • Channel quality-driven data rate CQDDR and packet type selection • Standard Bluetooth test modes • Extended radio and production test mode features • Full support for power savings modes Bluetooth standard hold and sniff Deep sleep modes and regulator shutdown Page 4 of 52 CYW20713 • Supports wideband speech WBS over PCM and packet loss concealment PLC for better audio quality • 2-, 3-, and 4-wire coexistence • Power amplifier PA shutdown for externally controlled coexistence, such as WIMAX • Built-in LPO clock or operation using an external LPO clock • TCXO input and auto-detection of all standard handset clock frequencies supports low-power crystal, which can be used during Power Saving mode with better timing accuracy • OR gate for combining a host clock request with a Bluetooth clock request operates even when the Bluetooth core logic is powered off • Larger patch RAM space to support future enhancements • Serial flash Interface with native support for devices from several manufacturers • One-time programmable OTP memory Page 5 of 52 Block Diagram Figure 2 on page 6 shows the interconnect of the major CYW20713 physical blocks and associated external interfaces. Figure Functional Block Diagram JTAG Flash ARM7TDMI-S AHB2EBI External Bus I/F Trap & Patch 32-bit AHB AHB2APB AHB2MEM Address Decoder AHB2MEM PMU Control WD Timer GPIO+Aux OTP 128 bytes SPI The CYW20713 supports a slave SPI HCI transport with an input clock range of up to 16 MHz. Higher clock rates may be possible. The physical interface between the SPI master and the CYW20713 consists of the four SPI signals SPI_CSB, SPI_CLK, SPI_SI, and SPI_SO and one interrupt signal SPI_INT . The CYW20713 can be configured to accept active-low or active-high polarity on the SPI_CSB chip select signal. It can also be configured to drive an active-low or active-high SPI_INT interrupt signal. Bit ordering on the SPI_SI and SPI_SO data lines can be configured as either little-endian or big-endian. Additionally, proprietary sleep mode, halfduplex handshaking is implemented between the SPI master and the CYW20713. SPI_INT is required to negotiate the start of a transaction. The SPI interface does not require flow control in the middle of a payload. The FIFO is large enough to handle the largest packet size. Only the SPI master can stop the flow of bytes on the data lines, since it controls SPI_CSB and SPI_CLK. Flow control should be implemented in higher layer protocols. Page 19 of 52 CYW20713 Frequency References The CYW20713 uses two different frequency references for normal and low-power operational modes. An external crystal or frequency reference driven by a Temperature Compensated Crystal Oscillator TCXO signal is used to generate the radio frequencies and normal operation clocking. Either an external kHz or fully integrated internal Low-Power Oscillator LPO is used for lowpower mode timing. Crystal Interface and Clock Generation The CYW20713 uses a fractional-N synthesizer to generate the radio frequencies, clocks, and data/packet timing, enabling it to operate from any of a multitude of frequency sources. The source can be external, such as a TCXO, or a crystal interfaced directly to the device. The default frequency reference setting is for a 20 MHz crystal or TCXO. The signal characteristics for the crystal interface are listed in Table 4 on page Table Crystal Interface Signal Characteristics Parameter Acceptable frequencies Crystal load capacitance ESR Power dissipation Input signal amplitude Crystal MHz in 2 ppma steps 12 typical 60 max 200 max N/A Signal type Input impedance Phase noise 1 kHz 10 kHz 100 kHz 1 MHz Auto-detection frequencies when using external LPOc 12, 13, 18, 20, 24, 26, and Tolerance without frequency ±20 trimmingd Initial frequency tolerance trimming ±50 range External Frequency Reference MHz in 2 ppma steps N/A 400 to 2000 to 3300 requires a 10 pF DC blocking capacitor to attenuate the signal Square-wave or sine-wave < < < < 12, 13, 18, 20, 24, 26, and ±20 Units pF mVp-p dBc/Hz dBc/Hz dBc/Hz dBc/Hz ±50 a. The frequency step size is approximately 80 Hz resolution. b. With a 26 MHz reference clock. For a 13 MHz clock, subtract 6 dB. For a 52 MHz clock, add 6 dB. c. Auto-detection of the frequency requires the crystal or external frequency reference to have less than ±50 ppm of variation and also requires an external LPO frequency which has less than ±250 ppm of variation at the time of detection. d. AT-Cut crystal or TXCO recommended. Page 20 of 52 CYW20713 Crystal Oscillator The CYW20713 can use an external crystal to provide a frequency reference. The recommended configuration for the crystal oscillator, including all external components, is shown in Figure Figure Recommended Oscillator Configuration 0 to 18 pF* Crystal Oscillator 0 to 18 pF* XOUT Capacitor value range depends on the manufacturer of the XTAL as well as board layout External Frequency Reference An external frequency reference generated by a TCXO signal that may be directly connected to the crystal input pin on the CYW20713, as shown in Figure The external frequency reference input is designed to not change loading on the TCXO when the CYW20713 is powered up or powered down. When using the CYW20713 with the TXCO OR gate option, GPIO 6 must be driven active high or active low. Excessive leakage current results if GPIO6 is allowed to float. Figure Recommended TCXO Connection TCXO pF packages. See Section “Ordering Information,” on page VDDO GPIO TCXO-OR Function In available on some packages. See Section “Ordering Information,” on page VDDO DETATCH/CARD_DETECT VDDO UART receive data VDDO UART transmit data VDDO UART request to send output VDDO UART clear to send input Page 25 of 52 CYW20713 Table CYW20713 Signal Descriptions Cont. Signal SCL SDA SPIM_CLK SPIM_CS_N PCM_IN PCM_OUT PCM_CLK PCM_SYNC COEX_IN COEX_OUT0 COEX_OUT1 OTP_DIS Supplies VDDIF VDDTF VDDLNA VDDRF VDDPX VDDC VDDO NC VSS FPBGA 50-Ball F7 E7 A8 C7 F6 G6 F4 F5 B6 E4 E5 B1 C1 E1 F1 G1 A5 B8 F8 G5 A6 G8 C2 D2 F2 D3 C6 A7 G7 WLBGA 42-Bump E1 D1 C1 E2 D4 E4 C4 A4 A2 B7 E7 F7 A3 F1 D3 B1 D7 B6 E6 F6 F3 A1 B2 Power Domain VDDO I2C clock VDDO I2C data VDDO Serial flash SPI clock VDDO Serial flash active-low chip select VDDO PCM/I2S data input VDDO PCM/I2S data output VDDO PCM/I2S clock VDDO PCM sync/I2S word select VDDO Coexistence input VDDO Coexistence output VDDO Coexistence output VDDO OTP disable pin. By default, leave this pin floating. Radio IF PLL supply Radio PA supply Radio LNA supply Radio supply Radio RF PLL supply Core logic supply Core logic supply Core logic supply Digital I/O supply voltage Digital I/O supply voltage Ordering Information Table 30 lists available part numbers and describes differences in package type, available I/O, and functional configuration. See the referenced figures and tables for mechanical drawings and package I/O information. All packages are rated from to +85°C. Table Part Ordering Information Part Number CYW20713A1KUFBXG CYW20713A1KUBG Package Type 50-ball FPBGA, mm x mm x mm. See Figure 20 on page 42-bump WLBGA, mm x mm x mm. See Figure 21 on page Functional I/O Features Dedicated Coexa, more GPIO, TM0b Table 9 on page 27 Strapped Configuration TCXO AND/OR mode enabled Table 10 on page 28 TCXO AND/OR mode enabled a. All packages support coexistence features through the ability to re-purpose most digital I/O based on the desired user configuration. Package include balls coexistence functionality default . b. TM0 allows configuration of CLK_REQ output polarity. Page 50 of 52 CYW20713 Document History Document Title CYW20713 Single-Chip Bluetooth Transceiver and Baseband Processor Document Number 002-14806 Orig. of Submission Change Description of Change 08/14/14 20713-DS100-R Initial release 20713-DS101-R 10/16/14 Updated: • General description on page 20713-DS102-R 12/22/15 Added: • “I2S Interface” on page 57 5482527 UTSV 10/20/16 Updated to Cypress Template Page 51 of 52 CYW20713 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Microcontrollers cypress.com/arm PSoC 1 \| PSoC 3 \| PSoC 4 \| PSoC 5LP Automotive Clocks & Buffers Interface Internet of Things Lighting & Power Control Memory cypress.com/automotive cypress.com/clocks cypress.com/interface cypress.com/iot cypress.com/powerpsoc cypress.com/memory

PDF Datasheet Preview

CYW20713

Single-Chip Bluetooth Transceiver and Baseband Processor

The Cypress CYW20713 is a monolithic, single-chip, Bluetooth compliant, stand-alone baseband processor with an integrated GHz transceiver. Manufactured using the industry's most advanced 65 nm CMOS low-power process, the CYW20713 employs the highest level of integration, eliminating all critical external components, and thereby minimizing the device’s footprint and costs associated with the implementation of Bluetooth solutions. The CYW20713 brings the latest mobile connectivity technology to automotive radio and industrial Bluetooth applications. Offering automotive Grade 3 to +85°C temperature performance, the CYW20713 is tested to AECQ100 environmental stress guidelines and manufactured in ISO9001 and TS16949 certified facilities.

Cypress Part Numbering Scheme
Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion, there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides Cypress ordering part number that matches an existing IoT part number.

Table Mapping Table for Part Number between Broadcom and Cypress

Broadcom Part Number BCM20713 BCM20713A1KUBG BCM20713A1KUFBXG

Cypress Part Number CYW20713 CYW20713A1KUBG CYW20713A1KUFBXG

Acronyms and Abbreviations In most cases, acronyms and abbreviations are defined on first use. For a comprehensive list of acronyms and other terms used in Cypress documents, go to:
• Bluetooth + EDR compliant.
• Class 1 capable with built-in PA.
• Programmable output power control meets Class 1, Class 2,
or Class 3 requirements.
• Use supply voltages up to 5.5V.Supports Cypress
wide-band speech, SBC codec, and packet loss concealment.
• Fractional-N synthesizer supports frequency references from 12 MHz to 52 MHz.
• Automatic frequency detection for standard crystal and TCXO values when an external kHz reference clock is provided.
• Ultra-low power consumption.
• Supports serial flash interfaces.
• Available in 42-bump WLBGA and 50-ball FPBGA packages.
• microprocessor with
integrated ROM and RAM.
• Supports patch RAM download without external memory.
• Automotive handsfree radios
• Automotive data communication
• Industrial appliances
• San Jose, CA 95134-1709
• 408-943-2600

PCM UART GPIO Memory

SPI I2S

TCXO LPO

Figure System Block Diagram CYW20713

High-Speed Peripheral Transport Unit PTU

Radio Transceiver

Microprocessor and Memory Unit uPU

Bluetooth Baseband Core BBC

CYW20713

IoT Resources

Cypress provides a wealth of data at to help you to select the right IoT device for your design, and quickly and effectively integrate the device into your design. Cypress provides customer access to a wide range of information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software updates. Customers can acquire technical documentation and software from the Cypress Support Community website

Page 2 of 52

CYW20713

Contents

Overview 4 Major Features 4 Block Diagram 6 Usage Model 7

Integrated Radio Transceiver 8 Transmitter Path 8 Receiver Path 8 Local Oscillator Generation 8 Calibration 8 Internal LDO Regulator 9

Bluetooth Baseband Core 10 Transmit and Receive Functions 10 Bluetooth + EDR Features 10 Frequency Hopping Generator 10 Link Control Layer 11 Test Mode Support 11 Power Management Unit 11 Adaptive Frequency Hopping 13 Collaborative Coexistence 13 Serial Enhanced Coexistence Interface 14

Microprocessor Unit 15 NVRAM Configuration Data and Storage 15 EEPROM 15 External Reset 15 One-Time Programmable Memory 16

Peripheral Transport Unit 17 PCM Interface 17 HCI Transport Detection Configuration 19 UART Interface 19 SPI 19

Frequency References 20 Crystal Interface and Clock Generation 20 Crystal Oscillator 21 External Frequency Reference 21 Frequency Selection 23 Frequency Trimming 23 LPO Clock Interface 24

Pin Information 25 Pin Descriptions 25 Ball Maps 27

Electrical Characteristics 29 Electrostatic Discharge Specifications 31 RF Specifications 34 Timing and AC Characteristics 37 I2S Interface 44

Mechanical Information 47 Tape, Reel, and Packing Specification 49
Ordering Information 50 Document History 51

Page 3 of 52

CYW20713

Overview

The Cypress CYW20713 complies with the Bluetooth Core Specification, version and is designed for use with a standard host controller interface HCI UART. The combination of the Bluetooth baseband core BBC , a Peripheral Transport Unit PTU , and an ARM-based microprocessor with on-chip ROM provides a complete lower layer Bluetooth protocol stack, including the link controller LC , link manager LM , and HCI.

Major Features

Major features of the CYW20713 include:
• Support for Bluetooth + EDR, including the following options Whitelist size of 25 Enhanced Power Control HCI Read Encryption Key Size command
• Full support for Bluetooth + EDR additional features Secure simple pairing SSP Encryption pause resume EPR Enhance inquiry response EIR Link supervision time out LSTO Sniff subrating SSR Erroneous data ED Packet boundary flag PBF
• Built-in low drop-out LDO regulators 2 to 5.5V input voltage range to 3.3V intermediate programmable output voltage
• Integrated RF section Single-ended, 50 ohm RF interface Built-in TX/RX switch functionality TX Class 1 output power capability -88 dBm RX sensitivity basic rate
• Supports maximum Bluetooth data rates over HCI UART and SPI interfaces
• Multipoint operation, with up to seven active slaves Maximum of seven simultaneous active ACL links Maximum of three simultaneous active SCO and eSCO links, with Scatternet support
• Scatternet operation, with up to four active piconets with background scan and support for ScatterMode
• High-speed HCI UART transport support H4 five-wire UART four signal wires, one ground wire H5 three-wire UART two signal wires, one ground wire Maximum UART baud rates of 4 Mbps Low-power out-of-band BT_WAKE and HOST_WAKE signaling VSC from host transport to UART Proprietary compressing scheme allows more than two simultaneous A2DP packets and up to five devices at a time
• Channel quality-driven data rate CQDDR and packet type selection
• Standard Bluetooth test modes
• Extended radio and production test mode features
• Full support for power savings modes Bluetooth standard hold and sniff Deep sleep modes and regulator shutdown

Page 4 of 52

CYW20713
• Supports wideband speech WBS over PCM and packet loss concealment PLC for better audio quality
• 2-, 3-, and 4-wire coexistence
• Power amplifier PA shutdown for externally controlled coexistence, such as WIMAX
• Built-in LPO clock or operation using an external LPO clock
• TCXO input and auto-detection of all standard handset clock frequencies supports low-power crystal, which can be used during

Power Saving mode with better timing accuracy
• OR gate for combining a host clock request with a Bluetooth clock request operates even when the Bluetooth core logic is powered
off
• Larger patch RAM space to support future enhancements
• Serial flash Interface with native support for devices from several manufacturers
• One-time programmable OTP memory

Page 5 of 52

Block Diagram Figure 2 on page 6 shows the interconnect of the major CYW20713 physical blocks and associated external interfaces.

Figure Functional Block Diagram

JTAG Flash

ARM7TDMI-S

AHB2EBI

External Bus I/F

Trap & Patch
32-bit AHB

AHB2APB

AHB2MEM

Address Decoder

AHB2MEM

PMU Control

WD Timer

GPIO+Aux

OTP 128 bytes
SPI The CYW20713 supports a slave SPI HCI transport with an input clock range of up to 16 MHz. Higher clock rates may be possible. The physical interface between the SPI master and the CYW20713 consists of the four SPI signals SPI_CSB, SPI_CLK, SPI_SI, and SPI_SO and one interrupt signal SPI_INT . The CYW20713 can be configured to accept active-low or active-high polarity on the SPI_CSB chip select signal. It can also be configured to drive an active-low or active-high SPI_INT interrupt signal. Bit ordering on the SPI_SI and SPI_SO data lines can be configured as either little-endian or big-endian. Additionally, proprietary sleep mode, halfduplex handshaking is implemented between the SPI master and the CYW20713. SPI_INT is required to negotiate the start of a transaction. The SPI interface does not require flow control in the middle of a payload. The FIFO is large enough to handle the largest packet size. Only the SPI master can stop the flow of bytes on the data lines, since it controls SPI_CSB and SPI_CLK. Flow control should be implemented in higher layer protocols.

Page 19 of 52

CYW20713

Frequency References

The CYW20713 uses two different frequency references for normal and low-power operational modes. An external crystal or frequency reference driven by a Temperature Compensated Crystal Oscillator TCXO signal is used to generate the radio frequencies and normal operation clocking. Either an external kHz or fully integrated internal Low-Power Oscillator LPO is used for lowpower mode timing.

Crystal Interface and Clock Generation The CYW20713 uses a fractional-N synthesizer to generate the radio frequencies, clocks, and data/packet timing, enabling it to operate from any of a multitude of frequency sources. The source can be external, such as a TCXO, or a crystal interfaced directly to the device. The default frequency reference setting is for a 20 MHz crystal or TCXO. The signal characteristics for the crystal interface are listed in Table 4 on page

Table Crystal Interface Signal Characteristics

Parameter Acceptable frequencies Crystal load capacitance ESR Power dissipation Input signal amplitude

Crystal MHz in 2 ppma steps 12 typical 60 max 200 max N/A

Signal type

Input impedance

Phase noise
1 kHz
10 kHz
100 kHz
1 MHz

Auto-detection frequencies when using external LPOc
12, 13, 18, 20, 24, 26, and

Tolerance without frequency
±20
trimmingd

Initial frequency tolerance trimming ±50 range

External Frequency Reference MHz in 2 ppma steps N/A 400 to 2000 to 3300 requires a 10 pF DC blocking capacitor to attenuate the signal Square-wave or sine-wave < < < < 12, 13, 18, 20, 24, 26, and ±20

Units pF
mVp-p
dBc/Hz dBc/Hz dBc/Hz dBc/Hz
±50
a. The frequency step size is approximately 80 Hz resolution. b. With a 26 MHz reference clock. For a 13 MHz clock, subtract 6 dB. For a 52 MHz clock, add 6 dB. c. Auto-detection of the frequency requires the crystal or external frequency reference to have less than ±50 ppm of variation and also requires an external LPO frequency
which has less than ±250 ppm of variation at the time of detection. d. AT-Cut crystal or TXCO recommended.

Page 20 of 52

CYW20713

Crystal Oscillator The CYW20713 can use an external crystal to provide a frequency reference. The recommended configuration for the crystal oscillator, including all external components, is shown in Figure

Figure Recommended Oscillator Configuration
0 to 18 pF*

Crystal Oscillator
0 to 18 pF*

XOUT
*Capacitor value range depends on the manufacturer of the XTAL as well as board layout

External Frequency Reference An external frequency reference generated by a TCXO signal that may be directly connected to the crystal input pin on the CYW20713, as shown in Figure The external frequency reference input is designed to not change loading on the TCXO when the CYW20713 is powered up or powered down. When using the CYW20713 with the TXCO OR gate option, GPIO 6 must be driven active high or active low. Excessive leakage current results if GPIO6 is allowed to float.

Figure Recommended TCXO Connection

TCXO pF*
packages. See Section “Ordering Information,”
on page

VDDO GPIO

TCXO-OR Function In available on some
packages. See Section “Ordering Information,”
on page

VDDO DETATCH/CARD_DETECT

VDDO UART receive data

VDDO UART transmit data

VDDO UART request to send output

VDDO UART clear to send input

Page 25 of 52

CYW20713

Table CYW20713 Signal Descriptions Cont.

Signal

SCL SDA SPIM_CLK SPIM_CS_N PCM_IN PCM_OUT PCM_CLK PCM_SYNC COEX_IN COEX_OUT0 COEX_OUT1 OTP_DIS Supplies VDDIF VDDTF VDDLNA VDDRF VDDPX VDDC VDDO NC VSS

FPBGA 50-Ball

F7 E7 A8 C7 F6 G6 F4 F5 B6 E4 E5

B1 C1 E1 F1 G1 A5 B8 F8 G5 A6 G8 C2 D2 F2 D3 C6 A7 G7

WLBGA 42-Bump

E1 D1 C1 E2 D4 E4 C4 A4 A2

B7 E7 F7 A3 F1 D3 B1 D7 B6 E6 F6 F3 A1 B2

Power Domain

VDDO I2C clock

VDDO I2C data

VDDO Serial flash SPI clock

VDDO Serial flash active-low chip select

VDDO PCM/I2S data input

VDDO PCM/I2S data output

VDDO PCM/I2S clock

VDDO PCM sync/I2S word select

VDDO Coexistence input

VDDO Coexistence output

VDDO Coexistence output

VDDO OTP disable pin. By default, leave this pin floating.

Radio IF PLL supply

Radio PA supply

Radio LNA supply

Radio supply

Radio RF PLL supply

Core logic supply

Core logic supply

Core logic supply

Digital I/O supply voltage

Digital I/O supply voltage
Ordering Information

Table 30 lists available part numbers and describes differences in package type, available I/O, and functional configuration. See the referenced figures and tables for mechanical drawings and package I/O information. All packages are rated from to +85°C.
Table Part Ordering Information

Part Number CYW20713A1KUFBXG

CYW20713A1KUBG

Package Type
50-ball FPBGA, mm x mm x mm. See Figure 20 on page 42-bump WLBGA, mm x mm x mm. See Figure 21 on page

Functional I/O Features Dedicated Coexa, more GPIO, TM0b Table 9 on page 27

Strapped Configuration

TCXO AND/OR mode enabled

Table 10 on page 28

TCXO AND/OR mode enabled
a. All packages support coexistence features through the ability to re-purpose most digital I/O based on the desired user configuration. Package include balls coexistence functionality default .
b. TM0 allows configuration of CLK_REQ output polarity.

Page 50 of 52

CYW20713

Document History

Document Title CYW20713 Single-Chip Bluetooth Transceiver and Baseband Processor Document Number 002-14806

Orig. of Submission

Change

Description of Change
08/14/14
20713-DS100-R Initial release
20713-DS101-R
10/16/14 Updated:
• General description on page
20713-DS102-R
12/22/15 Added:
• “I2S Interface” on page 57
5482527 UTSV
10/20/16 Updated to Cypress Template

Page 51 of 52

CYW20713

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products Microcontrollers
cypress.com/arm

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP

Automotive Clocks & Buffers Interface Internet of Things Lighting & Power Control Memory
cypress.com/automotive cypress.com/clocks
cypress.com/interface cypress.com/iot
cypress.com/powerpsoc cypress.com/memory

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CYW20713A1KUBXGT Datasheet file may be downloaded here without warranties.

Datasheet ID: CYW20713A1KUBXGT 508250