CYV15G0404RB-BGXC

CYV15G0404RB-BGXC Datasheet

CYV15G0404RB

Part	Datasheet
CYV15G0404RB-BGXC	CYV15G0404RB-BGXC (pdf)

Related Parts	Information
CYV15G0404RB-BGC	CYV15G0404RB-BGC

PDF Datasheet Preview
CYV15G0404RB Independent Clock Quad HOTLink II Deserializing Reclocker • Second-generation technology • Compliant to SMPTE 292M and SMPTE 259M video standards • Quad channel video reclocking deserializer 195 to 1500 Mbps serial data signaling rate Simultaneous operation at different signaling rates • Supports reception of either or Gbps data rate with the same training clock • Supports half-rate and full-rate clocking • Internal phase-locked loops PLLs with no external PLL components • Selectable differential PECL-compatible serial inputs Internal DC restoration • Synchronous LVTTL parallel interface • JTAG boundary scan • Built-In Self-Test BIST for at-speed link testing • Link Quality Indicator Analog signal detect Digital signal detect • Low-power 3W 3.3V typical • Single 3.3V supply • Thermally enhanced BGA • Pb-Free package option available • BiCMOS technology Functional Description The CYV15G0404RB Independent Clock Quad HOTLink II Deserializing Reclocker is a point-to-point or point-to-multipoint communications building block enabling data transfer over a variety of high speed serial links including SMPTE 292 and SMPTE 259 video applications. It supports signaling rates in the range of 195 to 1500 Mbps for each serial link. The four channels are independent and can simultaneously operate at different rates. Each receive channel accepts serial data and converts it to 10-bit parallel characters and presents these characters to an Output Register. The received serial data can also be reclocked and retransmitted through the reclocker serial outputs. Figure 1, "HOTLink II System Connections," on page 2 illustrates typical connections between independent video coprocessors and corresponding CYV15G0404RB Reclocking Deserializer and CYV15G0403TB Serializer chips. The CYV15G0404RB is SMPTE-259M and SMPTE-292M compliant according to SMPTE EG34-1999 Pathological Test Requirements. As a second generation HOTLink device, the CYV15G0404RB extends the HOTLink family with enhanced levels of integration and faster data rates, while maintaining serial-link compatibility data and BIST with other HOTLink devices. Each channel of the CYV15G0404RB Quad HOTLink II device accepts a serial bit-stream from one of two selectable PECL-compatible differential line receivers, and using a completely integrated Clock and Data Recovery PLL, recovers the timing information necessary for data reconstruction. The device reclocks and retransmits recovered bit-stream through the reclocker serial outputs. It also deserializes the recovered serial data and presents it to the destination host system. Each channel contains an independent BIST pattern checker. This BIST hardware enables at speed testing of the high-speed serial data paths in each receive section of this device, each transmit section of a connected HOTLink II device, and across the interconnecting links. The CYV15G0404RB is ideal for SMPTE applications where different data rates and serial interface standards are necessary for each channel. Some applications include multi-format routers, switchers, format converters, SDI monitors, and camera control units. • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CYV15G0404RB Video Coprocessor Video Coprocessor Figure HOTLink II System Connections Reclocked Outputs Independent Channel CYV15G0403TB Serializer Serial Links Independent Channel CYV15G0404RB Reclocking Deserializer Reclocked Outputs CYV15G0404RB Deserializing Reclocker Logic Block Diagram RXDA[9:0] TRGCLKA± RXDB[9:0] TRGCLKB± RXDC[9:0] TRGCLKC± RXDD[9:0] TRGCLKD± Deserializer Deserializer Deserializer Deserializer Reclocker Reclocker RX Reclocker RX Reclocker ROUTA1± ROUTA2± Ordering Information Speed Ordering Code Standard CYV15G0404RB-BGC Standard CYV15G0404RB-BGXC Package Name BL256 BL256 Package Type 256-Ball Thermally Enhanced Ball Grid Array Pb-Free 256-Ball Thermally Enhanced Ball Grid Array Operating Range Commercial Commercial Package Diagram Figure 256-Lead L2 Ball Grid Array 27 x 27 x mm BL256 A1 CORNER I.D. TOP VIEW REF. 0.20 4X A BOTTOM VIEW BALL SIDE Ø0.75±0.15 256X 20 18 16 14 12 10 8 6 4 2 19 17 15 13 11 9 7 5 3 1 R Max 4X MIN. A1 CORNER I.D. 26° TYP. SEATING PLANE MIN TOP OF MOLD COMPOUND TO TOP OF BALLS SIDE VIEW SECTION A-A 51-85123-*E HOTLink is a registered trademark and HOTLink II is a trademark of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders. Page 26 of 27 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CYV15G0404RB Document History Page Document Title CYV15G0404RB Independent Clock Quad HOTLink II Deserializing Reclocker Document Number 38-02102 ECN NO. ISSUE DATE ORIG. OF CHANGE DESCRIPTION OF CHANGE 246850 See ECN

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CYV15G0404RB

Independent Clock Quad HOTLink II Deserializing Reclocker
• Second-generation technology
• Compliant to SMPTE 292M and SMPTE 259M video
standards
• Quad channel video reclocking deserializer
195 to 1500 Mbps serial data signaling rate Simultaneous operation at different signaling rates
• Supports reception of either or Gbps data rate with the same training clock
• Supports half-rate and full-rate clocking
• Internal phase-locked loops PLLs with no external PLL components
• Selectable differential PECL-compatible serial inputs Internal DC restoration
• Synchronous LVTTL parallel interface
• JTAG boundary scan
• Built-In Self-Test BIST for at-speed link testing
• Link Quality Indicator Analog signal detect Digital signal detect
• Low-power 3W 3.3V typical
• Single 3.3V supply
• Thermally enhanced BGA
• Pb-Free package option available
• BiCMOS technology

Functional Description

The CYV15G0404RB Independent Clock Quad HOTLink II Deserializing Reclocker is a point-to-point or point-to-multipoint communications building block enabling data transfer over a variety of high speed serial links including SMPTE 292
and SMPTE 259 video applications. It supports signaling rates in the range of 195 to 1500 Mbps for each serial link. The four channels are independent and can simultaneously operate at different rates. Each receive channel accepts serial data and converts it to 10-bit parallel characters and presents these characters to an Output Register. The received serial data can also be reclocked and retransmitted through the reclocker serial outputs. Figure 1, "HOTLink II System Connections," on page 2 illustrates typical connections between independent video coprocessors and corresponding CYV15G0404RB Reclocking Deserializer and CYV15G0403TB Serializer chips.

The CYV15G0404RB is SMPTE-259M and SMPTE-292M compliant according to SMPTE EG34-1999 Pathological Test Requirements.

As a second generation HOTLink device, the CYV15G0404RB extends the HOTLink family with enhanced levels of integration and faster data rates, while maintaining serial-link compatibility data and BIST with other HOTLink devices.

Each channel of the CYV15G0404RB Quad HOTLink II device accepts a serial bit-stream from one of two selectable PECL-compatible differential line receivers, and using a completely integrated Clock and Data Recovery PLL, recovers the timing information necessary for data reconstruction. The device reclocks and retransmits recovered bit-stream through the reclocker serial outputs. It also deserializes the recovered serial data and presents it to the destination host system.

Each channel contains an independent BIST pattern checker. This BIST hardware enables at speed testing of the high-speed serial data paths in each receive section of this device, each transmit section of a connected HOTLink II device, and across the interconnecting links.

The CYV15G0404RB is ideal for SMPTE applications where different data rates and serial interface standards are necessary for each channel. Some applications include multi-format routers, switchers, format converters, SDI monitors, and camera control units.
• 198 Champion Court
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

CYV15G0404RB

Video Coprocessor

Video Coprocessor

Figure HOTLink II System Connections

Reclocked Outputs

Independent

Channel

CYV15G0403TB

Serializer

Serial Links

Independent

Channel

CYV15G0404RB

Reclocking Deserializer

Reclocked Outputs

CYV15G0404RB Deserializing Reclocker Logic Block Diagram

RXDA[9:0] TRGCLKA± RXDB[9:0] TRGCLKB± RXDC[9:0] TRGCLKC± RXDD[9:0] TRGCLKD±

Deserializer

Deserializer

Deserializer

Deserializer

Reclocker

Reclocker RX

Reclocker RX

Reclocker

ROUTA1± ROUTA2±
Ordering Information

Speed
Ordering Code

Standard CYV15G0404RB-BGC Standard CYV15G0404RB-BGXC

Package Name

BL256

BL256

Package Type
256-Ball Thermally Enhanced Ball Grid Array Pb-Free 256-Ball Thermally Enhanced Ball Grid Array

Operating Range

Commercial

Commercial

Package Diagram

Figure 256-Lead L2 Ball Grid Array 27 x 27 x mm BL256

A1 CORNER I.D.

TOP VIEW

REF.
0.20 4X A

BOTTOM VIEW BALL SIDE
Ø0.75±0.15 256X
20 18 16 14 12 10 8 6 4 2 19 17 15 13 11 9 7 5 3 1

R Max 4X

MIN.

A1 CORNER I.D.
26°

TYP.

SEATING PLANE

MIN TOP OF MOLD COMPOUND TO TOP OF BALLS

SIDE VIEW

SECTION A-A
51-85123-*E

HOTLink is a registered trademark and HOTLink II is a trademark of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders.

Page 26 of 27

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
[+] Feedback

CYV15G0404RB

Document History Page

Document Title CYV15G0404RB Independent Clock Quad HOTLink II Deserializing Reclocker Document Number 38-02102

ECN NO.

ISSUE DATE

ORIG. OF CHANGE

DESCRIPTION OF CHANGE
246850 See ECN

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CYV15G0404RB-BGXC Datasheet file may be downloaded here without warranties.

Datasheet ID: CYV15G0404RB-BGXC 508245