CYD04S72V-167BBC

CYD04S72V-167BBC Datasheet

CYD04S72V CYD09S72V CYD18S72V

Part	Datasheet
CYD04S72V-167BBC	CYD04S72V-167BBC (pdf)

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CYD04S72V CYD09S72V CYD18S72V FLEx72 V 64 K/128 K/256 K x 72 Synchronous Dual-Port RAM Functional Description • True dual-ported memory cells that allow simultaneous access of the same memory location • Synchronous pipelined operation • Family of 4 Mbit, 9 Mbit, and 18 Mbit devices • Pipelined output mode allows fast operation • 0.18-micron complmentary metal oxide semiconductor CMOS for optimum speed and power • High-speed clock to data access • V low power Active as low as 225 mA typ Standby as low as 55 mA typ • Mailbox function for message passing • Global master reset • Separate byte enables on both ports • Commercial and industrial temperature ranges • IEEE 1149.1-compatible joint test action group JTAG boundary scan • 484-ball fine-pitch ball grid array FBGA 1-mm pitch • Pb-free packaging available • Counter wrap around control Internal mask register controls counter wrap-around Counter-interrupt flags to indicate wrap-around Memory block retransmit operation • Counter readback on address lines • Mask register readback on address lines • Dual chip enables on both ports for easy depth expansion • Seamless migration to next generation dual-port family The FLEx72 family includes 4 Mbit, 9 Mbit and 18 Mbit pipelined, synchronous, true dual-port static RAMs that are high-speed, low-power V CMOS. Two ports are provided, permitting independent, simultaneous access to any location in memory. The result of writing to the same location by more than one port at the same time is undefined. Registers on control, address, and data lines allow for minimal set-up and hold time. During a Read operation, data is registered for decreased cycle time. Each port contains a burst counter on the input address register. After externally loading the counter with the initial address, the counter will increment the address internally more details to follow . The internal write pulse width is independent of the duration of the R/W input signal. The internal write pulse is self-timed to allow the shortest possible cycle times. A HIGH on CE0 or LOW on CE1 for one clock cycle will power down the internal circuitry to reduce the static power consumption. One cycle with chip enables asserted is required to reactivate the outputs. Additional features include readback of burst-counter internal address value on address lines, counter-mask registers to control the counter wrap-around, counter interrupt CNTINT flags, readback of mask register value on address lines, retransmit functionality, interrupt flags for message passing, JTAG for boundary scan, and asynchronous Master Reset MRST . The CYD18S72V device have limited features. Please see Table 3 on page 8 for details. Seamless Migration to Next-Generation Dual-Port Family Cypress offers a migration path for all devices to the next-generation devices in the Dual-Port family with a compatible footprint. Please contact Cypress Sales for more details Table Product Selection Guide Density Part number Max. speed MHz Max. access to data ns Typical operating current mA Package 4-Mbit 64K x 72 CYD04S72V 484-ball FBGA 23 mm x 23 mm 9-Mbit 128K x 72 CYD09S72V 484-ball FBGA 23 mm x 23 mm 18-Mbit 256K x 72 CYD18S72V 484-ball FBGA 23 mm x 23 mm Maximum 13 Operating Range 13 Electrical Characteristics Over the Operating Range 13 Capacitance 14 AC Test Load and Waveforms 14 Switching Characteristics Over the Operating Range 14 JTAG Timing Characteristics 16 Switching Waveforms 16 Ordering Information 26 Ordering Code Definitions 26 Package Diagram 27 Acronyms 28 Document Conventions 28 Units of Measure 28 Document History Page 29 Sales, Solutions, and Legal Information 30 Worldwide Sales and Design Support 30 Products 30 PSoC Solutions 30 Page 3 of 30 CYD04S72V CYD09S72V CYD18S72V Pin Configuration 484-ball BGA Top View CYD04S72V/CYD09S72V/CYD18S72V 10 11 12 13 14 15 16 17 18 19 20 21 22 A NC DQ61L DQ59L DQ57L DQ54L DQ51L DQ48L DQ45L DQ42L DQ39L DQ36L DQ36R DQ39R DQ42R DQ45R DQ48R DQ51R DQ54R DQ57R DQ59R DQ61R NC B DQ63L DQ62L DQ60L DQ58L DQ55L DQ52L DQ49L DQ46L DQ43L DQ40L DQ37L DQ37R DQ40R DQ43R DQ46R DQ49R DQ52R DQ55R DQ58R DQ60R DQ62R DQ63R C DQ65L DQ64L VSS DQ56L DQ53L DQ50L DQ47L DQ44L DQ41L DQ38L DQ38R DQ41R DQ44R DQ47R DQ50R DQ53R DQ56R VSS DQ64R DQ65R DQ67L DQ66L VSS D NC [2, 5] NC [2, 5] VSS LOWSP PORTS NC [2, 5] BUSYL CNTINT PORTS DL[2,4] TD0L [2, 5] L TD1L [2,4] [10] [2, 4] NC [2, 5] NC [2, 5] VSS DQ66R DQ67R DQ69L DQ68L VDDIOL VSS E VSS VDDIOL VDDIO VDDIOL VTTL VDDIO VDDIOR NC VSS VDDIOR DQ68R DQ69R DQ71L DQ70L CE1L[8] CE0L [9] VDDIOL VDDIO VDDIOL VCORE VDDIO VDDIOR CE0R [9] CE1R[8] DQ70R DQ71R G A0L A1L RETL[2,3] BE4L VDDIOL VREFL VSS [2, 4] VSS VREFR VDDIOR BE4R RETR[2,3 A1R [2, 4] H A2L A3L WRPL[2, BE5L VDDIOL VSS VSS VDDIOR BE5R WRPR[2, A3R J A4L A5L READYL BE6L VDDIOL VSS [2, 5] VSS VDDIOR BE6R READYR A5R [2, 5] K A6L A7L NC[2,5] BE7L VTTL VCORE VSS VCORE VDDIOR BE7R NC[2,5] A7R A6R Ordering Information Speed MHz Ordering Code Package Name Package Type Operating Range 256K x 72 18-Mbit V Synchronous CYD18S72V Dual-Port SRAM CYD18S72V-133BBI BB484 484-ball Grid Array Industrial 23 mm x 23 mm with 1.0-mm pitch FBGA CYD18S72V-100BBC BB484 484-ball Grid Array Commercial 23 mm x 23 mm with 1.0-mm pitch FBGA CYD18S72V-100BBI BB484 484-ball Grid Array Industrial 23 mm x 23 mm with 1.0-mm pitch FBGA 128K x 72 9-Mbit V Synchronous CYD09S72V Dual-Port SRAM CYD09S72V-133BBC BB484 484-ball Grid Array Commercial 23 mm x 23 mm with 1.0-mm pitch FBGA 64K x 72 4-Mbit V Synchronous CYD04S72V Dual-Port SRAM CYD04S72V-167BBC BB484 484-ball Grid Array Commercial 23 mm x 23 mm with 1.0-mm pitch FBGA Ordering Code Definitions CY D XX S 72 V - XXX BB X Temperature Range X = C or I C = Commercial I = Industrial X = Pb-free RoHS Compliant Package Type BB = 484-ball BGA Speed Grade XXX = 100 MHz / 133 MHz / 167 MHz V = V 72 = Width x 72 S = Sync XX = Density 04 = 4 Mb 09 = 9 Mb 18 = 18 Mb D = Dual Port SRAM CY = Cypress Device Page 26 of 30 Package Diagram CYD04S72V CYD09S72V CYD18S72V 51-85124 *H Page 27 of 30 Acronyms Acronym CMOS FBGA JTAG OE RAM Description Complementary metal oxide semiconductor fine-pitch ball grid array joint test action group Output enable Random access memory Document Conventions Units of Measure Symbol °C MHz µA mA mV mW ns pF V W Unit of Measure degree Celcius megahertz microamperes milliamperes millivolts milliwatts nanoseconds picofarad volts watts CYD04S72V CYD09S72V CYD18S72V Page 28 of 30 CYD04S72V CYD09S72V CYD18S72V Document History Page Document Title CYD04S72V / CYD09S72V / CYD18S72V FLEx72 V 64 K/128 K/256 K x 72 Synchronous Dual-Port RAM Document Number 38-06069 ECN NO. Issue Date Orig. of Change Description of Change 125859 06/17/03 SPN New Data Sheet 128707 08/01/03 SPN Added -133 speed bin Updated spec values for ICC, tHA, tHB, tHW, tHD Added new parameter ICC1 Added bank select read and read to write to read OE=low timing diagrams 128997 09/18/03 SPN Updated spec values for tOE, tOHZ, tCH2, tCL2, tHA, tHB, tHW, tHD, ICC, ISB5, tSA, tSB,tSW,tSD, tCD2 Updated read to write OE=low timing diagram Updated Master Reset values for tRS, tRSR, tRSF Updated pinout Updated VCORE voltage range 129936 09/30/03 SPN Updated package diagram Updated tCD2 value on first page Removed Preliminary status 233830 See ECN WWZ Added 4 Mbit and 9 Mbit x72 devices into the data sheet with updated pinout, pin description table, power table, and timing table Changed title Added Preliminary status to reflect the addition of 4 Mbit and 9 Mbit devices Removed FLEx72-E from the document Added Pb-Free Part Ordering Informations 360316 See ECN YDT Added note for VCORE Changed notes for PORTSTD to VSS Changed ICC, ISB1, ISB2 and ISB4 number for CYD09S72V per PE request 2898491 07/01/10 AJU Removed inactive parts from Ordering Information. Updated Packaging Information 3110296 12/14/2010 ADMU Updated Ordering Information. Added Ordering Code Definitions. 3265044 05/25/2011 ADMU Updates link to Application note. Removed obsolete part information. Notes updated across datasheet as per template. Added Acronyms and Units of measure table. 3402091 10/12/2011 ADMU Removed pruned part CYD18S72V-133BBC from Ordering Information Updated Package Diagram Page 29 of 30 CYD04S72V CYD09S72V CYD18S72V Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 \| PSoC 3 \| PSoC 5 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Page 30 of 30

PDF Datasheet Preview

CYD04S72V CYD09S72V CYD18S72V

FLEx72 V 64 K/128 K/256 K x 72 Synchronous Dual-Port RAM

Functional Description
• True dual-ported memory cells that allow simultaneous access of the same memory location
• Synchronous pipelined operation
• Family of 4 Mbit, 9 Mbit, and 18 Mbit devices
• Pipelined output mode allows fast operation
• 0.18-micron complmentary metal oxide semiconductor CMOS for optimum speed and power
• High-speed clock to data access
• V low power Active as low as 225 mA typ Standby as low as 55 mA typ
• Mailbox function for message passing
• Global master reset
• Separate byte enables on both ports
• Commercial and industrial temperature ranges
• IEEE 1149.1-compatible joint test action group JTAG boundary scan
• 484-ball fine-pitch ball grid array FBGA 1-mm pitch
• Pb-free packaging available
• Counter wrap around control Internal mask register controls counter wrap-around Counter-interrupt flags to indicate wrap-around Memory block retransmit operation
• Counter readback on address lines
• Mask register readback on address lines
• Dual chip enables on both ports for easy depth expansion
• Seamless migration to next generation dual-port family

The FLEx72 family includes 4 Mbit, 9 Mbit and 18 Mbit pipelined, synchronous, true dual-port static RAMs that are high-speed, low-power V CMOS. Two ports are provided, permitting independent, simultaneous access to any location in memory. The result of writing to the same location by more than one port at the same time is undefined. Registers on control, address, and data lines allow for minimal set-up and hold time.

During a Read operation, data is registered for decreased cycle time. Each port contains a burst counter on the input address register. After externally loading the counter with the initial address, the counter will increment the address internally more details to follow . The internal write pulse width is independent of the duration of the R/W input signal. The internal write pulse is self-timed to allow the shortest possible cycle times.

A HIGH on CE0 or LOW on CE1 for one clock cycle will power down the internal circuitry to reduce the static power consumption. One cycle with chip enables asserted is required to reactivate the outputs.

Additional features include readback of burst-counter internal address value on address lines, counter-mask registers to control the counter wrap-around, counter interrupt CNTINT flags, readback of mask register value on address lines, retransmit functionality, interrupt flags for message passing, JTAG for boundary scan, and asynchronous Master Reset MRST .

The CYD18S72V device have limited features. Please see Table 3 on page 8 for details.

Seamless Migration to Next-Generation Dual-Port Family

Cypress offers a migration path for all devices to the next-generation devices in the Dual-Port family with a compatible footprint. Please contact Cypress Sales for more details

Table Product Selection Guide

Density

Part number Max. speed MHz Max. access to data ns Typical operating current mA Package
4-Mbit 64K x 72

CYD04S72V
484-ball FBGA 23 mm x 23 mm
9-Mbit 128K x 72

CYD09S72V
484-ball FBGA 23 mm x 23 mm
18-Mbit 256K x 72

CYD18S72V
484-ball FBGA 23 mm x 23 mm
Maximum 13 Operating Range 13 Electrical Characteristics Over the Operating Range 13 Capacitance 14 AC Test Load and Waveforms 14 Switching Characteristics Over the Operating Range 14 JTAG Timing Characteristics 16 Switching Waveforms 16 Ordering Information 26
Ordering Code Definitions 26 Package Diagram 27 Acronyms 28 Document Conventions 28

Units of Measure 28 Document History Page 29 Sales, Solutions, and Legal Information 30

Worldwide Sales and Design Support 30 Products 30 PSoC Solutions 30

Page 3 of 30

CYD04S72V CYD09S72V CYD18S72V

Pin Configuration
484-ball BGA Top View

CYD04S72V/CYD09S72V/CYD18S72V
10 11 12 13 14 15 16 17 18 19
20 21 22

A NC DQ61L DQ59L DQ57L DQ54L DQ51L DQ48L DQ45L DQ42L DQ39L DQ36L DQ36R DQ39R DQ42R DQ45R DQ48R DQ51R DQ54R DQ57R DQ59R DQ61R NC

B DQ63L DQ62L DQ60L DQ58L DQ55L DQ52L DQ49L DQ46L DQ43L DQ40L DQ37L DQ37R DQ40R DQ43R DQ46R DQ49R DQ52R DQ55R DQ58R DQ60R DQ62R DQ63R

C DQ65L DQ64L VSS DQ56L DQ53L DQ50L DQ47L DQ44L DQ41L DQ38L DQ38R DQ41R DQ44R DQ47R DQ50R DQ53R DQ56R VSS DQ64R DQ65R

DQ67L DQ66L VSS D

NC [2, 5] NC [2, 5] VSS LOWSP PORTS NC [2, 5] BUSYL CNTINT PORTS

DL[2,4] TD0L
[2, 5]

L TD1L
[2,4]
[10]
[2, 4]

NC [2, 5] NC [2, 5]

VSS DQ66R DQ67R

DQ69L DQ68L VDDIOL VSS E

VSS VDDIOL VDDIO VDDIOL VTTL VDDIO VDDIOR NC

VSS VDDIOR DQ68R DQ69R

DQ71L DQ70L CE1L[8] CE0L [9] VDDIOL VDDIO VDDIOL VCORE VDDIO VDDIOR CE0R [9] CE1R[8] DQ70R DQ71R

G A0L

A1L RETL[2,3] BE4L VDDIOL VREFL VSS
[2, 4]

VSS VREFR VDDIOR BE4R RETR[2,3 A1R
[2, 4]

H A2L

A3L WRPL[2, BE5L VDDIOL VSS

VSS VDDIOR BE5R WRPR[2, A3R

J A4L

A5L READYL BE6L VDDIOL VSS
[2, 5]

VSS VDDIOR BE6R READYR A5R
[2, 5]

K A6L A7L NC[2,5] BE7L VTTL VCORE VSS VCORE VDDIOR BE7R NC[2,5] A7R A6R
Ordering Information

Speed MHz
Ordering Code

Package Name

Package Type

Operating Range
256K x 72 18-Mbit V Synchronous CYD18S72V Dual-Port SRAM

CYD18S72V-133BBI

BB484
484-ball Grid Array

Industrial
23 mm x 23 mm with 1.0-mm pitch FBGA

CYD18S72V-100BBC

BB484
484-ball Grid Array

Commercial
23 mm x 23 mm with 1.0-mm pitch FBGA

CYD18S72V-100BBI

BB484
484-ball Grid Array

Industrial
23 mm x 23 mm with 1.0-mm pitch FBGA
128K x 72 9-Mbit V Synchronous CYD09S72V Dual-Port SRAM

CYD09S72V-133BBC

BB484
484-ball Grid Array

Commercial
23 mm x 23 mm with 1.0-mm pitch FBGA
64K x 72 4-Mbit V Synchronous CYD04S72V Dual-Port SRAM

CYD04S72V-167BBC

BB484
484-ball Grid Array

Commercial
23 mm x 23 mm with 1.0-mm pitch FBGA
Ordering Code Definitions

CY D XX S 72 V - XXX BB X

Temperature Range X = C or I C = Commercial I = Industrial X = Pb-free RoHS Compliant Package Type BB = 484-ball BGA Speed Grade XXX = 100 MHz / 133 MHz / 167 MHz V = V 72 = Width x 72 S = Sync XX = Density 04 = 4 Mb 09 = 9 Mb 18 = 18 Mb D = Dual Port SRAM CY = Cypress Device

Page 26 of 30

Package Diagram

CYD04S72V CYD09S72V CYD18S72V
51-85124 *H

Page 27 of 30

Acronyms

Acronym CMOS FBGA JTAG OE RAM

Description Complementary metal oxide semiconductor fine-pitch ball grid array joint test action group Output enable Random access memory

Document Conventions

Units of Measure

Symbol °C MHz µA mA mV mW ns pF V W

Unit of Measure degree Celcius megahertz microamperes milliamperes millivolts milliwatts nanoseconds picofarad volts watts

CYD04S72V CYD09S72V CYD18S72V

Page 28 of 30

CYD04S72V CYD09S72V CYD18S72V

Document History Page

Document Title CYD04S72V / CYD09S72V / CYD18S72V FLEx72 V 64 K/128 K/256 K x 72 Synchronous Dual-Port RAM Document Number 38-06069

ECN NO. Issue Date

Orig. of Change

Description of Change
125859 06/17/03

SPN New Data Sheet
128707 08/01/03

SPN Added -133 speed bin

Updated spec values for ICC, tHA, tHB, tHW, tHD Added new parameter ICC1 Added bank select read and read to write to read OE=low timing diagrams
128997 09/18/03

SPN Updated spec values for tOE, tOHZ, tCH2, tCL2, tHA, tHB, tHW, tHD, ICC, ISB5, tSA,
tSB,tSW,tSD, tCD2

Updated read to write OE=low timing diagram

Updated Master Reset values for tRS, tRSR, tRSF Updated pinout Updated VCORE voltage range
129936 09/30/03

SPN Updated package diagram

Updated tCD2 value on first page Removed Preliminary status
233830 See ECN WWZ Added 4 Mbit and 9 Mbit x72 devices into the data sheet with updated pinout,
pin description table, power table, and timing table

Changed title

Added Preliminary status to reflect the addition of 4 Mbit and 9 Mbit devices

Removed FLEx72-E from the document
Added Pb-Free Part Ordering Informations
360316 See ECN

YDT Added note for VCORE

Changed notes for PORTSTD to VSS

Changed ICC, ISB1, ISB2 and ISB4 number for CYD09S72V per PE request
2898491 07/01/10
AJU Removed inactive parts from Ordering Information.

Updated Packaging Information
3110296 12/14/2010 ADMU Updated Ordering Information.
Added Ordering Code Definitions.
3265044 05/25/2011 ADMU Updates link to Application note.

Removed obsolete part information.

Notes updated across datasheet as per template.

Added Acronyms and Units of measure table.
3402091 10/12/2011 ADMU Removed pruned part CYD18S72V-133BBC from Ordering Information

Updated Package Diagram

Page 29 of 30

CYD04S72V CYD09S72V CYD18S72V

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products Automotive Clocks & Buffers Interface Lighting & Power Control

Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF
cypress.com/go/automotive cypress.com/go/clocks
cypress.com/go/interface cypress.com/go/powerpsoc
cypress.com/go/plc cypress.com/go/memory
cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB
cypress.com/go/wireless

PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Page 30 of 30

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Datasheet ID: CYD04S72V-167BBC 508191