CY8C5566AXI-061

CY8C5566AXI-061 Datasheet

5 CY8C55 Family Datasheet

Part	Datasheet
CY8C5566AXI-061	CY8C5566AXI-061 (pdf)

Related Parts	Information
CY8C5566LTI-017	CY8C5566LTI-017
CY8C5568LTI-114	CY8C5568LTI-114
CY8C5567AXI-019	CY8C5567AXI-019
CY8C5567LTI-079	CY8C5567LTI-079
CY8CKIT-010A	CY8CKIT-010A
CY8C5568AXI-060	CY8C5568AXI-060

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5 CY8C55 Family Datasheet Programmable System-on-Chip With its unique array of configurable blocks, 5 is a true system-level solution providing microcontroller unit MCU , memory, analog, and digital peripheral functions in a single chip. The CY8C55 family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples near DC voltages to ultrasonic signals. The CY8C55 family can handle dozens of data acquisition channels and analog inputs on every GPIO pin. The CY8C55 family is also a high-performance configurable digital system with some part numbers including interfaces such as USB, and multimaster I2C. In addition to communication interfaces, the CY8C55 family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance 32-bit Cortex -M3 microprocessor core. Designers can easily create system-level designs using a rich library of prebuilt components and boolean primitives using PSoC Creator , a hierarchical schematic design entry tool. The CY8C55 family provides unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates. • 32-bit ARM Cortex-M3 CPU core DC to 67 MHz operation Flash program memory, up to 256 KB, 100,000 write cycles, 20-year retention, and multiple security features Up to 64 KB SRAM memory 128 bytes of cache memory 2-KB electrically erasable programmable read-only EEPROM memory, 1 million cycles, and 20 years memory retention 24-channel direct memory access DMA with multilayer AMBA high-performance bus AHB bus access • Programmable chained descriptors and priorities • High bandwidth 32-bit transfer support • Low voltage, ultra low power Operating voltage range:2.7 V to V 6 mA at 6 MHz Low power modes including • 2-µA sleep mode • 300-nA hibernate mode with RAM retention • Versatile I/O system 46 to 70 I/Os 60 GPIOs, 8 SIOs, 2 USBIOs Any GPIO to any digital or analog peripheral routability LCD direct drive from any GPIO, up to 46x16 segments support from any GPIO[1] V to V I/O interface voltages, up to 4 domains Maskable, independent IRQ on any pin or port Schmitt-trigger transistor-transistor logic TTL inputs All GPIOs configurable as pull-up/pull-down, High-Z, open drain high/low, or strong output 25 mA sink on SIO • Digital peripherals 20 to 24 programmable logic device PLD based universal digital blocks UDBs Full-Speed FS USB 12 Mbps using a 24 MHz external oscillator Four 16-bit configurable timers, counters, and PWM blocks 67 MHz, 24-bit fixed point digital filter block DFB to implement finite impulse response FIR and infinite impulse response IIR filters Library of standard peripherals • 8-, 16-, 24-, and 32-bit timers, counters, and PWMs • SPI, UART, and I2C • Many others available in catalog Library of advanced peripherals • Cyclic redundancy check CRC • Pseudo random sequence PRS generator • Local interconnect network LIN bus Ordering Information 102 Part Numbering Conventions Packaging 104 Acronyms 106 Reference Documents 107 Document Conventions 108 Units of Measure Sales, Solutions, and Legal Information 111 Page 2 of 111 5 CY8C55 Family Datasheet Architectural Overview Introducing the CY8C55 family of ultra low power, flash Programmable System-on-Chip PSoC devices, part of a scalable 8-bit PSoC 3 and 32-bit PSoC 5 platform. The CY8C55 family provides configurable blocks of analog, digital, and interconnect circuitry around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables a high level of integration in a wide variety of consumer, industrial, and medical applications. Figure Simplified Block Diagram 4- 25 MHz Optional KHz Optiona l SIOs GPIOs GPIOs GPIOs System Wide Resources Xtal Osc RTC Timer WDT and Wake Clocking System Power Management System POR and LVD Sleep Power V LDO Clock Tree Usage Example for UDB Sequencer Digital Interconnect Analog Interconnect Digital System Universal Digital Block Array 24 x UDB 8- Bit Quadrature Decoder Timer 16- Bit PWM 16- Bit PRS UDB UDB I 2C Slave UDB 8- Bit SPI UDB UART UDB 12- Bit SPI UDB 8- Bit Timer Logic Logic UDB Ordering Information In addition to the features listed in Table 12-1, every CY8C55 device includes up to 256 KB flash, 64 KB SRAM, 2 KB EEPROM, a precision on-chip voltage reference, precision oscillators, flash, DMA, a fixed function I2C, SWD programming and debug, and more. In addition to these features, the flexible UDBs and analog subsection support a wide range of peripherals. To assist you in selecting the ideal part, PSoC Creator makes a part recommendation after you choose the components required by your application. All CY8C55 derivatives incorporate device and flash security in user-selectable security levels see the TRM for details. Table CY8C55 Family with ARM Cortex-M3 CPU MCU Core Analog Digital I/O[56] Package Device ID[57] 16-bit Timer/PWM Blocks[54] GPIO SIO USBIO Total I/O FS USB DFB CapSense UDBs[55] Opamps SC/CT Analog Comparators CPU Speed MHz Flash KB SRAM KB EEPROM KB LCD Segment Drive ADCs CY8C5568AXI-060 67 256 64 2 1x 20-bit Del-Sig 4 24 4 70 60 8 2 100-pin TQFP 0x0E13C069 2x 12-bit SAR CY8C5568LTI-114 67 256 64 2 1x 20-bit Del-Sig 4 24 4 46 36 8 2 68-pin QFN 0x0E172069 2x 12-bit SAR CY8C5567AXI-019 67 128 32 2 1x 20-bit Del-Sig 4 24 4 70 60 8 2 100-pin TQFP 0x0E113069 1x 12-bit SAR CY8C5567LTI-079 67 128 32 2 1x 20-bit Del-Sig 4 24 4 46 36 8 2 68-pin QFN 0x0E14F069 1x 12-bit SAR CY8C5566AXI-061 67 64 16 2 1x 20-bit Del-Sig 4 24 4 70 60 8 2 100-pin TQFP 0x0E13D069 1x 12-bit SAR CY8C5566LTI-017 67 64 16 2 1x20-bit Del-Sig 4 24 4 46 36 8 2 68-pin QFN 0x0E111069 1x12-bit SAR Part Numbering Conventions PSoC 5 devices follow the part numbering convention described here. All fields are single character alphanumeric 0, 1, 2, 9, A, B, Z unless stated otherwise. CY8Cabcdefg-xxx • a Architecture 3 PSoC 3 5 PSoC 5 • b Family group within architecture 2 CY8C52 family 3 CY8C53 family 4 CY8C54 family 5 CY8C55 family • c Speed grade 4 40 MHz 6 67 MHz • d Flash capacity 5 32 KB 6 64 KB 7 128 KB 8 256 KB • ef Package code Two character alphanumeric AX TQFP LT QFN • g Temperature range C commercial I industrial A automotive • xxx Peripheral set Three character numeric No meaning is associated with these three characters Notes Analog blocks support a wide variety of functionality including TIA, PGA, and mixers. See Example Peripherals on page 31 for more information on how analog blocks can be used. UDBs support a wide variety of functionality including SPI, LIN, UART, timer, counter, PWM, PRS, and others. Individual functions may use a fraction of a UDB or multiple UDBs. Multiple functions can share a single UDB. See Example Peripherals on page 31 for more information on how UDBs can be used. The I/O Count includes all types of digital I/O GPIO, SIO, and the two USB I/O. See I/O System and Routing on page 24 for details on the functionality of each of these types of I/O. The device ID has three major fields. The most significant nibble left digit is the version, followed by a 2 byte part number, and a 3 nibble manufacturer ID. Page 102 of 111

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5 CY8C55 Family Datasheet

Programmable System-on-Chip

With its unique array of configurable blocks, 5 is a true system-level solution providing microcontroller unit MCU , memory, analog, and digital peripheral functions in a single chip. The CY8C55 family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples near DC voltages to ultrasonic signals. The CY8C55 family can handle dozens of data acquisition channels and analog inputs on every GPIO pin. The CY8C55 family is also a high-performance configurable digital system with some part numbers including interfaces such as USB, and multimaster I2C. In addition to communication interfaces, the CY8C55 family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance 32-bit Cortex -M3 microprocessor core. Designers can easily create system-level designs using a rich library of prebuilt components and boolean primitives using PSoC Creator , a
hierarchical schematic design entry tool. The CY8C55 family provides unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates.
• 32-bit ARM Cortex-M3 CPU core

DC to 67 MHz operation Flash program memory, up to 256 KB, 100,000 write cycles,
20-year retention, and multiple security features

Up to 64 KB SRAM memory
128 bytes of cache memory
2-KB electrically erasable programmable read-only EEPROM memory, 1 million cycles, and 20 years
memory retention
24-channel direct memory access DMA with multilayer AMBA high-performance bus AHB bus access
• Programmable chained descriptors and priorities
• High bandwidth 32-bit transfer support
• Low voltage, ultra low power

Operating voltage range:2.7 V to V
6 mA at 6 MHz

Low power modes including
• 2-µA sleep mode
• 300-nA hibernate mode with RAM retention
• Versatile I/O system
46 to 70 I/Os 60 GPIOs, 8 SIOs, 2 USBIOs

Any GPIO to any digital or analog peripheral routability

LCD direct drive from any GPIO, up to 46x16 segments
support from any GPIO[1]

V to V I/O interface voltages, up to 4 domains

Maskable, independent IRQ on any pin or port

Schmitt-trigger transistor-transistor logic TTL inputs

All GPIOs configurable as pull-up/pull-down, High-Z,
open drain high/low, or strong output
25 mA sink on SIO
• Digital peripherals
20 to 24 programmable logic device PLD based universal digital blocks UDBs

Full-Speed FS USB 12 Mbps using a 24 MHz external oscillator

Four 16-bit configurable timers, counters, and PWM blocks
67 MHz, 24-bit fixed point digital filter block DFB to implement finite impulse response FIR and infinite impulse
response IIR filters

Library of standard peripherals
• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs
• SPI, UART, and I2C
• Many others available in catalog

Library of advanced peripherals
• Cyclic redundancy check CRC
• Pseudo random sequence PRS generator
• Local interconnect network LIN bus
Ordering Information 102 Part Numbering Conventions

Packaging 104

Acronyms 106

Reference Documents 107

Document Conventions 108 Units of Measure

Sales, Solutions, and Legal Information 111

Page 2 of 111
5 CY8C55 Family Datasheet

Architectural Overview

Introducing the CY8C55 family of ultra low power, flash Programmable System-on-Chip PSoC devices, part of a scalable 8-bit PSoC 3 and 32-bit PSoC 5 platform. The CY8C55 family provides configurable blocks of analog, digital, and interconnect circuitry around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables a high level of integration in a wide variety of consumer, industrial, and medical applications.

Figure Simplified Block Diagram
4- 25 MHz Optional

KHz Optiona l

SIOs

GPIOs

GPIOs

GPIOs

System Wide Resources

Xtal Osc

RTC Timer

WDT and Wake

Clocking System

Power Management System

POR and LVD Sleep Power

V LDO

Clock Tree Usage Example for UDB

Sequencer

Digital Interconnect

Analog Interconnect

Digital System

Universal Digital Block Array 24 x UDB
8- Bit Quadrature Decoder Timer
16- Bit PWM
16- Bit PRS UDB

UDB I 2C Slave

UDB 8- Bit SPI

UDB UART

UDB 12- Bit SPI

UDB 8- Bit Timer

Logic

Logic UDB
Ordering Information

In addition to the features listed in Table 12-1, every CY8C55 device includes up to 256 KB flash, 64 KB SRAM, 2 KB EEPROM, a precision on-chip voltage reference, precision oscillators, flash, DMA, a fixed function I2C, SWD programming and debug, and more. In addition to these features, the flexible UDBs and analog subsection support a wide range of peripherals. To assist you in selecting the ideal part, PSoC Creator makes a part recommendation after you choose the components required by your application. All CY8C55
derivatives incorporate device and flash security in user-selectable security levels see the TRM for details.

Table CY8C55 Family with ARM Cortex-M3 CPU

MCU Core

Analog

Digital

I/O[56]

Package

Device ID[57]
16-bit Timer/PWM

Blocks[54]

GPIO SIO USBIO

Total I/O

FS USB

DFB CapSense UDBs[55]

Opamps

SC/CT Analog

Comparators

CPU Speed MHz Flash KB SRAM KB EEPROM KB LCD Segment Drive

ADCs

CY8C5568AXI-060 67 256 64 2 1x 20-bit Del-Sig 4 24 4 70 60 8 2 100-pin TQFP 0x0E13C069 2x 12-bit SAR

CY8C5568LTI-114 67 256 64 2 1x 20-bit Del-Sig 4 24 4 46 36 8 2 68-pin QFN 0x0E172069 2x 12-bit SAR

CY8C5567AXI-019 67 128 32 2 1x 20-bit Del-Sig 4 24 4 70 60 8 2 100-pin TQFP 0x0E113069 1x 12-bit SAR

CY8C5567LTI-079 67 128 32 2 1x 20-bit Del-Sig 4 24 4 46 36 8 2 68-pin QFN 0x0E14F069 1x 12-bit SAR

CY8C5566AXI-061 67 64 16 2 1x 20-bit Del-Sig 4 24 4 70 60 8 2 100-pin TQFP 0x0E13D069 1x 12-bit SAR

CY8C5566LTI-017 67 64 16 2 1x20-bit Del-Sig 4 24 4 46 36 8 2 68-pin QFN 0x0E111069 1x12-bit SAR

Part Numbering Conventions PSoC 5 devices follow the part numbering convention described here. All fields are single character alphanumeric 0, 1, 2, 9, A, B, Z unless stated otherwise.

CY8Cabcdefg-xxx
• a Architecture 3 PSoC 3 5 PSoC 5
• b Family group within architecture 2 CY8C52 family 3 CY8C53 family 4 CY8C54 family 5 CY8C55 family
• c Speed grade 4 40 MHz 6 67 MHz
• d Flash capacity 5 32 KB 6 64 KB 7 128 KB 8 256 KB
• ef Package code Two character alphanumeric AX TQFP LT QFN
• g Temperature range C commercial I industrial A automotive
• xxx Peripheral set Three character numeric No meaning is associated with these three characters

Notes Analog blocks support a wide variety of functionality including TIA, PGA, and mixers. See Example Peripherals on page 31 for more information on how analog blocks
can be used. UDBs support a wide variety of functionality including SPI, LIN, UART, timer, counter, PWM, PRS, and others. Individual functions may use a fraction of a UDB or
multiple UDBs. Multiple functions can share a single UDB. See Example Peripherals on page 31 for more information on how UDBs can be used. The I/O Count includes all types of digital I/O GPIO, SIO, and the two USB I/O. See I/O System and Routing on page 24 for details on the functionality of each of
these types of I/O. The device ID has three major fields. The most significant nibble left digit is the version, followed by a 2 byte part number, and a 3 nibble manufacturer ID.

Page 102 of 111

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Datasheet ID: CY8C5566AXI-061 508171