CY7C21701KV18-400BZXC

CY7C21701KV18-400BZXC Datasheet

CY7C21701KV18

Part	Datasheet
CY7C21701KV18-400BZXC	CY7C21701KV18-400BZXC (pdf)

PDF Datasheet Preview
CY7C21701KV18 18-Mbit DDR II+ SRAM 2-Word Burst Architecture Cycle Read Latency with ODT • 18 Mbit Density 512K x 36 • 550 MHz Clock for High Bandwidth • 2-word Burst for reducing Address Bus Frequency • Double Data Rate DDR Interfaces data transferred at 1100 MHz at 550 MHz • Available in Clock Cycle Latency • Two Input Clocks K and K for precise DDR Timing SRAM uses rising edges only • Echo Clocks CQ and CQ simplify Data Capture in High Speed Systems • Data Valid Pin QVLD to indicate valid Data on the Output • On-Die Termination ODT feature Supported for D[x:0], BWS[x:0], and K/K inputs • Synchronous internally Self-timed Writes • DDR II+ operates with Cycle Read Latency when DOFF is asserted HIGH • Operates similar to DDR I Device with 1 Cycle Read Latency when DOFF is asserted LOW • Core VDD = 1.8V ± 0.1V I/O VDDQ = 1.4V to VDD[1] Supports both 1.5V and 1.8V I/O supply • HSTL Inputs and Variable Drive HSTL Output Buffers • Available in 165-Ball FBGA package 13 x 15 x mm • Offered in both Pb-free and non Pb-free packages • JTAG compatible Test Access Port • Phase-Locked Loop PLL for accurate Data Placement Configurations With Read Cycle Latency of cycles: CY7C21701KV18 512K x 36 Functional Description The CY7C21701KV18 are 1.8V Synchronous Pipelined SRAM equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input K clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of K and K. Each address location is associated with two 36-bit words that burst sequentially into or out of the device. These devices have an On-Die Termination feature supported for D[x:0], BWS[x:0], and K/K inputs, which helps eliminate external termination resistors, reduce cost, reduce board area, and simplify board routing. Asynchronous inputs include an output impedance matching input ZQ . Synchronous data outputs Q, sharing the same physical pins as the data inputs D are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately capturing data from each individual DDR SRAM in the system design. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. This device is down bonded from the 65 nm 72M QDRII device and hence have the same IDD/ISB1 values and JTAG ID code as the equivalent 72M device option. For details refer to the application note AN53189, 65 nm Technology Interim QDRII/DDRII SRAM device family description. Table Selection Guide Description Maximum Operating Frequency Maximum Operating Current 550 MHz 500 MHz 500 690 700 890 450 MHz 450 630 650 820 400 MHz 400 580 590 750 Unit MHz mA Note The Cypress QDR-II+ devices surpass the QDR consortium specification and can support VDDQ = 1.4V to VDD. • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback Logic Block Diagram CY7C21701KV18 CY7C21701KV18 Power Up Sequence 17 PLL 17 Maximum 18 Operating 18 Neutron Soft Error Immunity 18 Electrical 18 DC Electrical 18 AC Electrical Characteristics 19 Capacitance 20 Thermal 20 Switching 21 Switching Waveforms 22 Read/Write/Deselect Sequence 22 Ordering 23 Package 23 Document History Page 24 Sales, Solutions, and Legal Information 24 Worldwide Sales and Design Support....................... 24 Products 24 PSoC Solutions 24 Page 3 of 24 [+] Feedback CY7C21701KV18 Pin Configuration The pin configuration for CY7C21701KV18 follows. [2] 165-Ball FBGA 13 x 15 x mm Pinout CY7C21701KV18 512K x 36 CQ NC/144M NC/36M R/W BWS2 BWS1 DQ27 DQ18 BWS3 BWS0 DQ28 DQ29 DQ19 DQ20 VDDQ VDDQ DQ30 DQ21 VDDQ VDDQ DQ31 DQ22 VDDQ VDDQ DOFF VREF VDDQ VDDQ VDDQ DQ32 VDDQ VDDQ DQ23 VDDQ VDDQ DQ33 DQ24 VDDQ VDDQ DQ34 DQ35 DQ25 DQ26 QVLD 9 A NC VDDQ NC A 10 NC/72M Ordering Information The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at and refer to the product summary page at Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at Table Ordering Information Speed MHz Ordering Code 400 CY7C21701KV18-400BZXC Package Diagram Package Type Operating Range 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free Commercial Package Diagram Figure 165-Ball FBGA 13 x 15 x mm TOP VIEW PIN 1 CORNER 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P R SEATING PLANE C MAX. C BOTTOM VIEW PIN 1 CORNER M C M C A B 165X 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R 0.15 4X NOTES : SOLDER PAD TYPE NON-SOLDER MASK DEFINED NSMD PACKAGE WEIGHT 0.475g JEDEC REFERENCE MO-216 / ISSUE E PACKAGE CODE BB0AC 51-85180-C Page 23 of 24 [+] Feedback CY7C21701KV18 Document History Page Document Title CY7C21701KV18, 18-Mbit DDR II+ SRAM 2-Word Burst Architecture Cycle Read Latency with ODT Document Number 001-57344 Orig. of Change Submission Date Description of Change * 2798874 VKN/AESA 11/04/09 New data sheet *A 2888780 03/08/2010 Post to external web Updated package diagram Updated links in Sales, Solutions, and Legal Information Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory

PDF Datasheet Preview

CY7C21701KV18
18-Mbit DDR II+ SRAM 2-Word Burst Architecture Cycle Read Latency with ODT
• 18 Mbit Density 512K x 36
• 550 MHz Clock for High Bandwidth
• 2-word Burst for reducing Address Bus Frequency
• Double Data Rate DDR Interfaces data transferred at 1100 MHz at 550 MHz
• Available in Clock Cycle Latency
• Two Input Clocks K and K for precise DDR Timing SRAM uses rising edges only
• Echo Clocks CQ and CQ simplify Data Capture in High Speed Systems
• Data Valid Pin QVLD to indicate valid Data on the Output
• On-Die Termination ODT feature Supported for D[x:0], BWS[x:0], and K/K inputs
• Synchronous internally Self-timed Writes
• DDR II+ operates with Cycle Read Latency when DOFF is asserted HIGH
• Operates similar to DDR I Device with 1 Cycle Read Latency when DOFF is asserted LOW
• Core VDD = 1.8V ± 0.1V I/O VDDQ = 1.4V to VDD[1] Supports both 1.5V and 1.8V I/O supply
• HSTL Inputs and Variable Drive HSTL Output Buffers
• Available in 165-Ball FBGA package 13 x 15 x mm
• Offered in both Pb-free and non Pb-free packages
• JTAG compatible Test Access Port
• Phase-Locked Loop PLL for accurate Data Placement

Configurations

With Read Cycle Latency of cycles:

CY7C21701KV18 512K x 36

Functional Description

The CY7C21701KV18 are 1.8V Synchronous Pipelined SRAM equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input K clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of K and K. Each address location is associated with two 36-bit words that burst sequentially into or out of the device.

These devices have an On-Die Termination feature supported for D[x:0], BWS[x:0], and K/K inputs, which helps eliminate external termination resistors, reduce cost, reduce board area, and simplify board routing.

Asynchronous inputs include an output impedance matching input ZQ . Synchronous data outputs Q, sharing the same physical pins as the data inputs D are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately capturing data from each individual DDR SRAM in the system design.

All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

This device is down bonded from the 65 nm 72M QDRII device and hence have the same IDD/ISB1 values and JTAG ID code as the equivalent 72M device option. For details refer to the application note AN53189, 65 nm Technology Interim QDRII/DDRII SRAM device family description.

Table Selection Guide Description

Maximum Operating Frequency Maximum Operating Current
550 MHz
500 MHz 500 690 700 890
450 MHz 450 630 650 820
400 MHz 400 580 590 750

Unit MHz mA

Note The Cypress QDR-II+ devices surpass the QDR consortium specification and can support VDDQ = 1.4V to VDD.
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

Logic Block Diagram CY7C21701KV18

CY7C21701KV18
Power Up Sequence 17 PLL 17 Maximum 18 Operating 18 Neutron Soft Error Immunity 18 Electrical 18 DC Electrical 18 AC Electrical Characteristics 19 Capacitance 20 Thermal 20 Switching 21 Switching Waveforms 22 Read/Write/Deselect Sequence 22 Ordering 23 Package 23 Document History Page 24 Sales, Solutions, and Legal Information 24 Worldwide Sales and Design Support....................... 24 Products 24 PSoC Solutions 24

Page 3 of 24 [+] Feedback

CY7C21701KV18

Pin Configuration

The pin configuration for CY7C21701KV18 follows. [2]
165-Ball FBGA 13 x 15 x mm Pinout

CY7C21701KV18 512K x 36

CQ NC/144M NC/36M R/W

BWS2

BWS1

DQ27 DQ18

BWS3

BWS0

DQ28

DQ29 DQ19

DQ20

VDDQ

VDDQ

DQ30 DQ21 VDDQ

VDDQ

DQ31 DQ22 VDDQ

VDDQ

DOFF

VREF

VDDQ

VDDQ

VDDQ

DQ32

VDDQ

VDDQ

DQ23

VDDQ

VDDQ

DQ33 DQ24 VDDQ

VDDQ

DQ34

DQ35 DQ25

DQ26

QVLD
9 A NC VDDQ NC A
10 NC/72M
Ordering Information

The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at and refer to the product summary page at

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at
Table Ordering Information

Speed MHz
Ordering Code
400 CY7C21701KV18-400BZXC

Package Diagram

Package Type

Operating Range
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free Commercial

Package Diagram

Figure 165-Ball FBGA 13 x 15 x mm

TOP VIEW

PIN 1 CORNER
1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P R

SEATING PLANE C

MAX. C

BOTTOM VIEW

PIN 1 CORNER

M C M C A B
165X
11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R
0.15 4X

NOTES :

SOLDER PAD TYPE NON-SOLDER MASK DEFINED NSMD PACKAGE WEIGHT 0.475g JEDEC REFERENCE MO-216 / ISSUE E PACKAGE CODE BB0AC
51-85180-*C

Page 23 of 24 [+] Feedback

CY7C21701KV18

Document History Page

Document Title CY7C21701KV18, 18-Mbit DDR II+ SRAM 2-Word Burst Architecture Cycle Read Latency with ODT Document Number 001-57344

Orig. of Change

Submission Date

Description of Change
** 2798874 VKN/AESA
11/04/09 New data sheet
*A 2888780
03/08/2010 Post to external web Updated package diagram Updated links in Sales, Solutions, and Legal Information

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products Automotive Clocks & Buffers Interface Lighting & Power Control

Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF
cypress.com/go/automotive cypress.com/go/clocks
cypress.com/go/interface cypress.com/go/powerpsoc
cypress.com/go/plc cypress.com/go/memory

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C21701KV18-400BZXC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C21701KV18-400BZXC 508087