CY7C1081DV33-12BAXI

CY7C1081DV33-12BAXI Datasheet

CY7C1081DV33

Part	Datasheet
CY7C1081DV33-12BAXI	CY7C1081DV33-12BAXI (pdf)

PDF Datasheet Preview
CY7C1081DV33 64-Mbit 4 M x 16 Static RAM • High speed tAA = 12 ns • Low active power ICC = 300 mA at 12 ns • Low complementary metal oxide semiconductor CMOS standby power ISB2 = 100 mA • Operating voltages of ± V • 2.0-V data retention • Automatic power-down when deselected • Transistor-transistor logic TTL -compatible inputs and outputs • Easy memory expansion with CE1 and CE2 features • Available in Pb-free 48-ball fine ball grid array FBGA package Functional Description The CY7C1081DV33 is a high-performance CMOS static RAM organized as 4,194,304 words by 16 bits. To write to the device, take Chip Enables CE1 LOW and CE2 HIGH and Write Enable WE inputs LOW. If Byte Low Enable BLE is LOW, then data from I/O pins I/O0 through I/O7 is written into the location specified on the address pins A0 through A21 . If Byte High Enable BHE is LOW, then data from I/O pins I/O8 through I/O15 is written into the location specified on the address pins A0 through A21 . To read from the device, take Chip Enables CE1 LOW and CE2 HIGH and Output Enable OE LOW while forcing the Write Enable WE HIGH. If Byte Low Enable BLE is LOW, then data from the memory location specified by the address pins appears on I/O0 to I/O7. If Byte High Enable BHE is LOW, then data from memory appears on I/O8 to I/O15. See the Truth Table on page 9 for a complete description of read and write modes. The input and output pins I/O0 through I/O15 are placed in a high impedance state when the device is deselected CE1HIGH or CE2 LOW , the outputs are disabled OE HIGH , both byte high enable and byte low enable are disabled BHE, BLE HIGH , or during a write operation CE1 LOW, CE2 HIGH, and WE LOW . Logic Block Diagram DATAIN DRIVERS ROW DECODER SENSE AMPS A 10:0 4M x 16 RAM ARRAY COLUMN DECODER A 21:11 • San Jose, CA 95134-1709 • 408-943-2600 CY7C1081DV33 Contents Selection Guide 3 Pin Configuration 3 Maximum Ratings 4 Operating Range 4 DC Electrical Characteristics 4 Capacitance 4 Thermal Resistance 4 Data Retention Characteristics 5 AC Switching Characteristics 6 Switching Waveforms 7 Truth Table 9 Ordering Information 10 Ordering Code Definition 10 Package Diagram 11 Acronyms 11 Document Conventions 11 Units of Measure 11 Document History Page 12 Sales, Solutions, and Legal Information 12 Worldwide Sales and Design Support 12 Products 12 PSoC Solutions 12 Page 2 of 12 Selection Guide Description Maximum access time Maximum operating current Maximum CMOS standby current Pin Configuration 12 300 100 Figure 48-Ball FBGA Top View 1 2 34 56 BLE OE A0 A1 A2 CE2 A I/O8 BHE A3 A4 CE1 I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 A17 A7 I/O3 VCC VCC I/O12 A21 A16 I/O4 VSS I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 A20 A12 A13 WE I/O7 G A18 A8 A9 A10 A11 A19 CY7C1081DV33 Unit ns mA Page 3 of 12 CY7C1081DV33 Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Storage temperature C to +150 C Ambient temperature with power applied C to +125 C Supply voltage on VCC relative to GND V to V DC voltage applied to outputs in high-Z V to VCC + V DC input voltage[1] V to VCC + V Current into outputs LOW 20 mA Static discharge voltage............. V MIL-STD-883, Method 3015 Latch-up current >140 mA Operating Range Range Industrial Ambient Temperature °C to +85 °C VCC V  V Speed 12 ns DC Electrical Characteristics Over the Operating Range Parameter Test Conditions Output HIGH voltage VCC = Min, IOH = mA Output LOW voltage Ordering Information Speed ns Ordering Code 12 CY7C1081DV33-12BAXI Ordering Code Definition Package Diagram 001-50044 Package Type 48-Ball FBGA 8 x mm Pb-free CY 7 C 1 08 1 D V33 - xx xxx x Operating Range Industrial Temperature Range x = I = Industrial Package Type xxx = BAX = 48-ball FBGA Pb-free Speed xx = 12 ns V33 = Voltage range 3 V to V D = C9, 90 nm Technology 1 = Data width x 16 bits 08 = 64-Mbit density 1 = Fast Asynchronous SRAM family Technology Code C = CMOS 7 = SRAM CY = Cypress Page 10 of 12 Package Diagram CY7C1081DV33 Figure 48-Ball FBGA 8 x mm 001-50044 001-50044 *C Acronyms Acronym CMOS FBGA I/O SRAM TTL Description complementary metal oxide semiconductor fine ball grid array input/output static random access memory transistor-transistor logic Document Conventions Units of Measure Symbol °C mA MHz ns pF V W Unit of Measure degrees Celsius microampere milliampere megahertz nanosecond picofarad volt ohm watt Page 11 of 12 CY7C1081DV33 Document History Page Document Title CY7C1081DV33, 64-Mbit 4 M x 16 Static RAM Document Number 001-53992 Submission Date Orig. of Change Description of Change 2746867 07/31/2009 VKN/AESA New datasheet 3100499 12/02/2010 PRAS Updated Note Changed datasheet status from Preliminary to Final. Updated Package Diagram and Sales, Solutions, and Legal Information. Added Acronyms, Document Conventions and Ordering Code Definition. 3178249 21/02/2011 PRAS Post to external web 3246293 05/04/2011 PRAS Modified Figure 44-B all FBGA pin configuration. 3720094 08/22/2012 TAVA Minor Text edits. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 \| PSoC 3 \| PSoC 5 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. All products and company names mentioned in this document may be the trademarks of their respective holders. Page 12 of 12

PDF Datasheet Preview

CY7C1081DV33
64-Mbit 4 M x 16 Static RAM
• High speed tAA = 12 ns
• Low active power ICC = 300 mA at 12 ns
• Low complementary metal oxide semiconductor CMOS standby power ISB2 = 100 mA
• Operating voltages of ± V
• 2.0-V data retention
• Automatic power-down when deselected
• Transistor-transistor logic TTL -compatible inputs and outputs
• Easy memory expansion with CE1 and CE2 features
• Available in Pb-free 48-ball fine ball grid array FBGA package

Functional Description

The CY7C1081DV33 is a high-performance CMOS static RAM organized as 4,194,304 words by 16 bits.

To write to the device, take Chip Enables CE1 LOW and CE2 HIGH and Write Enable WE inputs LOW. If Byte Low Enable BLE is LOW, then data from I/O pins I/O0 through I/O7 is written into the location specified on the address pins A0 through A21 . If Byte High Enable BHE is LOW, then data from I/O pins I/O8 through I/O15 is written into the location specified on the address pins A0 through A21 . To read from the device, take Chip Enables CE1 LOW and CE2 HIGH and Output Enable OE LOW while forcing the Write Enable WE HIGH. If Byte Low Enable BLE is LOW, then data from the memory location specified by the address pins appears on I/O0 to I/O7. If Byte High Enable BHE is LOW, then data from memory appears on I/O8 to I/O15. See the Truth Table on page 9 for a complete description of read and write modes.

The input and output pins I/O0 through I/O15 are placed in a high impedance state when the device is deselected CE1HIGH or CE2 LOW , the outputs are disabled OE HIGH , both byte high enable and byte low enable are disabled BHE, BLE HIGH , or during a write operation CE1 LOW, CE2 HIGH, and WE LOW .

Logic Block Diagram

DATAIN DRIVERS

ROW DECODER SENSE AMPS

A 10:0
4M x 16 RAM ARRAY

COLUMN DECODER A 21:11
• San Jose, CA 95134-1709
• 408-943-2600

CY7C1081DV33

Contents

Selection Guide 3 Pin Configuration 3 Maximum Ratings 4 Operating Range 4 DC Electrical Characteristics 4 Capacitance 4 Thermal Resistance 4 Data Retention Characteristics 5 AC Switching Characteristics 6 Switching Waveforms 7 Truth Table 9
Ordering Information 10 Ordering Code Definition 10

Package Diagram 11 Acronyms 11 Document Conventions 11

Units of Measure 11 Document History Page 12 Sales, Solutions, and Legal Information 12

Worldwide Sales and Design Support 12 Products 12 PSoC Solutions 12

Page 2 of 12

Selection Guide

Description Maximum access time Maximum operating current Maximum CMOS standby current

Pin Configuration
12 300 100

Figure 48-Ball FBGA Top View
1 2 34 56

BLE OE A0 A1 A2 CE2 A

I/O8 BHE A3 A4 CE1 I/O0 B

I/O9 I/O10 A5 A6 I/O1 I/O2 C

VSS I/O11 A17 A7 I/O3 VCC

VCC I/O12 A21 A16 I/O4 VSS

I/O14 I/O13 A14 A15 I/O5 I/O6 F

I/O15 A20 A12 A13 WE I/O7 G

A18 A8 A9 A10 A11 A19

CY7C1081DV33

Unit ns mA

Page 3 of 12

CY7C1081DV33

Maximum Ratings

Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested.

Storage temperature C to +150 C

Ambient temperature with power applied C to +125 C Supply voltage on VCC relative to GND V to V DC voltage applied to outputs in high-Z V to VCC + V DC input voltage[1] V to VCC + V

Current into outputs LOW 20 mA Static discharge voltage............. V MIL-STD-883, Method 3015 Latch-up current >140 mA

Operating Range

Range Industrial

Ambient Temperature
°C to +85 °C

VCC V  V

Speed 12 ns

DC Electrical Characteristics

Over the Operating Range

Parameter

Test Conditions

Output HIGH voltage

VCC = Min, IOH = mA

Output LOW voltage
Ordering Information

Speed ns
Ordering Code
12 CY7C1081DV33-12BAXI
Ordering Code Definition

Package Diagram
001-50044

Package Type 48-Ball FBGA 8 x mm Pb-free

CY 7 C 1 08 1 D V33 - xx xxx x

Operating Range Industrial

Temperature Range x = I = Industrial Package Type xxx = BAX = 48-ball FBGA Pb-free Speed xx = 12 ns V33 = Voltage range 3 V to V D = C9, 90 nm Technology 1 = Data width x 16 bits 08 = 64-Mbit density 1 = Fast Asynchronous SRAM family Technology Code C = CMOS 7 = SRAM CY = Cypress

Page 10 of 12

Package Diagram

CY7C1081DV33

Figure 48-Ball FBGA 8 x mm 001-50044
001-50044 *C

Acronyms

Acronym CMOS FBGA I/O SRAM TTL

Description complementary metal oxide semiconductor fine ball grid array input/output static random access memory transistor-transistor logic

Document Conventions

Units of Measure

Symbol °C mA MHz ns pF V W

Unit of Measure degrees Celsius microampere milliampere megahertz nanosecond picofarad volt ohm watt

Page 11 of 12

CY7C1081DV33

Document History Page

Document Title CY7C1081DV33, 64-Mbit 4 M x 16 Static RAM Document Number 001-53992

Submission Date

Orig. of Change

Description of Change
2746867 07/31/2009 VKN/AESA New datasheet
3100499 12/02/2010

PRAS
Updated Note Changed datasheet status from Preliminary to Final. Updated Package Diagram and Sales, Solutions, and Legal Information. Added Acronyms, Document Conventions and Ordering Code Definition.
3178249 21/02/2011

PRAS Post to external web
3246293 05/04/2011

PRAS Modified Figure 44-B all FBGA pin configuration.
3720094 08/22/2012

TAVA Minor Text edits.

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products Automotive Clocks & Buffers Interface Lighting & Power Control

Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF
cypress.com/go/automotive cypress.com/go/clocks
cypress.com/go/interface cypress.com/go/powerpsoc
cypress.com/go/plc cypress.com/go/memory
cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB
cypress.com/go/wireless

PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

All products and company names mentioned in this document may be the trademarks of their respective holders.

Page 12 of 12

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Datasheet ID: CY7C1081DV33-12BAXI 507919