CY7C026A-15AXC

CY7C026A-15AXC Datasheet


CY7C026A/026B CY7C036A16K x 16/18 Dual-Port Static RAM

Part Datasheet
CY7C026A-15AXC CY7C026A-15AXC CY7C026A-15AXC (pdf)
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CY7C026A/026B CY7C036A16K x 16/18 Dual-Port Static RAM

CY7C026A/026B CY7C036A
16K x 16/18 Dual-Port Static RAM
• True dual-ported memory cells that allow simultaneous access of the same memory location
• 16K x 16 organization CY7C026A/026B[1]
• 16K x 18 organization CY7C036A
• micron CMOS for optimum speed and power
• High speed access 12[2], 15, and 20 ns
• Low operating power
• Active ICC = 180 mA typical
• Standby ISB3 = mA typical
• Fully asynchronous operation

Logic Block Diagram

R/WL UBL
• Automatic power down
• Expandable data bus to 32/36 bits or more using Master/Slave
chip select when using more than one device
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• INT flags for port-to-port communication
• Separate upper-byte and lower-byte control
• Pin select for Master or Slave
• Commercial and Industrial temperature ranges
• Available in 100-Pin TQFP
• Pb-free packages available

R/WR UBR

LBL OEL
/17L

I/O Control

I/O Control

LBR OER

Address

Decode

True Dual-Ported RAM Array

CEL OEL

R/WL SEML BUSYL [5] INTL UBL LBL

Notes CY7C026A and CY7C026B are functionally identical. See page 6 for Load Conditions. for x16 devices for x18 devices. for x16 devices for x18 devices. BUSY is an output in master mode and an input in slave mode.

Interrupt Semaphore Arbitration

Address

Decode

CER OER

R/WR SEMR [5] BUSYR

INTR UBR LBR
• San Jose, CA 95134-1709
• 408-943-2600
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Pin Configurations

Figure 100-Pin TQFP Top View

CY7C026A/026B CY7C036A

I/O9L I/O8L I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L GND I/O1L I/O0L OEL VCC R/WL SEML CEL UBL LBL A13L A12L A11L A10L A9L A8L A7L

NC I/O10L I/O11L I/O12L I/O13L GND I/O14L I/O15L

VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

CY7C026A/026B 16K x 16
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

NC A6L A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R A5R NC

I/O7R I/O8R I/O9R I/O10R I/O11R I/O12R I/O13R I/O14R GND I/O15R OER R/WR GND SEMR CER UBR
Ordering Information
16K x16 Asynchronous Dual-Port SRAM

Speed ns 12[2] 15
Ordering Code CY7C026A-12AC CY7C026A-15AC CY7C026A-15AXC CY7C026B-15AI CY7C026A-15AXI CY7C026A-20AC CY7C026A-20AXC

Package Name A100

Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack

Speed ns 12[2] 15
Ordering Code CY7C036A-12AC CY7C036A-15AC CY7C036A-15AI CY7C036A-20AC

Package Name A100

Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack

Package Diagram

Figure 100-Pin Pb-Free Thin Plastic Quad Flat Pack TQFP A100

Operating Range

Commercial

Industrial

Commercial

Operating Range

Commercial Industrial Commercial
51-85048-*C

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CY7C026A/026B CY7C036A

Document History Page

Document Title CY7C026A/026B, CY7C036A 16K X 16/18 Dual-Port Static RAM Document Number 38-06046

ECN No.

Orig. of Submission

Change

Description of Change
110198
09/29/01 Change from Spec number 38-00832 to 38-06046
122296
12/27/02 Power up requirements added to Maximum Ratings Information
237621

See ECN Removed cross information from features section
393454

See ECN Added Pb-Free Logo
Added Pb-Free parts to ordering information:

CY7C026A-15AXC, CY7C026A-20AXC
2623540 VKN/PYRS 12/17/08 Added CY7C026B part
Added CY7C026A-15AXI part in the Ordering Information table

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.

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CAN 2.0b
psoc.cypress.com/can
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Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

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Datasheet ID: CY7C026A-15AXC 507877