CGS3322M

CGS3322M Datasheet

CGS3321<br>• CGS3322 CMOS Crystal Clock Generators

Part	Datasheet
CGS3322M	CGS3322M (pdf)

Related Parts	Information
CGS3321M	CGS3321M
CGS3321MX	CGS3321MX
CGS3322MX	CGS3322MX

PDF Datasheet Preview
CGS3321 • CGS3322 CMOS Crystal Clock Generators CGS3321 • CGS3322 CMOS Crystal Clock Generators The CGS3321 and CGS3322 devices are designed for Clock Generation and Support CGS applications up to 110 MHz. The CGS332x series of devices are crystal controlled CMOS oscillators requiring a minimum of external components. The 332x devices provide selectable output divide ratio. The circuit is designed to operate over a wide frequency range using fundamental mode or overtone crystals. s Fairchild’s CGS family of devices for high frequency clock source applications s Crystal frequency operation range fundamental 10 MHz to 100 MHz typical 3rd or 5th overtone 10 MHz to 95 MHz s 1000V ESD protection on OCS_IN and OSC_OUT pins. 2000V ESD protection on all other pins s Output current drive of 48 mA for IOL/IOH s CMOS output levels s Output has high speed short circuit protection s Intended for Pierce oscillator applications s Hysteresis inputs to improve noise margin s CGS3321 has duty cycle adjust s CGS3322 has 1, 2, 4 divide ratio Ordering Code: Order Number Package Number Package Description CGS3321M M08A 8-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow CGS3322M M08A 8-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams CGS3321 Truth Table Division Selection DIVB F 1 0 OEH X 1 Divider Output Divide-by 1 Divide-by 2 Divide-by 4 Note Actual value of the floating DIVB input is VCC/2 CGS3322 is a trademark of Fairchild Semiconductor Corporation. 2001 Fairchild Semiconductor Corporation DS011503 CGS3321 • CGS3322 Pin Descriptions Note Pin out varies for each device. OSC_IN Input to Oscillator Inverter. The output of the crystal would be connected here. OSC_OUT Resistive Buffered Output of the Oscillator Inverter DIVB CGS3322 only 3-Level input used to select Binary Divide-by value of output frequency. DC_ADJ CGS3321 only Active high input that controls output duty cycle. Logic high level will delay the HL transition edge approximately ns. OUT OSCLO_1 VCC GND Note Pin out varies for each device. Block Diagrams Active HIGH 3-STATE enable pin. This pin pulls to a HIGH value when left floating and 3STATEs the output when forced LOW. This pin has TTL compatible input levels. This pin is the main clock output on the device. The Oscillator LOW pin is the ground for the Oscillator. The power pin for the chip. The ground pin for all sections of the circuitry except the oscillator and oscillator related circuitry. Note Pin numbers vary for each device CGS3321 • CGS3322 Block Diagrams Continued Oscillator Stage Output Stage CGS3321 • CGS3322 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Voltage Diode Current IIK DC Input Voltage VI DC Output Diode Current IOK DC Output Voltage VO DC Output Source or Sink Current IO Storage Temperature TSTG Junction Temperature TJ SOIC −0.5V to 7.0V ±9 mA −0.5V to 7.0V ±20 mA -0.5V to VCC + 0.5V ±70 mA −55°C to 150°C

PDF Datasheet Preview

CGS3321
• CGS3322 CMOS Crystal Clock Generators

CGS3321
• CGS3322 CMOS Crystal Clock Generators

The CGS3321 and CGS3322 devices are designed for Clock Generation and Support CGS applications up to 110 MHz. The CGS332x series of devices are crystal controlled CMOS oscillators requiring a minimum of external components. The 332x devices provide selectable output divide ratio. The circuit is designed to operate over a wide frequency range using fundamental mode or overtone crystals.
s Fairchild’s CGS family of devices for high frequency clock source applications
s Crystal frequency operation range fundamental 10 MHz to 100 MHz typical 3rd or 5th overtone 10 MHz to 95 MHz
s 1000V ESD protection on OCS_IN and OSC_OUT pins. 2000V ESD protection on all other pins
s Output current drive of 48 mA for IOL/IOH s CMOS output levels s Output has high speed short circuit protection s Intended for Pierce oscillator applications s Hysteresis inputs to improve noise margin s CGS3321 has duty cycle adjust s CGS3322 has 1, 2, 4 divide ratio
Ordering Code:

Order Number Package Number

Package Description

CGS3321M

M08A
8-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow

CGS3322M

M08A
8-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagrams

CGS3321

Truth Table

Division Selection

DIVB F 1 0

OEH X 1

Divider Output Divide-by 1 Divide-by 2 Divide-by 4

Note Actual value of the floating DIVB input is VCC/2

CGS3322
is a trademark of Fairchild Semiconductor Corporation.
2001 Fairchild Semiconductor Corporation DS011503

CGS3321
• CGS3322

Pin Descriptions

Note Pin out varies for each device.

OSC_IN Input to Oscillator Inverter. The output of the crystal would be connected here.

OSC_OUT Resistive Buffered Output of the Oscillator Inverter

DIVB

CGS3322 only 3-Level input used to select Binary Divide-by value of output frequency.

DC_ADJ

CGS3321 only Active high input that controls output duty cycle. Logic high level will delay the HL transition edge approximately ns.

OUT OSCLO_1

VCC GND

Note Pin out varies for each device.

Block Diagrams

Active HIGH 3-STATE enable pin. This pin pulls to a HIGH value when left floating and 3STATEs the output when forced LOW. This pin has TTL compatible input levels. This pin is the main clock output on the device.

The Oscillator LOW pin is the ground for the Oscillator.

The power pin for the chip. The ground pin for all sections of the circuitry except the oscillator and oscillator related circuitry.

Note Pin numbers vary for each device

CGS3321
• CGS3322

Block Diagrams Continued

Oscillator Stage Output Stage

CGS3321
• CGS3322

Absolute Maximum Ratings Note 1

Supply Voltage VCC DC Input Voltage Diode Current IIK DC Input Voltage VI DC Output Diode Current IOK DC Output Voltage VO DC Output Source
or Sink Current IO Storage Temperature TSTG Junction Temperature TJ

SOIC
−0.5V to 7.0V ±9 mA
−0.5V to 7.0V ±20 mA
-0.5V to VCC + 0.5V
±70 mA −55°C to 150°C

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Datasheet ID: CGS3322M 513590