CS493105-CLZR

CS493105-CLZR Datasheet

CS49300 Family DSP

Part	Datasheet
CS493105-CLZR	CS493105-CLZR (pdf)

Related Parts	Information
CS493105-CLZ	CS493105-CLZ

PDF Datasheet Preview
CS49300 Family DSP Multi-Standard Audio Decoder Family z CS4930X DVD Audio Sub-family PES Layer decode for A/V sync DVD Audio Pack Layer Support Meridian Lossless Packing Specification MLP Dolby Digital , Dolby Pro Logic II MPEG-2, Advanced Audio Coding Algorithm AAC MPEG Multichannel DTS Digital Surround , DTS-ES Extended Surround z CS4931X Broadcast Sub-family PES Layer decode for A/V sync Dolby Digital MPEG-2, Advanced Audio Coding Algorithm AAC MPEG-1 Layers 1, 2, 3 Stereo MPEG-2 Layers 2, 3 Stereo z CS4932X AVR Sub-family Dolby Digital, Dolby Pro Logic II DTS & DTS-ES decoding with integrated DTS tables Cirrus Original Surround PCM Enhancement MPEG-2, Advanced Audio Coding Algorithm AAC MPEG Multichannel MP3 MPEG-1, Layer 3 z CS49330 General Purpose Audio DSP Surround EX and Ultra2 Cinema General Purpose AVR and Broadcast Audio Decoder MPEG Multichannel, MPEG Stereo, MP3, C.O.S. Car Audio z Features are a super-set of the CS4923/4/5/6/7/8/9 8 channel output, including dual zone output capability Dynamic Channel Remapability Supports up to 192 kHz Fs 24-bit throughput Increased memory/MIPs SRAM Interface for increased delay and buffer capability Dual-Precision Bass Manager Enhance your system functionality via firmware upgrades through the Crystal WareTM Software Licensing Program The CS493XX is a family of multichannel audio decoders intended to supersede the CS4923/4/5/6/7/8/9 family as the leader of audio decoding in both the DVD, broadcast and receiver markets. The family will be split into parts tailored for each of these distinct market segments. For the DVD market, parts will be offered which support Meridian Lossless Packing MLP , Dolby Digital, Dolby Pro Logic II, MPEG Multichannel, DTS Digital Surround, DTS-ES, AAC, and subsets thereof. For the receiver market, parts will be offered which support Dolby Digital, Dolby Pro Logic II, MPEG Multichannel, DTS Digital Surround, DTS-ES, AAC, and various virtualizers and PCM enhancement algorithms such as DTS Neo:6TM, and SRS Circle Surround For the broadcast market, parts will be offered which support Dolby Digital, AAC, MPEG-1, Layers 1,2 and 3, MPEG-2, Layers 2 and Under the Crystal brand, Cirrus Logic is the only single supplier of high-performance 24-bit multi-standard audio DSP decoders, DSP firmware, and high-resolution data converters. This combination of DSPs, system firmware, and data converters simplify rapid creation of world-class high-fidelity digital audio products for the Internet age. Ordering Information See page 87 CS49300 CS49310 CS49311 CS49312 CS49325 CS49326 CS49329 CS49330 APPLICATION DVD Audio Broadcast AVR Car Audio DSP General Purpose Post-Processor CORE DECODER FUNCTIONALITY MLP, AC-3, AAC, DTS, MPEG MP3, etc. AAC, AC-3, MPEG Stereo, MP3, etc. AAC, MPEG Stereo, MP3, etc. AC-3, MPEG Stereo, MP3, etc. AC-3, COS, MPEG MP3, etc. AC-3, DTS, COS, MPEG MP3, etc. AC-3, AAC, DTS, MPEG MP3, etc. Car Audio Code MPEG Stereo, MP3, C.O.S., etc DPP, THX Surround EX, THX Ultra2 Cinema RESET RD, WR, SCDIO, DATA7:0, R/W, DS, SCDOUT, EMAD7:0, EMOE, EMWR, PSEL, A0, A1, ABOOT, GPIO7:0 CS GPIO11 GPIO10 GPIO9 SCCLK SCDIN INTREQ EXTMEM, GPIO8 CMPDAT, SDATAN2 CMPCLK, SCLKN2 CMPREQ, LRCLKN2 SCLKN1, STCCLK2 LRCLKN1 SDATAN1 CLKIN CLKSEL Compressed Data Input Interface Framer Shifter Digital Audio Input Interface Input Buffer Controller RAM Input Buffer PLL Clock Manager Parallel or Serial Host Interface 24-Bit DSP Processing RAM Program Data Memory ROM Program Data Memory RAM Output Buffer DD DC Output Formatter MCLK SCLK LRCLK AUDATA[2.0] XMT958/AUDATA3 FILT2 FILT1 VA AGND DGND[3:1] VD[3:1] Copyright Cirrus Logic, Inc. 2006 All Rights Reserved APR ‘06 DS339F7 13.ORDERING INFORMATION 87 14.PACKAGE DIMENSIONS 88 LIST OF FIGURES Figure RESET Timing 9 Figure CLKIN with CLKSEL = VSS = PLL Enable 9 Figure Parallel Host Mode Read Cycle 11 Figure Parallel Host Mode Write Cycle 11 Figure Parallel Host Mode Read Cycle 13 Figure Parallel Host Mode Write Cycle 13 Figure SPI Control Port Timing 15 Figure Control Port Timing 17 Figure Digital Audio Input Data, Master and Slave Clock Timing 19 Figure Serial Compressed Data Timing 20 Figure Parallel Data Timing when not in a parallel control mode 21 Figure Digital Audio Output Data, Input and Output Clock Timing 23 Figure Control 29 Figure Control with External Memory 30 Figure SPI Control 31 Figure SPI Control with External Memory 32 Figure Parallel Control Mode 33 DS339F7 CS49300 Family DSP Figure Parallel Control Mode 34 Figure SPI Write Flow Diagram 37 Figure SPI Read Flow Diagram 37 Figure SPI Timing 39 Figure Write Flow Diagram 40 Figure Read Flow Diagram 41 Figure Timing 42 Figure Intel Mode, One-Byte Write Flow Diagram 46 Figure Intel Mode, One-Byte Read Flow Diagram 47 Figure Motorola Mode, One-Byte Write Flow Diagram 48 Figure Motorola Mode, One-Byte Read Flow Diagram 48 Figure Typical Parallel Host Mode Control Write Sequence Flow Diagram 49 Figure Typical Parallel Host Mode Control Read Sequence Flow Diagram 50 Figure External Memory Interface 53 Figure External Memory Read 16-bit address 53 Figure External Memory Write 16-bit address 53 Figure Typical Serial Boot and Download Procedure 55 Figure Typical Parallel Boot and Download Procedure 56 Figure Autoboot Timing Diagram 58 Figure Autoboot Sequence 59 Figure Autoboot INTREQ Behavior 60 Figure Fast Autoboot Sequence Using GFABT Codes 62 Figure Performing a Reset 64 Figure Non-Paged Memory 65 Figure Example Contents of a Paged 32 Kilobytes External Memory 66 Figure CDB49300-MEMA.0 Daughter Card for the CDB4923/30-REV-A.0 67 Figure I2S Format 69 Figure Left Justified Format Rising Edge Valid SCLK 69 Figure Multichannel Format 70 LIST OF TABLES Table PLL Filter Component 28 Table Host Modes 36 Table SPI Communication Signals 36 Table Communication Signals 38 Table Parallel Input/Output 45 Table Intel Mode Communication Signals 46 Table Motorola Mode Communication 47 Table Memory Interface 51 Table Boot Write Messages 54 Table Boot Read Messages 54 Table Reduced Autoboot Times using GFABT8.LD, GFABT6.LD, and GFABT4.LD on a Input Parameter A 75 Table Input Data Format Configuration Input Parameter B 75 DS339F7 CS49300 Family DSP Table Input SCLK Polarity Configuration Input Parameter C 77 Table Input FIFO Setup Configuration Input Parameter D 77 Table Output Clock Configuration Parameter A 78 Table Output Data Format Configuration Parameter B 78 Table Output MCLK Configuration Parameter C 79 Table Output SCLK Configuration Parameter D 79 Table Output SCLK Polarity Configuration Parameter E 79 Table Example Values to be Sent to CS493XX After Download or Soft Reset.............. 81 DS339F7 CS49300 Family DSP Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries "Cirrus" believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind express or implied . Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE "CRITICAL APPLICATIONS" . CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. Dolby, Dolby Digital, AC-3, Pro Logic, Dolby Surround, Surround EX, Virtual Dolby Digital, MLP, MLP Lossless, AAC, the "AAC" logo, the "Dolby Digital" logo, "Dolby Digital with Pro Logic II" logo, "Dolby" and the double-"D" symbol are trademarks or registered trademarks of Dolby Laboratories, Inc. Supply of an implementation of Dolby Technology does not convey a license nor imply a right under any patent, or any other industrial or Intellectual Property Right of Dolby Laboratories, to use the Implementation in any finished end-user or ready-to-use final product. It is hereby notified that a license for such use is required from Dolby Laboratories. DTS, DTS Digital Surround, DTS-ES Extended Surround, DTS Neo:6, DTS Virtual the "DTS", "DTS-ES", "DTS Virtual logos are trademarks or registered trademarks of the Digital Theater Systems, Inc. It is hereby notified that a third-party license from DTS is necessary to distribute software of DTS in any finished end-user or ready-to-use final product. Technology by Lucasarts Entertainment Company Corporation. THX is a registered trademark of Lucasarts Entertainment Company Corporation. Home THX is a registered trademark of Lucasfilm Ltd. , High Definition Compatible and Pacific Microsonics Inc. are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. HDCD technology cannot be used or distributed without a license from Microsoft Licensing, Inc. The "MPEG Logo" is a registered trademark of Philips Electronics N.V. In regards to the MP3 capable functionality of the CS49300 Family DSP via downloading of mp3_493xxx_vv.ld and mp3e_493xxx_vv.ld application codes the following statements are applicable "MPEG Layer-3 MP3 audio coding technology licensed from Fraunhofer Gesellschaft and Thomson multimedia. Supply of this product only conveys a license for personal, private and non-commercial use." SRS, Circle Surround, and TruSurround are registered trademarks of SRS Labs, Inc. The CIRCLE SURROUND TECHNOLOGY rights incorporated in the Cirrus Logic chip are owned by SRS Labs, Inc. and by Valence Technology Ltd., and licensed to Cirrus Logic, Inc. Users of any Cirrus Logic chip containing enabled CIRCLE SURROUND i.e., CIRCLE LICENSEES must first sign a license to purchase production quantities for consumer electronics applications which may be granted upon submission of a preproduction sample to, and the satisfactory passing of performance verification tests performed by SRS Labs, Inc., or Valence Technology Ltd. E-mail requests for performance specifications and testing rate schedule may be made to SRS Labs, Inc. and Valence Technology, Ltd., reserve the right to decline a use license for any submission that does not pass performance specifications or is not in the consumer electronics classification. All equipment manufactured using any Cirrus Logic chip containing enabled CIRCLE TECHNOLOGY must carry the Circle logo on the front panel in a manner approved in writing by SRS Labs, Inc., or Valence Technology Ltd. If the Circle logo is printed in users manuals, service manuals or advertisements, it must appear in a form approved in writing by SRS Labs, Inc., or Valence Technology, Ltd. The rear panel of Circle products, users manuals, service manuals, and all advertising must all carry the legends as described in LICENSOR'S most current version of the CIRCLE SURROUND Trademark Usage Manual. Intel is a registered trademark of Intel Corporation. Motorola and SPI are registered trademarks of Motorola, Inc. Harman VMAx and LOGIC7 are registered trademarks of Harman International Industries, Inc. I2C is a registered trademark of Philips Semiconductor. ORDERING INFORMATION CS49300 Family DSP Base Part Number 6th digit = ROM ID CS493122 CS493292 CS493302 CS493253 CS493263 CS493254 CS493264 CS493005 CS493105 CS493115 CS493295 Grades and Temperature Ranges Consumer 0° to 70°C Industrial -40° to 85°C Automotive -40° to 85°C CS493122-CL CS493292-CL CS493292-IL CS493302-CL CS493302-IL CS493253-CL CS493263-CL CS493263-IL CS493263-DL Pb-free Only CS493254-CL CS493254-IL CS493264-CL CS493264-IL CS493005-CL CS493105-CL CS493115-CL CS493295-CL Package 44-pin PLCC Pb-free Option “Z” Suffix CS493122-CLZ CS493292-CLZ CS493302-CLZ or -ILZ CS493253-CLZ CS493263-CLZ or -ILZ or -DLZ CS493254-CLZ CS493264-CLZ CS493005-CLZ CS493105-CLZ CS493115-CLZ CS493295-CLZ CS493105-CLZ EFBAJXAB0325 DS339F7 PACKAGE DIMENSIONS CS49300 Family DSP 44L PLCC PACKAGE DRAWING e D2/E2 INCHES MILLIMETERS DS339F7 CS49300 Family DSP Date Mar 2003 Feb 2004 Changes 0x0014C0 to 0x0028C0 p. 84, Added ROM ID-5 devices and a note on ordering lead-free devices to “Ordering Information”. Also added a description of the characters that comprise the part number. Removed ambient temperature condition TA=25°C from Spec Tables. Changed Note in Table p.12 and Table p.14 from: With a 4.7k Ohm pull-up resistor this value is typically 215ns. As this pin is open drain adjusting the pull up value will affect the rise time. Apr 2004 Changed “All bidirectional pins high-Z after RESET low” Trst2z parameter from 50ns Max to 100ns Max. See page APR 2005 Updated Device Ordering Information to include Pb-free devices. JUN 2005 Corrected error in mechanical information - “e”, pin spacing from mm to NOV 2005 Updated CLKIN high/low times to 14 ns. Added “Delay from falling edge of CMPREQ to CMPCLK rising edge” parameter to Serial Bursty Data Input timing 0 ns . Updated same timing diagram to include Treqclk parameter. JAN 2006 AddedThermal Data section APR 2006 Added Note 3 and Note 4 to Section “Thermal Data” on page Corrected copyright date. DS339F7 CS49300 Family DSP DS339F7

PDF Datasheet Preview

CS49300 Family DSP

Multi-Standard Audio Decoder Family
z CS4930X DVD Audio Sub-family PES Layer decode for A/V sync DVD Audio Pack Layer Support Meridian Lossless Packing Specification MLP Dolby Digital , Dolby Pro Logic II MPEG-2, Advanced Audio Coding Algorithm AAC MPEG Multichannel DTS Digital Surround , DTS-ES Extended Surround
z CS4931X Broadcast Sub-family PES Layer decode for A/V sync Dolby Digital MPEG-2, Advanced Audio Coding Algorithm AAC MPEG-1 Layers 1, 2, 3 Stereo MPEG-2 Layers 2, 3 Stereo
z CS4932X AVR Sub-family Dolby Digital, Dolby Pro Logic II DTS & DTS-ES decoding with integrated DTS tables Cirrus Original Surround PCM Enhancement MPEG-2, Advanced Audio Coding Algorithm AAC MPEG Multichannel MP3 MPEG-1, Layer 3
z CS49330 General Purpose Audio DSP Surround EX and Ultra2 Cinema General Purpose AVR and Broadcast Audio Decoder MPEG Multichannel, MPEG Stereo, MP3, C.O.S. Car Audio
z Features are a super-set of the CS4923/4/5/6/7/8/9 8 channel output, including dual zone output capability Dynamic Channel Remapability Supports up to 192 kHz Fs 24-bit throughput Increased memory/MIPs SRAM Interface for increased delay and buffer capability Dual-Precision Bass Manager Enhance your system functionality via firmware upgrades through the Crystal WareTM Software Licensing Program

The CS493XX is a family of multichannel audio decoders intended to supersede the CS4923/4/5/6/7/8/9 family as the leader of audio decoding in both the DVD, broadcast and receiver markets. The family will be split into parts tailored for each of these distinct market segments.

For the DVD market, parts will be offered which support Meridian Lossless Packing MLP , Dolby Digital, Dolby Pro Logic II, MPEG Multichannel, DTS Digital Surround, DTS-ES, AAC, and subsets thereof. For the receiver market, parts will be offered which support Dolby Digital, Dolby Pro Logic II, MPEG Multichannel, DTS Digital Surround, DTS-ES, AAC, and various virtualizers and PCM enhancement algorithms such as DTS Neo:6TM, and SRS Circle Surround For the broadcast market, parts will be offered which support Dolby Digital, AAC, MPEG-1, Layers 1,2 and 3, MPEG-2, Layers 2 and

Under the Crystal brand, Cirrus Logic is the only single supplier of high-performance 24-bit multi-standard audio DSP decoders, DSP firmware, and high-resolution data converters. This combination of DSPs, system firmware, and data converters simplify rapid creation of world-class high-fidelity digital audio products for the Internet age.
Ordering Information See page 87

CS49300 CS49310 CS49311 CS49312 CS49325 CS49326 CS49329 CS49330

APPLICATION DVD Audio Broadcast AVR

Car Audio DSP General Purpose Post-Processor

CORE DECODER FUNCTIONALITY MLP, AC-3, AAC, DTS, MPEG MP3, etc.

AAC, AC-3, MPEG Stereo, MP3, etc. AAC, MPEG Stereo, MP3, etc. AC-3, MPEG Stereo, MP3, etc.

AC-3, COS, MPEG MP3, etc. AC-3, DTS, COS, MPEG MP3, etc. AC-3, AAC, DTS, MPEG MP3, etc.

Car Audio Code MPEG Stereo, MP3, C.O.S., etc DPP, THX Surround EX, THX Ultra2 Cinema

RESET

RD, WR, SCDIO,

DATA7:0,

R/W, DS, SCDOUT,

EMAD7:0,

EMOE, EMWR, PSEL, A0, A1, ABOOT,

GPIO7:0 CS GPIO11 GPIO10 GPIO9 SCCLK SCDIN INTREQ

EXTMEM, GPIO8

CMPDAT, SDATAN2

CMPCLK, SCLKN2

CMPREQ, LRCLKN2

SCLKN1, STCCLK2 LRCLKN1 SDATAN1

CLKIN CLKSEL

Compressed Data Input Interface

Framer Shifter

Digital Audio Input

Interface

Input Buffer Controller

RAM Input Buffer

PLL Clock Manager

Parallel or Serial Host Interface
24-Bit DSP Processing

RAM Program Data Memory

ROM Program Data Memory

RAM Output Buffer

DD DC

Output Formatter

MCLK SCLK LRCLK AUDATA[2.0]

XMT958/AUDATA3

FILT2 FILT1 VA AGND

DGND[3:1] VD[3:1]

Copyright Cirrus Logic, Inc. 2006 All Rights Reserved

APR ‘06 DS339F7
13.ORDERING INFORMATION 87
14.PACKAGE DIMENSIONS 88

LIST OF FIGURES

Figure RESET Timing 9 Figure CLKIN with CLKSEL = VSS = PLL Enable 9 Figure Parallel Host Mode Read Cycle 11 Figure Parallel Host Mode Write Cycle 11 Figure Parallel Host Mode Read Cycle 13 Figure Parallel Host Mode Write Cycle 13 Figure SPI Control Port Timing 15 Figure Control Port Timing 17 Figure Digital Audio Input Data, Master and Slave Clock Timing 19 Figure Serial Compressed Data Timing 20 Figure Parallel Data Timing when not in a parallel control mode 21 Figure Digital Audio Output Data, Input and Output Clock Timing 23 Figure Control 29 Figure Control with External Memory 30 Figure SPI Control 31 Figure SPI Control with External Memory 32 Figure Parallel Control Mode 33

DS339F7

CS49300 Family DSP

Figure Parallel Control Mode 34 Figure SPI Write Flow Diagram 37 Figure SPI Read Flow Diagram 37 Figure SPI Timing 39 Figure Write Flow Diagram 40 Figure Read Flow Diagram 41 Figure Timing 42 Figure Intel Mode, One-Byte Write Flow Diagram 46 Figure Intel Mode, One-Byte Read Flow Diagram 47 Figure Motorola Mode, One-Byte Write Flow Diagram 48 Figure Motorola Mode, One-Byte Read Flow Diagram 48 Figure Typical Parallel Host Mode Control Write Sequence Flow Diagram 49 Figure Typical Parallel Host Mode Control Read Sequence Flow Diagram 50 Figure External Memory Interface 53 Figure External Memory Read 16-bit address 53 Figure External Memory Write 16-bit address 53 Figure Typical Serial Boot and Download Procedure 55 Figure Typical Parallel Boot and Download Procedure 56 Figure Autoboot Timing Diagram 58 Figure Autoboot Sequence 59 Figure Autoboot INTREQ Behavior 60 Figure Fast Autoboot Sequence Using GFABT Codes 62 Figure Performing a Reset 64 Figure Non-Paged Memory 65 Figure Example Contents of a Paged 32 Kilobytes External Memory 66 Figure CDB49300-MEMA.0 Daughter Card for the CDB4923/30-REV-A.0 67 Figure I2S Format 69 Figure Left Justified Format Rising Edge Valid SCLK 69 Figure Multichannel Format 70

LIST OF TABLES

Table PLL Filter Component 28 Table Host Modes 36 Table SPI Communication Signals 36 Table Communication Signals 38 Table Parallel Input/Output 45 Table Intel Mode Communication Signals 46 Table Motorola Mode Communication 47 Table Memory Interface 51 Table Boot Write Messages 54 Table Boot Read Messages 54 Table Reduced Autoboot Times using GFABT8.LD, GFABT6.LD, and GFABT4.LD on a

Input Parameter A 75 Table Input Data Format Configuration

Input Parameter B 75

DS339F7

CS49300 Family DSP

Table Input SCLK Polarity Configuration Input Parameter C 77

Table Input FIFO Setup Configuration Input Parameter D 77

Table Output Clock Configuration Parameter A 78

Table Output Data Format Configuration Parameter B 78

Table Output MCLK Configuration Parameter C 79

Table Output SCLK Configuration Parameter D 79

Table Output SCLK Polarity Configuration Parameter E 79

Table Example Values to be Sent to CS493XX After Download or Soft Reset.............. 81

DS339F7

CS49300 Family DSP

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

IMPORTANT NOTICE

Cirrus Logic, Inc. and its subsidiaries "Cirrus" believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind express or implied . Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE "CRITICAL APPLICATIONS" . CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.

Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.

Dolby, Dolby Digital, AC-3, Pro Logic, Dolby Surround, Surround EX, Virtual Dolby Digital, MLP, MLP Lossless, AAC, the "AAC" logo, the "Dolby Digital" logo, "Dolby Digital with Pro Logic II" logo, "Dolby" and the double-"D" symbol are trademarks or registered trademarks of Dolby Laboratories, Inc. Supply of an implementation of Dolby Technology does not convey a license nor imply a right under any patent, or any other industrial or Intellectual Property Right of Dolby Laboratories, to use the Implementation in any finished end-user or ready-to-use final product. It is hereby notified that a license for such use is required from Dolby Laboratories.

DTS, DTS Digital Surround, DTS-ES Extended Surround, DTS Neo:6, DTS Virtual the "DTS", "DTS-ES", "DTS Virtual logos are trademarks or registered trademarks of the Digital Theater Systems, Inc. It is hereby notified that a third-party license from DTS is necessary to distribute software of DTS in any finished end-user or ready-to-use final product.

Technology by Lucasarts Entertainment Company Corporation. THX is a registered trademark of Lucasarts Entertainment Company Corporation. Home THX is a registered trademark of Lucasfilm Ltd.
, High Definition Compatible and Pacific Microsonics Inc. are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. HDCD technology cannot be used or distributed without a license from Microsoft Licensing, Inc.

The "MPEG Logo" is a registered trademark of Philips Electronics N.V.

In regards to the MP3 capable functionality of the CS49300 Family DSP via downloading of mp3_493xxx_vv.ld and mp3e_493xxx_vv.ld application codes the following statements are applicable "MPEG Layer-3 MP3 audio coding technology licensed from Fraunhofer Gesellschaft and Thomson multimedia. Supply of this product only conveys a license for personal, private and non-commercial use."

SRS, Circle Surround, and TruSurround are registered trademarks of SRS Labs, Inc. The CIRCLE SURROUND TECHNOLOGY rights incorporated in the Cirrus Logic chip are owned by SRS Labs, Inc. and by Valence Technology Ltd., and licensed to Cirrus Logic, Inc. Users of any Cirrus Logic chip containing enabled CIRCLE SURROUND i.e., CIRCLE LICENSEES must first sign a license to purchase production quantities for consumer electronics applications which may be granted upon submission of a preproduction sample to, and the satisfactory passing of performance verification tests performed by SRS Labs, Inc., or Valence Technology Ltd. E-mail requests for performance specifications and testing rate schedule may be made to SRS Labs, Inc. and Valence Technology, Ltd., reserve the right to decline a use license for any submission that does not pass performance specifications or is not in the consumer electronics classification.

All equipment manufactured using any Cirrus Logic chip containing enabled CIRCLE TECHNOLOGY must carry the Circle logo on the front panel in a manner approved in writing by SRS Labs, Inc., or Valence Technology Ltd. If the Circle logo is printed in users manuals, service manuals or advertisements, it must appear in a form approved in writing by SRS Labs, Inc., or Valence Technology, Ltd. The rear panel of Circle products, users manuals, service manuals, and all advertising must all carry the legends as described in LICENSOR'S most current version of the CIRCLE SURROUND Trademark Usage Manual.

Intel is a registered trademark of Intel Corporation.

Motorola and SPI are registered trademarks of Motorola, Inc.

Harman VMAx and LOGIC7 are registered trademarks of Harman International Industries, Inc.

I2C is a registered trademark of Philips Semiconductor.
ORDERING INFORMATION

CS49300 Family DSP

Base Part Number
6th digit = ROM ID

CS493122 CS493292 CS493302 CS493253 CS493263

CS493254 CS493264 CS493005 CS493105 CS493115 CS493295

Grades and Temperature Ranges

Consumer
0° to 70°C

Industrial
-40° to 85°C

Automotive
-40° to 85°C

CS493122-CL

CS493292-CL CS493292-IL

CS493302-CL CS493302-IL

CS493253-CL

CS493263-CL CS493263-IL CS493263-DL

Pb-free Only

CS493254-CL CS493254-IL

CS493264-CL CS493264-IL

CS493005-CL

CS493105-CL

CS493115-CL

CS493295-CL

Package 44-pin PLCC

Pb-free Option “Z” Suffix

CS493122-CLZ CS493292-CLZ CS493302-CLZ or -ILZ CS493253-CLZ CS493263-CLZ or -ILZ or -DLZ

CS493254-CLZ CS493264-CLZ CS493005-CLZ CS493105-CLZ CS493115-CLZ CS493295-CLZ

CS493105-CLZ EFBAJXAB0325

DS339F7

PACKAGE DIMENSIONS

CS49300 Family DSP
44L PLCC PACKAGE DRAWING
e D2/E2

INCHES

MILLIMETERS

DS339F7

CS49300 Family DSP

Date Mar 2003 Feb 2004

Changes
0x0014C0 to 0x0028C0 p. 84, Added ROM ID-5 devices and a note on ordering lead-free devices to “Ordering Information”. Also added a description of the characters that comprise the part number.

Removed ambient temperature condition TA=25°C from Spec Tables.

Changed Note in Table p.12 and Table p.14 from:

With a 4.7k Ohm pull-up resistor this value is typically 215ns. As this pin is open drain adjusting the pull up value will affect the rise time.

Apr 2004

Changed “All bidirectional pins high-Z after RESET low” Trst2z parameter from
50ns Max to 100ns Max. See page

APR 2005
Updated Device Ordering Information to include Pb-free devices.

JUN 2005

Corrected error in mechanical information - “e”, pin spacing from mm to

NOV 2005

Updated CLKIN high/low times to 14 ns. Added “Delay from falling edge of

CMPREQ to CMPCLK rising edge” parameter to Serial Bursty Data Input timing
0 ns . Updated same timing diagram to include Treqclk parameter.

JAN 2006

AddedThermal Data section

APR 2006

Added Note 3 and Note 4 to Section “Thermal Data” on page Corrected
copyright date.

DS339F7

CS49300 Family DSP

DS339F7

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Datasheet ID: CS493105-CLZR 523191