HC1S80F1020AY

HC1S80F1020AY Datasheet

The HardCopy Stratix devices use the same base arrays across multiple designs for a given device density and are customized using the top two metal layers. The HardCopy Stratix family consists of the HC1S25, HC1S30, HC1S40, HC1S60, and HC1S80 devices. Table provides the details of the HardCopy Stratix devices.

Part	Datasheet
HC1S80F1020AY	HC1S80F1020AY (pdf)

Related Parts	Information
HC1S60F1020N	HC1S60F1020N
HC1S60F1020	HC1S60F1020
HC1S60F1020AG	HC1S60F1020AG
HC1S60F1020BL	HC1S60F1020BL
HC1S60F1020BM	HC1S60F1020BM
HC1S60F1020BQ	HC1S60F1020BQ
HC1S60F1020CA	HC1S60F1020CA
HC1S40F780NAK	HC1S40F780NAK
HC1S60F1020NBJ	HC1S60F1020NBJ
HC1S60F1020NBW	HC1S60F1020NBW
HC1S60F1020NBX	HC1S60F1020NBX
HC1S60F1020NBZ	HC1S60F1020NBZ
HC1S80F1020	HC1S80F1020
HC1S60F1020BY	HC1S60F1020BY
HC1S30F780NAE	HC1S30F780NAE
HC1S60F1020NAM	HC1S60F1020NAM
HC1S40F780NAH	HC1S40F780NAH
HC1S40F780NAF	HC1S40F780NAF
HC1S40F780NAD	HC1S40F780NAD
HC1S40F780N	HC1S40F780N
HC1S40F780NAM	HC1S40F780NAM
HC1S40F780	HC1S40F780
HC1S40F780NAL	HC1S40F780NAL
HC1S30F780NAC	HC1S30F780NAC
HC1S30F780NAB	HC1S30F780NAB
HC1S30F780AB	HC1S30F780AB
HC1S30F780	HC1S30F780
HC1S40F780NAJ	HC1S40F780NAJ
HC1S80F1020AR	HC1S80F1020AR
HC1S40F780AF	HC1S40F780AF
HC1S80F1020NAN	HC1S80F1020NAN
HC1S80F1020AS	HC1S80F1020AS
HC1S60F1020CB	HC1S60F1020CB
HC1S80F1020NAYR	HC1S80F1020NAYR
HC1S80F1020NAYP	HC1S80F1020NAYP
HC1S80F1020NAY	HC1S80F1020NAY
HC1S80F1020NAR	HC1S80F1020NAR
HC1S80XX	HC1S80XX
HC1S80F1020NAM	HC1S80F1020NAM
HC1S80F1020N	HC1S80F1020N
HC1S80F1020AX	HC1S80F1020AX
HC1S80F1020AT	HC1S80F1020AT
HC1S80F1020NAW	HC1S80F1020NAW
HC1S80F1020AW	HC1S80F1020AW
HC1S80F1020AYR	HC1S80F1020AYR
HC1S80F1020AXP	HC1S80F1020AXP
HC1S80F1020AXR	HC1S80F1020AXR
HC1S80F1020AYP	HC1S80F1020AYP

PDF Datasheet Preview
Section I. HardCopy Stratix Device Family Data Sheet This section provides designers with the data sheet specifications for Stratix structured ASICs. The chapters contain feature definitions of the internal architecture, JTAG boundary-scan testing information, DC operating conditions, AC timing parameters, and a reference to power consumption for HardCopy Stratix structured ASICs. This section contains the following: • Chapter 1, Introduction to HardCopy Stratix Devices • Chapter 2, Description, Architecture, and Features • Chapter 3, Boundary-Scan Support • Chapter 4, Operating Conditions • Chapter 5, Quartus II Support for HardCopy Stratix Devices • Chapter 6, Design Guidelines for HardCopy Stratix Performance Improvement Altera Corporation Section Preliminary HardCopy Series Handbook, Volume 1 Section Preliminary Altera Corporation H51001-2.4 Introduction Introduction to HardCopy Stratix Devices structured ASICs, Altera’s second-generation HardCopy structured ASICs, are low-cost, high-performance devices with the same architecture as the high-density Stratix FPGAs. The combination of Stratix FPGAs for prototyping and design verification, HardCopy Stratix devices for high-volume production, and the II design software beginning with version provide a complete and powerful alternative to ASIC design and development. HardCopy Stratix devices are architecturally equivalent and have the same features as the corresponding Stratix FPGA. They offer pin-to-pin compatibility using the same package as the corresponding Stratix FPGA prototype. Designers can prototype their design to verify functionality with Stratix FPGAs before seamlessly migrating the proven design to a HardCopy Stratix structured ASIC. The Quartus II software provides a complete set of inexpensive and easy-to-use tools for designing HardCopy Stratix devices. Using the successful and proven methodology from HardCopy APEX devices, Stratix FPGA designs can be seamlessly and quickly migrated to a low-cost ASIC alternative. Designers can use the Quartus II software to design HardCopy Stratix devices to obtain an average of 50% higher performance and up to 40% lower power consumption than can be achieved in the corresponding Stratix FPGAs. The migration process is fully automated, requires minimal customer involvement, and takes approximately eight weeks to deliver fully tested HardCopy Stratix prototypes. The HardCopy Stratix devices use the same base arrays across multiple designs for a given device density and are customized using the top two metal layers. The HardCopy Stratix family consists of the HC1S25, HC1S30, HC1S40, HC1S60, and HC1S80 devices. Table provides the details of the HardCopy Stratix devices. Altera Corporation September 2008 HardCopy Series Handbook, Volume 1 Table HardCopy Stratix Devices and Features Device HC1S25 HC1S30 HC1S40 HC1S60 HC1S80 LEs 1 25,660 32,470 41,250 57,120 79,040 M512 Blocks M4K Blocks M-RAM Blocks 2 4 2 4 DSP Blocks 2 10 12 14 18 22 PLLs 3 Notes to Table 1 LE logic elements. 2 DSP digital signal processing. 3 PLLs phase-locked loops. 4 In HC1S30, HC1S40, and HC1S80 devices, there are fewer M-RAM blocks than in the equivalent Stratix FPGA. All other resources are identical to the Stratix counterpart. HardCopy Stratix devices are manufactured on the same 1.5-V, um all-layer-copper metal fabrication process up to eight layers of metal as the Stratix FPGAs. • Preserves the functionality of a configured Stratix device • Pin-compatible with the Stratix counterparts • On average, 50% faster than their Stratix equivalents • On average, 40% less power consumption than their Stratix equivalents • 25,660 to 79,040 LEs • Up to 5,658,408 RAM bits available • TriMatrix memory architecture consisting of three RAM block sizes to implement true dual-port memory and first-in-first-out FIFO buffers • Embedded high-speed DSP blocks provide dedicated implementation of multipliers, multiply-accumulate functions, and finite impulse response FIR filters • Up to 12 PLLs four enhanced PLLs and eight fast PLLs per device which provide identical features as the FPGA counterparts, including spread spectrum, programmable bandwidth, clock switchover, real-time PLL reconfiguration, advanced multiplication, and phase shifting • Supports numerous single-ended and differential I/O standards • Supports high-speed networking and communications bus standards including RapidIO , UTOPIA IV, CSIX, HyperTransport technology, 10G Ethernet XSBI, SPI-4 Phase 2 POS-PHY Level 4 , and SFI-4 • Differential on-chip termination support for LVDS Altera Corporation September 2008

PDF Datasheet Preview

Section I. HardCopy Stratix Device Family Data Sheet

This section provides designers with the data sheet specifications for Stratix structured ASICs. The chapters contain feature definitions of the internal architecture, JTAG boundary-scan testing information, DC operating conditions, AC timing parameters, and a reference to power consumption for HardCopy Stratix structured ASICs.

This section contains the following:
• Chapter 1, Introduction to HardCopy Stratix Devices
• Chapter 2, Description, Architecture, and Features
• Chapter 3, Boundary-Scan Support
• Chapter 4, Operating Conditions
• Chapter 5, Quartus II Support for HardCopy Stratix Devices
• Chapter 6, Design Guidelines for HardCopy Stratix Performance Improvement

Altera Corporation

Section Preliminary

HardCopy Series Handbook, Volume 1

Section Preliminary

Altera Corporation

H51001-2.4

Introduction

Introduction to HardCopy Stratix Devices
structured ASICs, Altera’s second-generation HardCopy structured ASICs, are low-cost, high-performance devices with the same architecture as the high-density Stratix FPGAs. The combination of Stratix FPGAs for prototyping and design verification, HardCopy Stratix devices for high-volume production, and the II design software beginning with version provide a complete and powerful alternative to ASIC design and development.

HardCopy Stratix devices are architecturally equivalent and have the same features as the corresponding Stratix FPGA. They offer pin-to-pin compatibility using the same package as the corresponding Stratix FPGA prototype. Designers can prototype their design to verify functionality with Stratix FPGAs before seamlessly migrating the proven design to a HardCopy Stratix structured ASIC.

The Quartus II software provides a complete set of inexpensive and easy-to-use tools for designing HardCopy Stratix devices. Using the successful and proven methodology from HardCopy APEX devices, Stratix FPGA designs can be seamlessly and quickly migrated to a low-cost ASIC alternative. Designers can use the Quartus II software to design HardCopy Stratix devices to obtain an average of 50% higher performance and up to 40% lower power consumption than can be achieved in the corresponding Stratix FPGAs. The migration process is fully automated, requires minimal customer involvement, and takes approximately eight weeks to deliver fully tested HardCopy Stratix prototypes.

The HardCopy Stratix devices use the same base arrays across multiple designs for a given device density and are customized using the top two metal layers. The HardCopy Stratix family consists of the HC1S25, HC1S30, HC1S40, HC1S60, and HC1S80 devices. Table provides the details of the HardCopy Stratix devices.

Altera Corporation September 2008

HardCopy Series Handbook, Volume 1

Table HardCopy Stratix Devices and Features

Device

HC1S25 HC1S30 HC1S40 HC1S60 HC1S80

LEs 1
25,660 32,470 41,250 57,120 79,040

M512 Blocks M4K Blocks

M-RAM Blocks
2 4 2 4

DSP Blocks 2
10 12 14 18 22

PLLs 3

Notes to Table 1 LE logic elements. 2 DSP digital signal processing. 3 PLLs phase-locked loops. 4 In HC1S30, HC1S40, and HC1S80 devices, there are fewer M-RAM blocks than in the equivalent Stratix FPGA. All
other resources are identical to the Stratix counterpart.

HardCopy Stratix devices are manufactured on the same 1.5-V, um all-layer-copper metal fabrication process up to eight layers of metal as the Stratix FPGAs.
• Preserves the functionality of a configured Stratix device
• Pin-compatible with the Stratix counterparts
• On average, 50% faster than their Stratix equivalents
• On average, 40% less power consumption than their Stratix
equivalents
• 25,660 to 79,040 LEs
• Up to 5,658,408 RAM bits available
• TriMatrix memory architecture consisting of three RAM block sizes
to implement true dual-port memory and first-in-first-out FIFO buffers
• Embedded high-speed DSP blocks provide dedicated implementation of multipliers, multiply-accumulate functions, and finite impulse response FIR filters
• Up to 12 PLLs four enhanced PLLs and eight fast PLLs per device which provide identical features as the FPGA counterparts, including spread spectrum, programmable bandwidth, clock switchover, real-time PLL reconfiguration, advanced multiplication, and phase shifting
• Supports numerous single-ended and differential I/O standards
• Supports high-speed networking and communications bus standards including RapidIO , UTOPIA IV, CSIX, HyperTransport technology, 10G Ethernet XSBI, SPI-4 Phase 2 POS-PHY Level 4 , and SFI-4
• Differential on-chip termination support for LVDS

Altera Corporation September 2008

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived HC1S80F1020AY Datasheet file may be downloaded here without warranties.

Datasheet ID: HC1S80F1020AY 517146