PEX8649-AA50RBC F

PEX8649-AA50RBC F Datasheet

PEX 8649, PCI Express Gen 2 Switch, 48 Lanes, 12 Ports

Part	Datasheet
PEX8649-AA50RBC F	PEX8649-AA50RBC F (pdf)

Related Parts	Information
PEX8649-16U16DAICRDK	PEX8649-16U16DAICRDK

PDF Datasheet Preview
PEX 8649, PCI Express Gen 2 Switch, 48 Lanes, 12 Ports Highlights PEX 8649 General Features o 48-lane, 12-port PCIe Gen2 switch - Integrated GT/s SerDes o 27 x 27mm2, 676-ball FCBGA package o Typical Power Watts PEX 8649 Key Features o Standards Compliant - PCI Express Base Specification, r2.0 backwards compatible w/ PCIe r1.0a/1.1 - PCI Power Management Spec, r1.2 - Microsoft Vista Compliant - Supports Access Control Services - Dynamic link-width control - Dynamic SerDes speed control o High Performance performancePAK 9 Read Pacing bandwidth throttling 9 Multicast 9 Dynamic Buffer/FC Credit Pool - Non-blocking switch fabric - Full line rate on all ports - Packet Cut-Thru with 176ns max packet latency x16 to x16 - 2KB Max Payload Size o Multi-Host & Fail-Over Support - Configurable Non-Transparent NT port - Failover with NT port - Up to Four upstream/Host ports with 1+1 or N+1 failover to other upstream ports o Quality of Service QoS - Eight traffic classes per port - Weighted round-robin source port arbitration o Reliability, Availability, Serviceability visionPAK 9 Per Port Performance Monitoring Per port payload & header counters 9 SerDes Eye Capture 9 Error Injection and Loopback - 3 Hot Plug Ports with native HP Signals - All ports hot plug capable thru I2C Hot Plug Controller on every port - ECRC and Poison bit support - Data Path parity - Memory RAM Error Correction - INTA# and FATAL_ERR# signals - Advanced Error Reporting - Port Status bits and GPIO available • Per port error diagnostics - JTAG AC/DC boundary scan The ExpressLane PEX 8649 device offers Multi-Host PCI Express switching capability enabling users to connect multiple hosts to their respective endpoints via scalable, high bandwidth, non-blocking interconnection to a wide variety of applications including servers, storage systems, and communications platforms. The PEX 8649 is well suited for fan-out, aggregation, and peer-to-peer applications. Multi-Host Architecture The PEX 8649 employs an enhanced version of PLX’s field tested PEX 8648 PCIe switch architecture, which allows users to configure the device in legacy single-host mode or multi-host mode with up to four host ports capable of 1+1 one active & one backup or N+1 N active & one backup host failover. This powerful architectural enhancement enables users to build PCIe based systems to support high-availability, failover, redundant and clustered systems. High Performance & Low Packet Latency The PEX 8649 architecture supports packet cut-thru with a maximum latency of 176ns x16 to x16 . This, combined with large packet memory, flexible common buffer/FC credit pool and non-blocking internal switch architecture, provides full line rate on all ports for performance-hungry applications such as servers and switch fabrics. The low latency enables applications to achieve high throughput and performance. In addition to low latency, the device supports a packet payload size of up to 2048 bytes, enabling the user to achieve even higher throughput. Data Integrity The PEX 8649 provides end-to-end CRC ECRC protection and Poison bit support to enable designs that require end-to-end data integrity. PLX also supports data path parity and memory RAM error correction circuitry throughout the internal data paths as packets pass through the switch. Flexible Configuration The PEX 8649’s 12 ports can be configured to lane widths of x1, x2, x4, x8, or x16. Flexible buffer allocation, along with the device's flexible packet flow control, maximizes throughput for applications where more traffic flows in the downstream, rather than upstream, direction. Any port can be designated as the upstream port, which can be changed dynamically. Figure 1 shows some of the PEX 8649’s common port configurations in legacy Single-Host mode. PLX Technology, 5/14/2009, Version PEX 8649, PCI Express Gen 2 Switch, 48 Lanes, 12 Ports The PEX 8649 can also be configured in Multi-Host mode where users can choose up to four ports as host/upstream ports and assign a desired number of downstream ports to each host. In Multi-Host mode, a virtual switch is created for each host port and its associated downstream ports inside the device. The traffic between the ports of a virtual switch is completely isolated from the traffic in other virtual switches. Figure 2 illustrates some configurations of the PEX 8649 in Multi-Host mode where each ellipse represents a virtual switch inside the device. The PEX 8649 x8 x4 also provides several ways to configure its registers. The PEX 8649 PEX 8649 device can be configured through strapping pins, I2C 3 x8 2 x4 3 x4s 2 x8 2 x4 2 x4 4 x4s interface, host software, or an optional serial EEPROM. This PEX 8649 PEX 8649 allows for easy debug during the 9 x4s 8 x4s Product Ordering Information PEX8649-AA50BC F 48-Lane, 12-Port PCI Express Switch, Pb-Free 27x27mm2 PEX8649-16U16D AIC PEX 8649 Rapid Development Kit with x16 Upstream and Two x16 Downstream PLX Technology, Inc. All rights reserved. PLX, the PLX logo, ExpressLane, Read Pacing and Dual Cast are trademarks of PLX Technology, Inc. All other product names that appear in this material are for identification purposes only and are acknowledged to be trademarks or registered trademarks of their respective companies. Information supplied by PLX is believed to be accurate and reliable, but PLX assumes no responsibility for any errors that may appear in this material. PLX reserves the right, without notice, to make changes in product design or specification. Visit for more information. Figure PEX8649-16U16D AIC RDK PLX Technology, Page 5 of 5 5/14/2009, Version

PDF Datasheet Preview

PEX 8649, PCI Express Gen 2 Switch, 48 Lanes, 12 Ports

Highlights

PEX 8649 General Features
o 48-lane, 12-port PCIe Gen2 switch - Integrated GT/s SerDes
o 27 x 27mm2, 676-ball FCBGA package o Typical Power Watts

PEX 8649 Key Features
o Standards Compliant - PCI Express Base Specification, r2.0 backwards compatible w/ PCIe r1.0a/1.1 - PCI Power Management Spec, r1.2 - Microsoft Vista Compliant - Supports Access Control Services - Dynamic link-width control - Dynamic SerDes speed control
o High Performance performancePAK 9 Read Pacing bandwidth throttling 9 Multicast 9 Dynamic Buffer/FC Credit Pool - Non-blocking switch fabric - Full line rate on all ports - Packet Cut-Thru with 176ns max packet latency x16 to x16 - 2KB Max Payload Size
o Multi-Host & Fail-Over Support - Configurable Non-Transparent NT port - Failover with NT port - Up to Four upstream/Host ports with 1+1 or N+1 failover to other upstream ports
o Quality of Service QoS - Eight traffic classes per port - Weighted round-robin source port arbitration
o Reliability, Availability, Serviceability visionPAK 9 Per Port Performance Monitoring Per port payload & header counters 9 SerDes Eye Capture 9 Error Injection and Loopback - 3 Hot Plug Ports with native HP Signals - All ports hot plug capable thru I2C Hot Plug Controller on every port - ECRC and Poison bit support - Data Path parity - Memory RAM Error Correction - INTA# and FATAL_ERR# signals - Advanced Error Reporting - Port Status bits and GPIO available
• Per port error diagnostics - JTAG AC/DC boundary scan

The ExpressLane PEX 8649 device offers Multi-Host PCI Express switching capability enabling users to connect multiple hosts to their respective endpoints via scalable, high bandwidth, non-blocking interconnection to a wide variety of applications including servers, storage systems, and communications platforms. The PEX 8649 is well suited for fan-out, aggregation, and peer-to-peer applications.

Multi-Host Architecture The PEX 8649 employs an enhanced version of PLX’s field tested PEX 8648 PCIe switch architecture, which allows users to configure the device in legacy single-host mode or multi-host mode with up to four host ports capable of 1+1 one active & one backup or N+1 N active & one backup host failover. This powerful architectural enhancement enables users to build PCIe based systems to support high-availability, failover, redundant and clustered systems.

High Performance & Low Packet Latency The PEX 8649 architecture supports packet cut-thru with a maximum latency of 176ns x16 to x16 . This, combined with large packet memory, flexible common buffer/FC credit pool and non-blocking internal switch architecture, provides full line rate on all ports for performance-hungry applications such as servers and switch fabrics. The low latency enables applications to achieve high throughput and performance. In addition to low latency, the device supports a packet payload size of up to 2048 bytes, enabling the user to achieve even higher throughput.

Data Integrity The PEX 8649 provides end-to-end CRC ECRC protection and Poison bit support to enable designs that require end-to-end data integrity. PLX also supports data path parity and memory RAM error correction circuitry throughout the internal data paths as packets pass through the switch.

Flexible Configuration The PEX 8649’s 12 ports can be configured to lane widths of x1, x2, x4, x8, or x16. Flexible buffer allocation, along with the device's flexible packet flow control, maximizes throughput for applications where more traffic flows in the downstream, rather than upstream, direction. Any port can be designated as the upstream port, which can be changed dynamically. Figure 1 shows some of the PEX 8649’s common port configurations in legacy Single-Host mode.

PLX Technology,
5/14/2009, Version

PEX 8649, PCI Express Gen 2 Switch, 48 Lanes, 12 Ports

The PEX 8649 can also be configured in Multi-Host mode where users can choose up to four ports as host/upstream ports and assign a desired number of downstream ports to each host. In Multi-Host mode, a virtual switch is created for each host port and its associated downstream ports inside the device. The traffic between the ports of a virtual switch is completely isolated from the traffic in other virtual switches. Figure 2 illustrates some configurations of the PEX 8649 in Multi-Host mode where each ellipse represents a virtual switch inside the device.

The PEX 8649
x8 x4
also provides
several ways to
configure its registers. The

PEX 8649

PEX 8649
device can be
configured
through strapping pins, I2C
3 x8 2 x4 3 x4s
2 x8 2 x4 2 x4 4 x4s
interface, host
software, or an
optional serial EEPROM. This

PEX 8649

PEX 8649
allows for easy
debug during the
9 x4s
8 x4s
Product Ordering Information

PEX8649-AA50BC F
48-Lane, 12-Port PCI Express Switch, Pb-Free 27x27mm2

PEX8649-16U16D AIC PEX 8649 Rapid Development Kit with
x16 Upstream and Two x16 Downstream

PLX Technology, Inc. All rights reserved. PLX, the PLX logo, ExpressLane, Read Pacing and Dual Cast are trademarks of PLX Technology, Inc. All other product names that appear in this material are for identification purposes only and are acknowledged to be trademarks or registered trademarks of their respective companies. Information supplied by PLX is believed to be accurate and reliable, but PLX assumes no responsibility for any errors that may appear in this material. PLX reserves the right, without notice, to make changes in product design or specification.

Visit for more information.

Figure PEX8649-16U16D AIC RDK

PLX Technology,

Page 5 of 5
5/14/2009, Version

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived PEX8649-AA50RBC F Datasheet file may be downloaded here without warranties.

Datasheet ID: PEX8649-AA50RBC F 520511