SCANPSC110FSCX

SCANPSC110FSCX Datasheet

SCANPSC110F SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port IEEE1149.1 System Test Support

Part	Datasheet
SCANPSC110FSCX	SCANPSC110FSCX (pdf)

Related Parts	Information
SCANPSC110FSC	SCANPSC110FSC

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SCANPSC110F SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port IEEE1149.1 System Test Support SCANPSC110F SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port IEEE1149.1 System Test Support The SCANPSC110F Bridge extends the IEEE Std. test bus into a multidrop test bus environment. The advantage of a hierarchical approach over a single serial scan chain is improved test throughput and the ability to remove a board from the system and retain test access to the remaining modules. Each SCANPSC110F Bridge supports up to 3 local scan rings which can be accessed individually or combined serially. Addressing is accomplished by loading the instruction register with a value matching that of the Slot inputs. Backplane and inter-board testing can easily be accomplished by parking the local TAP Controllers in one of the stable TAP Controller states via a Park instruction. The 32-bit TCK counter enables built in self test operations to be performed on one port while other scan chains are simultaneously tested. s True IEEE1149.1 hierarchical and multidrop addressable capability s The 6 slot inputs support up to 59 unique addresses, a Broadcast Address, and 4 Multi-cast Group Addresses s 3 IEEE 1149.1-compatible configurable local scan ports s Mode Register allows local TAPs to be bypassed, selected for insertion into the scan chain individually, or serially in groups of two or three s 32-bit TCK counter s 16-bit LFSR Signature Compactor s L4 s local TAPs can be 3-stated via the OE input to allow an alternate test master to take control of the local TAPs Ordering Code: Order Number Package Number Package Description SCANPSC110FSC M28B 28-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names TCKB TMSB TDIB TDOB TRST Backplane Test Clock Input Backplane Test Mode Select Input Backplane Test Data Input Backplane Test Data Output Asynchronous Test Reset Input Active LOW S 0,5 OE Address Select Port Local Scan Port Output Enable Active LOW Local Port Test Clock Output Local Port Test Mode Select Output Local Port Test Data Input Local Port Test Data Output 2000 Fairchild Semiconductor Corporation DS011570 SCANPSC110F TABLE Glossary of Terms LFSR Linear Feedback Shift Register. When enabled, will generate a 16-bit signature of sampled serial test data. LSP Local Local Scan Port. A four signal port that drives a “local” i.e. non-backplane scan chain. e.g., TCKL1, TMSL1, TDOL1, TDIL1 Local is used to describe IEEE Std. compliant scan rings and the SCANPSC110F Bridge Test Access Port that drives them. The term “local” was adopted from the system test architecture that the SCANPSC110F Bridge will most commonly be used in namely, a system test backplane with a SCANPSC110F Bridge on each card driving up to 3 “local” scan rings per card. Each card can contain multiple SCANPSC110Fs, with 3 local scan ports per SCANPSC110F. Park/Unpark Park, parked, unpark, and unparked, are used to describe the state of the LSP controller and the state of the local TAP controllers the “local TAP controllers” refers to the TAP controllers of the scan compo- nents that make up a local scan ring . Park is also used to describe the action of parking a LSP transitioning into one of the Parked LSP controller states . It is important to understand that when a LSP controller is in one of the parked states, TMSL is held constant, thereby holding or “parking” the local TAP controllers in a given state. Test Access Port as defined by IEEE Std. Selected/Unselected Selected and Unselected refers to the state of the SCANPSC110F Bridge Selection Controller. A selected SCANPSC110F has been properly addressed and is ready to receive Level 2 protocol. Unselected SCANPSC110Fs monitor the system test backplane, but do not accept Level 2 protocol except for the GOTOWAIT instruction . The data registers and LSPs of unselected SCANPSC110Fs are not accessible from the system test master. Active Scan Chain The Active Scan Chain refers to the scan chain configuration as seen by the test master at a given moment. When a SCANPSC110F is selected with all of its LSPs parked, the active scan chain is the current scan bridge register only. When a LSP is unparked, the active scan chain becomes TDIB the current SCANPSC110F register the local scan ring registers a PAD bit TDOB. Refer to Table 4 for Unparked configurations of the LSP network. Level 1 Protocol Level 1 is the protocol used to address a SCANPSC110F. Level 2 Protocol Level 2 is the protocol that is used once a SCANPSC110F is selected. Level 2 protocol is IEEE Std. compliant when an individual SCANPSC110F is selected. A one bit register that is placed at the end of each local scan port scan-chain. The PAD bit eliminates the prop delay that would be added by the SCANPSC110F LSPN logic between TDILn and TDOL n+1 or TDOB by buffering and synchronizing the TDIL inputs to the falling edge of TCKB, thus allowing data to be scanned at higher frequencies without violating set-up and hold times. Least Significant Bit, the right-most position in a register bit 0 Most Significant Bit, the left-most position in a register SCANPSC110F TABLE Detailed Pin Description Table Name TMSB TDIB TDOB TCKB

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SCANPSC110F SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port IEEE1149.1 System Test Support

SCANPSC110F SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port IEEE1149.1 System Test Support

The SCANPSC110F Bridge extends the IEEE Std. test bus into a multidrop test bus environment. The advantage of a hierarchical approach over a single serial scan chain is improved test throughput and the ability to remove a board from the system and retain test access to the remaining modules. Each SCANPSC110F Bridge supports up to 3 local scan rings which can be accessed individually or combined serially. Addressing is accomplished by loading the instruction register with a value matching that of the Slot inputs. Backplane and inter-board testing can easily be accomplished by parking the local TAP Controllers in one of the stable TAP Controller states via a Park instruction. The 32-bit TCK counter enables built in self test operations to be performed on one port while other scan chains are simultaneously tested.
s True IEEE1149.1 hierarchical and multidrop addressable capability
s The 6 slot inputs support up to 59 unique addresses, a Broadcast Address, and 4 Multi-cast Group Addresses
s 3 IEEE 1149.1-compatible configurable local scan ports s Mode Register allows local TAPs to be bypassed,
selected for insertion into the scan chain individually, or serially in groups of two or three s 32-bit TCK counter s 16-bit LFSR Signature Compactor s L4 s local TAPs can be 3-stated via the OE input to allow an alternate test master to take control of the local TAPs
Ordering Code:

Order Number Package Number

Package Description

SCANPSC110FSC

M28B
28-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

Pin Names

TCKB TMSB TDIB TDOB TRST

Backplane Test Clock Input Backplane Test Mode Select Input Backplane Test Data Input Backplane Test Data Output Asynchronous Test Reset Input Active LOW

S 0,5 OE

Address Select Port Local Scan Port Output Enable Active LOW

Local Port Test Clock Output Local Port Test Mode Select Output Local Port Test Data Input Local Port Test Data Output
2000 Fairchild Semiconductor Corporation DS011570

SCANPSC110F

TABLE Glossary of Terms

LFSR

Linear Feedback Shift Register. When enabled, will generate a 16-bit signature of sampled serial test data.

LSP Local

Local Scan Port. A four signal port that drives a “local” i.e. non-backplane scan chain. e.g., TCKL1, TMSL1, TDOL1, TDIL1

Local is used to describe IEEE Std. compliant scan rings and the SCANPSC110F Bridge Test Access Port that drives them. The term “local” was adopted from the system test architecture that the SCANPSC110F Bridge will most commonly be used in namely, a system test backplane with a SCANPSC110F Bridge on each card driving up to 3 “local” scan rings per card. Each card can contain multiple SCANPSC110Fs, with 3 local scan ports per SCANPSC110F.

Park/Unpark

Park, parked, unpark, and unparked, are used to describe the state of the LSP controller and the state
of the local TAP controllers the “local TAP controllers” refers to the TAP controllers of the scan compo-
nents that make up a local scan ring . Park is also used to describe the action of parking a LSP transitioning into one of the Parked LSP controller states . It is important to understand that when a LSP
controller is in one of the parked states, TMSL is held constant, thereby holding or “parking” the local TAP controllers in a given state.

Test Access Port as defined by IEEE Std.

Selected/Unselected Selected and Unselected refers to the state of the SCANPSC110F Bridge Selection Controller. A selected SCANPSC110F has been properly addressed and is ready to receive Level 2 protocol. Unselected SCANPSC110Fs monitor the system test backplane, but do not accept Level 2 protocol except for the GOTOWAIT instruction . The data registers and LSPs of unselected SCANPSC110Fs are not accessible from the system test master.

Active Scan Chain

The Active Scan Chain refers to the scan chain configuration as seen by the test master at a given
moment. When a SCANPSC110F is selected with all of its LSPs parked, the active scan chain is the
current scan bridge register only. When a LSP is unparked, the active scan chain becomes TDIB the current SCANPSC110F register the local scan ring registers a PAD bit TDOB. Refer to Table 4 for Unparked configurations of the LSP network.

Level 1 Protocol

Level 1 is the protocol used to address a SCANPSC110F.

Level 2 Protocol

Level 2 is the protocol that is used once a SCANPSC110F is selected. Level 2 protocol is IEEE Std. compliant when an individual SCANPSC110F is selected.

A one bit register that is placed at the end of each local scan port scan-chain. The PAD bit eliminates
the prop delay that would be added by the SCANPSC110F LSPN logic between TDILn and TDOL n+1 or TDOB by buffering and synchronizing the TDIL inputs to the falling edge of TCKB, thus allowing data to be scanned at higher frequencies without violating set-up and hold times.

Least Significant Bit, the right-most position in a register bit 0

Most Significant Bit, the left-most position in a register

SCANPSC110F

TABLE Detailed Pin Description Table

Name TMSB

TDIB TDOB

TCKB

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Datasheet ID: SCANPSC110FSCX 634708