SCAN18374TSSCX

SCAN18374TSSCX Datasheet

SCAN18374T D-Type Flip-Flop with 3-STATE Outputs

Part	Datasheet
SCAN18374TSSCX	SCAN18374TSSCX (pdf)

Related Parts	Information
SCAN18374TSSC	SCAN18374TSSC

PDF Datasheet Preview
SCAN18374T D-Type Flip-Flop with 3-STATE Outputs SCAN18374T D-Type Flip-Flop with 3-STATE Outputs The SCAN18374T is a high speed, low-power D-type flipflop featuring separate D-type inputs organized into dual 9bit bytes with byte-oriented clock and output enable control signals. This device is compliant with IEEE Standard Test Access Port and BOUNDARY-SCAN Architecture with the incorporation of the defined BOUNDARYSCAN test logic and test access port consisting of Test Data Input TDI , Test Data Out TDO , Test Mode Select TMS , and Test Clock TCK . s IEEE JTAG Compliant s Buffered positive edge-triggered clock s 3-STATE outputs for bus-oriented applications s 9-bit data busses for parity applications s Reduced-swing outputs source 32 mA/sink 64 mA s Guaranteed to drive transmission line to TTL input levels of 0.8V and 2.0V s TTL compatible inputs s 25 mil pitch SSOP Shrink Small Outline Package s Includes CLAMP and HIGHZ instructions s Member of Fairchild’s SCAN Products Ordering Code: Order Number Package Number Package Description SCAN18374TSSC MS56A 56-Lead Shrink Small Outline Package SSOP , JEDEC MO-118, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names ACP, BCP AOE1, BOE1 Description Data Inputs Clock Pulse Inputs 3-STATE Output Enable Inputs 3-STATE Outputs Truth Tables Inputs AOE1 H L Inputs BOE1 H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = High Impedance = L-to-H Transition 2000 Fairchild Semiconductor Corporation DS010963 SCAN18374T Functional Description The SCAN18374 consists of two sets of nine edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable pins are common to all flip-flops. Each set of the nine flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the Logic Diagram LOW-to-HIGH Clock ACP or BCP transition. With the Output Enable AOE1 or BOE1 LOW, the contents of the nine flip-flops are available at the outputs. When the Output Enable is HIGH, the outputs go to the high impedance state. Operation of the Output Enable input does not affect the state of the flip-flops. Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Block Diagrams Byte-A Note BSR stands for Boundary Scan Register SCAN18374T Block Diagrams Continued Tap Controller Byte-B Note BSR stands for Boundary Scan Register SCAN18374T Description of Boundary-Scan Circuitry The scan cells used in the BOUNDARY-SCAN register are one of the following two types depending upon their location. Scan cell TYPE1 is intended to solely observe system data, while TYPE2 has the additional ability to control system data. Scan cell TYPE1 is located on each system input pin while scan cell TYPE2 is located at each system output pin as well as at each of the two internal active-high output enable signals. AOE controls the activity of the A-outputs while BOE controls the activity of the B-outputs. Each will activate their respective outputs by loading a logic high. The BYPASS register is a single bit shift register stage identical to scan cell TYPE1. It captures a fixed logic low. The two least significant bits of this captured value 01 are required by IEEE Std The upper six bits are unique to the SCAN18374T device. SCAN CMOS Test Access Logic devices do not include the IEEE optional identification register. Therefore, this unique captured value can be used as a “pseudo ID” code to confirm that the correct device is placed in the appropriate location in the boundary scan chain. Instruction Register Scan Chain Definition Bypass Register Scan Chain Definition Logic 0 The INSTRUCTION register is an eight-bit register which captures the value MSB LSB Instruction Code Instruction EXTEST SAMPLE/PRELOAD CLAMP

PDF Datasheet Preview

SCAN18374T D-Type Flip-Flop with 3-STATE Outputs

SCAN18374T D-Type Flip-Flop with 3-STATE Outputs

The SCAN18374T is a high speed, low-power D-type flipflop featuring separate D-type inputs organized into dual 9bit bytes with byte-oriented clock and output enable control signals. This device is compliant with IEEE Standard Test Access Port and BOUNDARY-SCAN Architecture with the incorporation of the defined BOUNDARYSCAN test logic and test access port consisting of Test Data Input TDI , Test Data Out TDO , Test Mode Select TMS , and Test Clock TCK .
s IEEE JTAG Compliant s Buffered positive edge-triggered clock s 3-STATE outputs for bus-oriented applications s 9-bit data busses for parity applications s Reduced-swing outputs source 32 mA/sink 64 mA s Guaranteed to drive transmission line to TTL input
levels of 0.8V and 2.0V s TTL compatible inputs s 25 mil pitch SSOP Shrink Small Outline Package s Includes CLAMP and HIGHZ instructions s Member of Fairchild’s SCAN Products
Ordering Code:

Order Number Package Number

Package Description

SCAN18374TSSC

MS56A
56-Lead Shrink Small Outline Package SSOP , JEDEC MO-118, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

Pin Names ACP, BCP AOE1, BOE1

Description Data Inputs Clock Pulse Inputs 3-STATE Output Enable Inputs 3-STATE Outputs

Truth Tables

Inputs

AOE1 H L

Inputs

BOE1

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
= High Impedance = L-to-H Transition
2000 Fairchild Semiconductor Corporation DS010963

SCAN18374T

Functional Description

The SCAN18374 consists of two sets of nine edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable pins are common to all flip-flops. Each set of the nine flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the

Logic Diagram

LOW-to-HIGH Clock ACP or BCP transition. With the Output Enable AOE1 or BOE1 LOW, the contents of the nine flip-flops are available at the outputs. When the Output Enable is HIGH, the outputs go to the high impedance state. Operation of the Output Enable input does not affect the state of the flip-flops.

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Block Diagrams

Byte-A

Note BSR stands for Boundary Scan Register

SCAN18374T

Block Diagrams Continued

Tap Controller

Byte-B

Note BSR stands for Boundary Scan Register

SCAN18374T

Description of Boundary-Scan Circuitry

The scan cells used in the BOUNDARY-SCAN register are one of the following two types depending upon their location. Scan cell TYPE1 is intended to solely observe system data, while TYPE2 has the additional ability to control system data.

Scan cell TYPE1 is located on each system input pin while scan cell TYPE2 is located at each system output pin as well as at each of the two internal active-high output enable signals. AOE controls the activity of the A-outputs while BOE controls the activity of the B-outputs. Each will activate their respective outputs by loading a logic high.

The BYPASS register is a single bit shift register stage identical to scan cell TYPE1. It captures a fixed logic low.

The two least significant bits of this captured value 01 are required by IEEE Std The upper six bits are unique to the SCAN18374T device. SCAN CMOS Test Access Logic devices do not include the IEEE optional identification register. Therefore, this unique captured value can be used as a “pseudo ID” code to confirm that the correct device is placed in the appropriate location in the boundary scan chain.

Instruction Register Scan Chain Definition

Bypass Register Scan Chain Definition Logic 0

The INSTRUCTION register is an eight-bit register which captures the value

MSB LSB

Instruction Code

Instruction

EXTEST SAMPLE/PRELOAD

CLAMP

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived SCAN18374TSSCX Datasheet file may be downloaded here without warranties.

Datasheet ID: SCAN18374TSSCX 634705