SCAN18373TSSC

SCAN18373TSSC Datasheet

SCAN18373T Transparent Latch with 3-STATE Outputs

Part	Datasheet
SCAN18373TSSC	SCAN18373TSSC (pdf)

Related Parts	Information
SCAN18373TSSCX	SCAN18373TSSCX

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SCAN18373T Transparent Latch with 3-STATE Outputs SCAN18373T Transparent Latch with 3-STATE Outputs The SCAN18373T is a high speed, low-power transparent latch featuring separate data inputs organized into dual 9bit bytes with byte-oriented latch enable and output enable control signals. This device is compliant with IEEE Standard Test Access Port and Boundary Scan Architecture with the incorporation of the defined boundary-scan test logic and test access port consisting of Test Data Input TDI , Test Data Out TDO , Test Mode Select TMS , and Test Clock TCK . s IEEE JTAG Compliant s Buffered active-low latch enable s 3-STATE outputs for bus-oriented applications s 9-bit data busses for parity applications s Reduced-swing outputs source 32 mA/sink 64 mA s Guaranteed to drive transmission line to TTL input levels of 0.8V and 2.0V s TTL compatible inputs s 25 mil pitch SSOP Shrink Small Outline Package s Includes CLAMP and HIGHZ instructions s Member of Fairchild’s SCAN Products Ordering Code: Order Number Package Number Package Description SCAN1837TSSC MS56A 56-Lead Shrink Small Outline Package SSOP , JEDEC MO-118, Wide Device also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names ALE, BLE AOE1, BOE1 Description Data Inputs Latch Enable Inputs 3-STATE Output Enable Inputs 3-STATE Latch Outputs Truth Tables ALE X H L Inputs AOE1 H L X L H X Inputs BOE1 H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance AO0 = Previous AO before H-to-L transition of ALE BO0 = Previous BO before H-to-L transition of BLE Z L H AO0 Z L H BO0 2000 Fairchild Semiconductor Corporation DS010962 SCAN18373T Functional Description The SCAN18373T consists of two sets of nine D-type latches with 3-STATE standard outputs. When the Latch Enable ALE or BLE input is HIGH, data on the inputs or enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its input changes. When Latch Enable is LOW, the latches store the information that was present on Logic Diagram the inputs a set-up time preceding the HIGH-to-LOW transition of the Latch Enable. The 3-STATE standard outputs are controlled by the Output Enable AOE1 or BOE1 input. When Output Enable is LOW, the standard outputs are in the 2-state mode. When Output Enable is HIGH, the standard outputs are in the high impedance mode, but this does not interfere with entering new data into the latches. Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Block Diagrams Byte-A SCAN18373T Block Diagrams Continued Tap Controller Byte-B Note BSR stands for Boundary Scan Register. SCAN18373T Description of Boundary-Scan Circuitry The scan cells used in the BOUNDARY-SCAN register are one of the following two types depending upon their location. Scan cell TYPE1 is intended to solely observe system data, while TYPE2 has the additional ability to control system data. Scan cell TYPE1 is located on each system input pin while scan cell TYPE2 is located at each system output pin as well as at each of the two internal active-high output enable signals. AOE controls the activity of the A-outputs while BOE controls the activity of the B-outputs. Each will activate their respective outputs by loading a logic high. The BYPASS register is a single bit shift register stage identical to scan cell TYPE1. It captures a fixed logic low. to the SCAN18373T device. SCAN CMOS Test Access Logic devices do not include the IEEE optional identification register. Therefore, this unique captured value can be used as a “pseudo ID” code to confirm that the correct device is placed in the appropriate location in the boundary scan chain. Instruction Register Scan Chain Definition Bypass Register Scan Chain Definition Logic 0 The INSTRUCTION register is an eight-bit register which captures the value The two least significant bits of this captured value 01 are required by IEEE Std The upper six bits are unique MSB LSB Instruction Code All Others Instruction EXTEST

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SCAN18373T Transparent Latch with 3-STATE Outputs

SCAN18373T Transparent Latch with 3-STATE Outputs

The SCAN18373T is a high speed, low-power transparent latch featuring separate data inputs organized into dual 9bit bytes with byte-oriented latch enable and output enable control signals. This device is compliant with IEEE Standard Test Access Port and Boundary Scan Architecture with the incorporation of the defined boundary-scan test logic and test access port consisting of Test Data Input TDI , Test Data Out TDO , Test Mode Select TMS , and Test Clock TCK .
s IEEE JTAG Compliant s Buffered active-low latch enable s 3-STATE outputs for bus-oriented applications s 9-bit data busses for parity applications s Reduced-swing outputs source 32 mA/sink 64 mA s Guaranteed to drive transmission line to TTL input
levels of 0.8V and 2.0V s TTL compatible inputs s 25 mil pitch SSOP Shrink Small Outline Package s Includes CLAMP and HIGHZ instructions s Member of Fairchild’s SCAN Products
Ordering Code:

Order Number Package Number

Package Description

SCAN1837TSSC

MS56A
56-Lead Shrink Small Outline Package SSOP , JEDEC MO-118, Wide
Device also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

Pin Names ALE, BLE AOE1, BOE1

Description Data Inputs Latch Enable Inputs 3-STATE Output Enable Inputs 3-STATE Latch Outputs

Truth Tables

ALE X H L

Inputs

AOE1 H L

X L H X

Inputs

BOE1

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance AO0 = Previous AO before H-to-L transition of ALE BO0 = Previous BO before H-to-L transition of BLE

Z L H AO0

Z L H BO0
2000 Fairchild Semiconductor Corporation DS010962

SCAN18373T

Functional Description

The SCAN18373T consists of two sets of nine D-type latches with 3-STATE standard outputs. When the Latch Enable ALE or BLE input is HIGH, data on the inputs or enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its input changes. When Latch Enable is LOW, the latches store the information that was present on

Logic Diagram
the inputs a set-up time preceding the HIGH-to-LOW transition of the Latch Enable. The 3-STATE standard outputs are controlled by the Output Enable AOE1 or BOE1 input. When Output Enable is LOW, the standard outputs are in the 2-state mode. When Output Enable is HIGH, the standard outputs are in the high impedance mode, but this does not interfere with entering new data into the latches.

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Block Diagrams

Byte-A

SCAN18373T

Block Diagrams Continued

Tap Controller

Byte-B

Note BSR stands for Boundary Scan Register.

SCAN18373T

Description of Boundary-Scan Circuitry

The scan cells used in the BOUNDARY-SCAN register are one of the following two types depending upon their location. Scan cell TYPE1 is intended to solely observe system data, while TYPE2 has the additional ability to control system data.

Scan cell TYPE1 is located on each system input pin while scan cell TYPE2 is located at each system output pin as well as at each of the two internal active-high output enable signals. AOE controls the activity of the A-outputs while BOE controls the activity of the B-outputs. Each will activate their respective outputs by loading a logic high.

The BYPASS register is a single bit shift register stage identical to scan cell TYPE1. It captures a fixed logic low.
to the SCAN18373T device. SCAN CMOS Test Access Logic devices do not include the IEEE optional identification register. Therefore, this unique captured value can be used as a “pseudo ID” code to confirm that the correct device is placed in the appropriate location in the boundary scan chain.

Instruction Register Scan Chain Definition

Bypass Register Scan Chain Definition Logic 0

The INSTRUCTION register is an eight-bit register which captures the value The two least significant bits of this captured value 01 are required by IEEE Std The upper six bits are unique

MSB LSB

Instruction Code All Others

Instruction EXTEST

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Datasheet ID: SCAN18373TSSC 634704