ORT8850H-1BM680C

ORT8850H-1BM680C Datasheet

ORT8850

Part	Datasheet
ORT8850H-1BM680C	ORT8850H-1BM680C (pdf)

Related Parts	Information
ORT8850H-1BMN680C	ORT8850H-1BMN680C
ORT8850H-1BMN680I	ORT8850H-1BMN680I
ORT8850L-3BMN680C	ORT8850L-3BMN680C
ORT8850L-2BMN680C	ORT8850L-2BMN680C
ORT8850L-1BMN680C	ORT8850L-1BMN680C
ORT8850L-2BMN680I	ORT8850L-2BMN680I
ORT8850L-1BMN680I	ORT8850L-1BMN680I
ORT8850H-2BMN680C	ORT8850H-2BMN680C
ORT8850L-1BM680I	ORT8850L-1BM680I
ORT8850L-1BM680C	ORT8850L-1BM680C
ORT8850H-2BM680C	ORT8850H-2BM680C
ORT8850L-2BM680C	ORT8850L-2BM680C
ORT8850H-1BM680I	ORT8850H-1BM680I
ORT8850L-3BM680C	ORT8850L-3BM680C
ORT8850L-2BM680I	ORT8850L-2BM680I

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ORT8850 Field-Programmable System Chip FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver February 2008 Data Sheet Introduction Field Programmable System-on-a-Chip FPSCs bring a whole new dimension to programmable logic Field Programmable Gate Array FPGA logic and an embedded system solution on a single device. Lattice has developed a solution for designers who need the many advantages of FPGA-based design implementation, coupled with highspeed serial backplane data transfer. Built on the Series 4 embedded System-on-a-Chip SoC architecture, the ORT8850 family is made up of backplane transceivers SERDES containing eight channels, each operating at up to 850 Mbits/s Gbits/s when all eight channels are used . This is combined with a full-duplex synchronous interface, with built-in Clock and Data Recovery CDR in standard-cell logic, along with over 600K usable FPGA system gates ORT8850H . With the addition of protocol and access logic such as protocol-independent framers, Asynchronous Transfer Mode ATM framers, Packet-over-SONET PoS interfaces, and framers for HDLC for Internet Protocol IP , designers can build a interface retaining proven backplane driver/receiver technology. Designers can also use the device to drive high-speed data transfer across buses within a system that are not SONET/SDH based. For example, designers can build a Gbits/s PCI-to-PCI half bridge using our PCI soft core. The ORT8850 family offers a clockless High-Speed Interface for inter-device communication on a board or across a backplane. The built-in clock recovery of the ORT8850 allows for higher system performance, easier-to-design clock domains in a multiboard system, and fewer signals on the backplane. Network designers will from the backplane transceiver as a network termination device. The backplane transceiver offers SONET scrambling/descrambling of data and streamlined SONET framing, pointer moving, and transport overhead handling, plus the programmable logic to terminate the network into proprietary systems. For non-SONET applications, all SONET functionality is hidden from the user and no prior networking knowledge is required. Table ORCA ORT8850 Family Available FPGA Logic equivalent to OR4E02 and OR4E06 respectively FPGA Max Device PFU Rows Columns Total PFUs User I/Os LUTs EBR Blocks FPGA EBR Bits System Gates K ORT8850L 4,992 201 - 397 ORT8850H 2,024 16,192 471 - 899 Note The embedded core, embedded system bus, FPGA interface and MPI are not included in the above gate counts. The System Gate ranges are derived from the following Minimum System Gates assumes 100% of the PFUs are used for logic only No PFU RAM with 40% EBR usage and 2 PLL's. Maximum System Gates assumes 80% of the PFUs are for logic, 20% are used for PFU RAM, with 80% EBR usage and 6 PLLs. 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The and information herein are subject to change without notice. ort8850_11.1 Lattice Semiconductor ORCA ORT8850 Data Sheet Table of Contents Introduction 1 Table of 2 Features 3 Embedded Core Features............................... 3 FPGA Features 4 Programmable Logic System Features........... 5 Description 6 What is an 6 FPSC 6 ispLEVER Development System..................... 7 FPSC Design Kit 7 FPGA Logic 8 System-Level Features 9 10 Additional Information 10 ORT8850 Overview 11 Embedded Core Overview 11 SONET Logic Blocks - Overview 12 System Considerations for Reference Clock 15 SONET Bypass Mode 16 STM Macrocells - Overview 17 HSI Macrocell - Overview.............................. 19 Supervisory and Test Support Features - Over- view 19 Protection Switching - Overview 21 FPSC Configuration - Overview 22 Backplane Transceiver Core Detailed Description 25 SONET Logic Blocks, Detailed Description 25 Receive Path Logic 34 FPGA/Embedded Core Interface Signals 47 Clock and Data Timing at the FPGA/Embedded Core Interface - SONET Block 49 Powerdown Mode 56 Protection 56 Memory Map 57 Registers Access and General Description... 57 Electrical 69 Absolute Maximum Ratings 69 Recommended Operating Conditions 69 Power Supply Decoupling LC Circuit 70 HSI Electrical and Timing Characteristics 71 Embedded Core LVDS I/O............................ 73 Pin Information 77 Package Pinouts 82 Package Thermal Characteristics Summary............ 100 qJA 100 YJC 100 qJB 100 FPSC Maximum Junction Temperature 101 Package Thermal Characteristics 101 Heat Sink 101 Package Coplanarity 101 Package 102 Package Outline Diagrams 102 Lattice Semiconductor ORCA ORT8850 Data Sheet Embedded Core Features • Implemented in an ORCA Series 4 FPGA. • Allows a wide range of high-speed backplane applications, including SONET transport and termination. • No knowledge of SONET/SDH needed in generic applications. Simply supply data, 78 MHz clock, and a frame pulse. • High-Speed Interface HSI function for clock/data recovery serial backplane data transfer without external clocks. • Eight-channel HSI function provides 850 Mbits/s serial interface per channel for a total chip bandwidth of Gbits/s full duplex . • HSI function uses Lattice’s 850 Mbits/s serial interface core. Rates from 126 Mbits/s to 850 Mbits/s are sup- ported. • LVDS I/Os compliant with support hot insertion. All embedded LVDS I/Os include both input and output on-board termination to allow long-haul driving of backplanes. • Low-power V HSI core. • Low-power LVDS buffers. • Programmable STS-3, and STS-12 framing. • Independent STS-3, and STS-12 data streams per quad channels. • 8:1 data multiplexing/demultiplexing for MHz byte-wide data processing in FPGA logic. • On-chip, Phase-Lock Loop PLL clock meets type B jitter tolerance of ITU-T recommendation G.958. • Powerdown option of HSI receiver on a per-channel basis. • HSI automatically recovers from loss-of-clock once its reference clock returns to normal operating state. • Frame alignment across multiple ORT8850 devices for work/protect switching at OC-192/STM-64 and above rates. • In-band management and through transport overhead extraction/insertion. • Supports transparent modes where either the only insertion is A1/A2 framing bytes, or no bytes are inserted. • Streamlined pointer processor pointer mover for 8 kHz frame alignment to system clocks. • Built-in boundry scan IEEE JTAG . • FIFOs align incoming data across all eight channels two groups of four channels or four groups of two channels for both SONET scrambling. Optional ability to bypass alignment FIFOs. • 1 + 1 protection supports STS-12/STS-48 redundancy by either software or hardware control for protection switching applications. STS-192 and above rates are supported through multiple devices. • ORCA FPGA soft intellectual property core support for a variety of applications. • Programmable Synchronous Transport Module STM pointer mover bypass mode. • Programmable STM framer bypass mode. • Programmable Clock and Data Recovery CDR bypass mode clocked LVDS High-Speed Interface . • Redundant outputs and multiplexed redundant inputs for CDR I/Os allow for implementation of eight channels with redundancy on a single device. Lattice Semiconductor ORCA ORT8850 Data Sheet FPGA Features • High-performance platform design µm 7-level metal technology. Internal performance of >250 MHz. Over 600K FPGA system gates ORT8850H . Meets multiple I/O interface standards. V operation 30% less power than V operation translates to greater performance. • Traditional I/O selections LVTTL 3.3V and LVCMOS V and V I/Os. Per pin-selectable I/O clamping diodes provide V PCI compliance. Individually programmable drive capability 24 mA sink/12 mA source, 12 mA sink/6 mA source, or 6 mA sink/3 mA source. Two slew rates supported fast and slew-limited . Fast-capture input latch and input for reduced input setup time and zero hold time. Fast open-drain drive capability. Capability to register 3-state enable signal. Off-chip clock drive capability. Two-input function generator in output path. • New programmable high-speed I/O Single-ended GTL, GTL+, PECL, SSTL3/2 class I & II , HSTL Class I, III, IV , ZBT, and DDR. Double-ended LVDS, bused-LVDS, LVPECL. LVDS include optional on-chip termination resistor per I/O and on-chip reference generation. • New capability to de multiplex I/O signals New Double-Data Rate DDR on both input and output at rates up to 350 MHz 700 Mbits/s effective rate . New 2x and 4x downlink and uplink capability per I/O i.e., 50 MHz internal to 200 MHz I/O . • Enhanced twin-quad Programmable Function Unit PFU Eight 16-bit Look-Up Tables LUTs per PFU. Nine user registers per PFU, one following each LUT, and organized to allow two nibbles to act independently, plus one extra for arithmetic operations. New register control in each PFU has two independent programmable clocks, clock enables, local SET/RESET, and data selects. New LUT structure allows combinations of LUT4, LUT5, new LUT6, 4 1 MUX, new 8 1 MUX, and ripple mode arithmetic functions in the same PFU. 32 x 4 RAM per PFU, as single- or dual-port. Create large, fast RAM/ROM blocks 128 x 8 in only eight PFUs using the SLIC decoders as bank drivers. Soft-Wired LUTs SWL allow fast cascading of up to three levels of LUT logic in a single PFU through fast internal routing, which reduces routing congestion and improves speed. Flexible fast access to PFU inputs from routing. Fast-carry logic and routing to all four adjacent PFUs for nibble-wide, byte-wide, or longer arithmetic functions, with the option to register the PFU carry-out. • Abundant high-speed buffered and nonbuffered routing resources provide 2x average speed improvements over previous architectures. • Hierarchical routing optimized for both local and global routing with dedicated routing resources. This results in faster routing times with predictable and performance. • SLIC provides eight 3-State Buffers, up to 10-bit decoder, and-OR-INVERT AOI in each programmable logic cell. • Improved built-in clock management with dual-output Programmable Phase-Locked Loops PPLLs provide optimum clock and conditioning for phase, frequency, and duty cycle from 15 MHz up to 420 MHz. Multiplication of the input frequency up to 64x, and division of the input frequency down to 1/64x possible. Lattice Semiconductor ORCA ORT8850 Data Sheet • New 200 MHz embedded quad-port RAM blocks, two read ports, two write ports, and two sets of byte lane enables. Each embedded RAM block can be as x 18 quad-port, two read/two write with optional built-in arbitration. x 36 dual-port, one read/one write . x 9 dual-port, one read/one write . x 9 dual-port, one read/one write for each . Two RAM with arbitrary number of words whose sum is 512 or less by 18 dual-port, one read/one write . Supports joining of RAM blocks. Two 16 x 8-bit Content Addressable Memory CAM support. FIFO 512 x 18, 256 x 36, 1K x 9, or dual 512 x Constant multiply 8 x 16 or 16 x Dual variable multiply 8 x • Embedded 32-bit internal system bus plus 4-bit parity interconnects FPGA logic, MicroProcessor Interface MPI , embedded RAM blocks, and embedded backplane transceiver blocks with 100 MHz bus performance. Included are built-in system registers that act as the control and status center for the device. • Built-in testability Full boundary scan IEEE and Draft JTAG . Programming and readback through boundary scan port compliant to IEEE Draft 1532:D1.7. TS_ALL testability function to 3-state all I/O pins. New temperature-sensing diode. • Cycle stealing capability allows a typical 15% to 40% internal speed improvement after place and route. This feature also supports compliance with many setup/hold and clock to out I/O and may provide reduced ground bounce for output buses by allowing delays of switching output buffers. Programmable Logic System Features • PCI local bus compliant for FPGA I/Os. • Improved PowerPC/Power QUICC MPC860 and PowerPC II MPC8260 high-speed synchronous MicroProcessor Interface can be used for readback, device control, and device status, as well as for a general-purpose interface to the FPGA logic, RAMs, and embedded backplane transceiver blocks. Glueless interface to synchronous PowerPC processors with address space provided. • New embedded AMBA AHB system bus ARM processor facilitates communication among the MicroProcessor Interface, logic, embedded block RAM, FPGA logic, and backplane transceiver logic. • New network PLLs meet ITU-T G.811 and provide clock conditioning for DS-1/E-1 and STS3/STM-1 applications. • Variable size bused readback of data capability with the built-in MicroProcessor Interface and system bus. • Internal, 3-state, and bidirectional buses with simple control provided by the SLIC. • New clock routing structures for global and local clocking increases speed and reduces skew <200 ps for OR4E04 . • New local clock routing structures allow creation of localized clock trees. Byte Ordering in SONET Frames The ORT8850 expects byte ordering in the SONET frames to be in the standard byte interleaved format per the GR-253 SONET standard. Byte ordering is the same in both the transmit and receive direction and treats the data as multiple STS-1 frames. When using the ORT8850 in STS-3 format both the transmitter and receiver device must be framed, based on STS-3 format. Likewise for the STS-12 format, both must operate in STS-12 format. Table Byte Ordering, STS-3 Format STS-3 A --> 3 2 1 STS-3 B --> 3 2 1 STS-3 C --> 3 2 1 STS-3 D --> 3 2 1 Table Byte Ordering, STS-12 Format STS-12 A --> 12 9 6 3 11 8 5 2 10 7 4 1 STS-12 B --> 12 9 6 3 11 8 5 2 10 7 4 1 STS-12 C --> 12 9 6 3 11 8 5 2 10 7 4 1 STS-12 D --> 12 9 6 3 11 8 5 2 10 7 4 1 Lattice Semiconductor ORCA ORT8850 Data Sheet Table Byte Ordering, Quad STS-12 OC-48 Format STS-12 A --> 12 9 6 3 11 8 5 2 10 7 4 1 STS-12 B --> 24 21 18 15 23 20 17 14 22 19 16 13 STS-12 C --> 36 33 30 27 35 32 29 26 34 31 28 25 STS-12 D --> 48 45 42 39 47 44 41 38 46 43 40 37 All internal framing is based on the system frame pulse SYS_FP which is a one-cycle pulse at an 8kHz rate. There is one system frame pulse for all 8 channels or both quads. When the framer receives the system frame pulse the individual overhead bytes are HSI Macrocell The ORT8850 High-Speed Interface HSI provides a physical medium for high-speed asynchronous serial data transfer between ASIC devices. The devices can be mounted on the same PC board or mounted on different boards and connected through the shelf back-plane. The ORT8850 CDR macro is an eight-channel Clock-Phase Select CPS and data retime function with serial-to-parallel demultiplexing for the incoming data stream and parallel-to-serial multiplexing for outgoing data. The ORT8850 uses an eight-channel HSI macro cell. The HSI macro consists of three functionally independent blocks receiver, transmitter, and PLL synthesizer. The PLL synthesizer block generates the necessary 850 MHz clock for operation from a MHz, reference. The PLL synthesizer block is a common asset shared by all eight receive and transmit channels. The PLL reference clock must match the interface frequency. The HSI_RX block receives differential 850 Mbits/s serial data without clock at its LVDS receiver input. Based on data transitions, the receiver selects an appropriate 850 MHz clock phase for each channel to retime the data. The retimed data and clock are then passed to the deMUX deserializer module. DeMUX module performs serial-toparallel conversion and provides the 106 Mbits/s data and clock. The HSI_TX block receives 106 Mbits/s parallel data at its input. MUX serializer module performs a parallel-toserial conversion using an 850 MHz clock provided by the PLL/synthesizer block. The resulting 850 Mbits/s serial data stream is then transmitted through the LVDS driver. The loopback feature built into the HSI macro provides looping of the transmitter data output into the receiver input when desired. All rate examples described here are the maximum rates possible. The actual HSI internal clock rate is determined by the provided reference clock rate. For example, if a MHz reference clock is provided, the HSI macro will operate at 622 Mbits/s. Transmit Path Logic In the transmit direction each STM quad will receive frame aligned streams of STS-12 data maximum of four streams per quad from the FPGA logic. The transmitter receives data interface in a parallel 8-bit format. A common frame pulse for all 8 channels is provided as an input from the FPGA logic to the transmit SONET block. The system frame pulse is a single pulse at the reference clock rate every 9720 clock cycles. For a MHz reference clock this creates an 8KHz pulse rate. The system frame pulse SYS_FP is used to generate the A1/A2 in the transmit direction. It is also used by the Pointer Mover Block to perform the line side loopback, which otherwise uses the LINE_FP frame pulse also provided by the user from the FPGA to the Embeddded ASIC Block. The Function of the LINE_FP is mentioned in the Pointer Mover bypass description. The system frame pulse is common to all channels in the transmit direction. Once it is received from the FPGA logic, the data to be transmitted goes through the following processing steps: • A parity check is performed on the data • The Transport Overhead TOH data is optional Lattice Semiconductor ORCA ORT8850 Data Sheet • A1 and A2 framing bits are inserted errored bits may optionally be inserted • The bit interleaved parity bit B1 for the previously transmitted frame is inserted • The data is scrambled using the standard STS-12 polynomial optional • A parallel to serial conversion is performed on the data • The serial data is broadcast to the work and protect LVDS buffers These processing steps are described in more detail in the following sections. A block diagram of the transmit path logic is shown in Figure All processing except the parallel to serial conversion is optional. If all processing except the SERDES is deselected, the device is said to be operating in the "bypass" mode. Figure Basic Logic Blocks, Transmit Path, Single Channel FPGA Logic TX_TOH_CK_EN TOH_Inxx DINxx [7:0] 8 DINxx _PAR Note xx=[AA, Embedded Core SONET Logic TOH Serial To Parallel Convert from control registers Insert A1A2 Error Insert B1 Error Prev. B1 Hold B1 Calc. Parity TOH A1A2 B1 Repeater Check Insert for opt. opt. opt. STS 3 Odd or Even from control register Scrambler optional Parallel To Serial Convert 622 MHz I/O MUXs And LVDS Buffers This table is constructed to show the correct values when read and written via the system bus MPI interface. When using this table while interfacing with the system bus user logic master interface, the data values will need to be byte This is due to the opposite orientation of the MPI and master interface bus ordering. More information on this can be found in the MPI/System Bus Application Note TN1017 . Lattice Semiconductor ORCA ORT8850 Data Sheet Table Memory Map Descriptions 0x Absolute Address 30000 30001 30002 Bit Type [0:7] [0:7] [0:7] Name - 30003 [0:7] R/W scratch pad 30004 [0:7] R/W lockreg MSB 30005 [0:7] R/W lockreg LSB 30006 [0] R/W [1-7] 30007 [0:7] Device Register Blocks global reset Not Used Not Used LVDS loopback control 30008 Not Used Not Used LVDS Protection Switch enable TOH RX serial enable [5-7] Not Used Reset Value 0x 05 80 00 00 0 00 The scratch pad has no function and is not used anywhere in the core. However, this register can be written to and read from for debugging purposes. Ordering Information Figure Part Number Description ORT8850X - X XXX X Device Family ORT8850L ORT8850H Speed Grade Package Type BM = Fine-Pitch Plastic Ball Grid Array PBGAM BMN = Lead-Free Fine-Pitch Plastic Ball Grid Array PBGAM Grade C = Commercial I = Industrial Ball Count Table Device Type Options Device ORT8850L ORT8850H Voltage V internal V/2.5 V/1.8 V/1.5 V I/O V internal V/2.5 V/1.8 V/1.5 V I/O Table Temperature Range Symbol C I Description Commercial Industrial Ambient Temperature 0 to +70 to +85 Junction Temperature 0 to +85 to +100 Table Conventional Packaging Commercial Ordering Information1 Device Family ORT8850L ORT8850H Part Number ORT8850L-3BM680C ORT8850L-2BM680C ORT8850L-1BM680C ORT8850H-2BM680C ORT8850H-1BM680C Speed Grade 3 2 1 2 1 Package Type PBGAM fpBGA PBGAM fpBGA PBGAM fpBGA PBGAM fpBGA PBGAM fpBGA Ball Count Grade C Table Conventional Packaging Industrial Ordering Information1 Device Family ORT8850L ORT8850H Part Number ORT8850L-2BM680I ORT8850L-1BM680I ORT8850H-1BM680I Speed Grade Package Type PBGAM fpBGA PBGAM fpBGA PBGAM fpBGA Ball Count Grade I 1.For all but the slowest commercial speed grade, the speed grades on these devices are dual marked. For example, the commercial speed grade is also marked with the industrial grade The commercial grade is always one speed grade faster than the associated dual mark industrial grade. The slowest commercial speed grade is marked as commercial grade only. Lattice Semiconductor ORCA ORT8850 Data Sheet Table Lead-Free Packaging Commercial Ordering Information1 Device Family ORT8850L ORT8850H Part Number ORT8850L-3BMN680C ORT8850L-2BMN680C ORT8850L-1BMN680C ORT8850H-2BMN680C ORT8850H-1BMN680C Speed Grade 3 2 1 2 1 Package Type Lead-Free PBGAM fpBGA Lead-Free PBGAM fpBGA Lead-Free PBGAM fpBGA Lead-Free PBGAM fpBGA Lead-Free PBGAM fpBGA Ball Count Grade C Table Lead-Free Packaging Industrial Ordering Information1 Device Family ORT8850L ORT8850H Part Number ORT8850L-2BMN680I ORT8850L-1BMN680I ORT8850H-1BMN680I Speed Grade Package Type Lead-Free PBGAM fpBGA Lead-Free PBGAM fpBGA Lead-Free PBGAM fpBGA Ball Count Grade I 1.For all but the slowest commercial speed grade, the speed grades on these devices are dual marked. For example, the commercial speed grade is also marked with the industrial grade The commercial grade is always one speed grade faster than the associated dual mark industrial grade. The slowest commercial speed grade is marked as commercial grade only. January 2004 August 2004 October 2005 April 2006 February 2008 Version 8 9 10 Change Summary Previous Lattice releases. Added lead-free package designator. Added lead-free package ordering part numbers OPNs . Added to the STM Pointer Mover bypass. Added to the signal description for LINE_FP. Added to the B1, section bit interleavered parity BIP-8 byte. Added to B1 processing. Corrected name of Register 30009, Bits 5 & 6 in Memory Map Description table.

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ORT8850

Field-Programmable System Chip FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver

February 2008

Data Sheet

Introduction

Field Programmable System-on-a-Chip FPSCs bring a whole new dimension to programmable logic Field Programmable Gate Array FPGA logic and an embedded system solution on a single device. Lattice has developed a solution for designers who need the many advantages of FPGA-based design implementation, coupled with highspeed serial backplane data transfer. Built on the Series 4 embedded System-on-a-Chip SoC architecture, the ORT8850 family is made up of backplane transceivers SERDES containing eight channels, each operating at up to 850 Mbits/s Gbits/s when all eight channels are used . This is combined with a full-duplex synchronous interface, with built-in Clock and Data Recovery CDR in standard-cell logic, along with over 600K usable FPGA system gates ORT8850H . With the addition of protocol and access logic such as protocol-independent framers, Asynchronous Transfer Mode ATM framers, Packet-over-SONET PoS interfaces, and framers for HDLC for Internet Protocol IP , designers can build a interface retaining proven backplane driver/receiver technology. Designers can also use the device to drive high-speed data transfer across buses within a system that are not SONET/SDH based. For example, designers can build a Gbits/s PCI-to-PCI half bridge using our PCI soft core.

The ORT8850 family offers a clockless High-Speed Interface for inter-device communication on a board or across a backplane. The built-in clock recovery of the ORT8850 allows for higher system performance, easier-to-design clock domains in a multiboard system, and fewer signals on the backplane. Network designers will from the backplane transceiver as a network termination device. The backplane transceiver offers SONET scrambling/descrambling of data and streamlined SONET framing, pointer moving, and transport overhead handling, plus the programmable logic to terminate the network into proprietary systems. For non-SONET applications, all SONET functionality is hidden from the user and no prior networking knowledge is required.

Table ORCA ORT8850 Family Available FPGA Logic equivalent to OR4E02 and OR4E06 respectively

FPGA Max

Device PFU Rows Columns Total PFUs User I/Os LUTs

EBR Blocks

FPGA

EBR Bits System

Gates K

ORT8850L
4,992
201 - 397

ORT8850H
2,024
16,192
471 - 899

Note The embedded core, embedded system bus, FPGA interface and MPI are not included in the above gate counts. The System Gate ranges are derived from the following Minimum System Gates assumes 100% of the PFUs are used for logic only No PFU RAM with 40% EBR usage and 2 PLL's. Maximum System Gates assumes 80% of the PFUs are for logic, 20% are used for PFU RAM, with 80% EBR usage and 6 PLLs.
2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other
brand or product names are trademarks or registered trademarks of their respective holders. The and information herein are subject to change without
notice.
ort8850_11.1

Lattice Semiconductor

ORCA ORT8850 Data Sheet

Table of Contents

Introduction 1 Table of 2 Features 3

Embedded Core Features............................... 3 FPGA Features 4 Programmable Logic System Features........... 5 Description 6 What is an 6 FPSC 6 ispLEVER Development System..................... 7 FPSC Design Kit 7 FPGA Logic 8 System-Level Features 9 10 Additional Information 10 ORT8850 Overview 11 Embedded Core Overview 11 SONET Logic Blocks - Overview 12 System Considerations for Reference Clock
15 SONET Bypass Mode 16 STM Macrocells - Overview 17 HSI Macrocell - Overview.............................. 19 Supervisory and Test Support Features - Over-
view 19 Protection Switching - Overview 21 FPSC Configuration - Overview 22 Backplane Transceiver Core Detailed Description 25 SONET Logic Blocks, Detailed Description 25 Receive Path Logic 34 FPGA/Embedded Core Interface Signals 47 Clock and Data Timing at the FPGA/Embedded

Core Interface - SONET Block 49 Powerdown Mode 56 Protection 56 Memory Map 57 Registers Access and General Description... 57 Electrical 69 Absolute Maximum Ratings 69 Recommended Operating Conditions 69 Power Supply Decoupling LC Circuit 70 HSI Electrical and Timing Characteristics 71 Embedded Core LVDS I/O............................ 73 Pin Information 77 Package Pinouts 82

Package Thermal Characteristics Summary............ 100 qJA 100 YJC 100 qJB 100 FPSC Maximum Junction Temperature 101 Package Thermal Characteristics 101 Heat Sink 101 Package Coplanarity 101

Package 102 Package Outline Diagrams 102
Lattice Semiconductor

ORCA ORT8850 Data Sheet

Embedded Core Features
• Implemented in an ORCA Series 4 FPGA.
• Allows a wide range of high-speed backplane applications, including SONET transport and termination.
• No knowledge of SONET/SDH needed in generic applications. Simply supply data, 78 MHz clock,
and a frame pulse.
• High-Speed Interface HSI function for clock/data recovery serial backplane data transfer without external
clocks.
• Eight-channel HSI function provides 850 Mbits/s serial interface per channel for a total chip bandwidth of

Gbits/s full duplex .
• HSI function uses Lattice’s 850 Mbits/s serial interface core. Rates from 126 Mbits/s to 850 Mbits/s are sup-
ported.
• LVDS I/Os compliant with support hot insertion. All embedded LVDS I/Os include both input and output
on-board termination to allow long-haul driving of backplanes.
• Low-power V HSI core.
• Low-power LVDS buffers.
• Programmable STS-3, and STS-12 framing.
• Independent STS-3, and STS-12 data streams per quad channels.
• 8:1 data multiplexing/demultiplexing for MHz byte-wide data processing in FPGA logic.
• On-chip, Phase-Lock Loop PLL clock meets type B jitter tolerance of ITU-T recommendation

G.958.
• Powerdown option of HSI receiver on a per-channel basis.
• HSI automatically recovers from loss-of-clock once its reference clock returns to normal operating state.
• Frame alignment across multiple ORT8850 devices for work/protect switching at OC-192/STM-64 and above
rates.
• In-band management and through transport overhead extraction/insertion.
• Supports transparent modes where either the only insertion is A1/A2 framing bytes, or no bytes are inserted.
• Streamlined pointer processor pointer mover for 8 kHz frame alignment to system clocks.
• Built-in boundry scan IEEE JTAG .
• FIFOs align incoming data across all eight channels two groups of four channels or four groups of two channels
for both SONET scrambling. Optional ability to bypass alignment FIFOs.
• 1 + 1 protection supports STS-12/STS-48 redundancy by either software or hardware control for protection
switching applications. STS-192 and above rates are supported through multiple devices.
• ORCA FPGA soft intellectual property core support for a variety of applications.
• Programmable Synchronous Transport Module STM pointer mover bypass mode.
• Programmable STM framer bypass mode.
• Programmable Clock and Data Recovery CDR bypass mode clocked LVDS High-Speed Interface .
• Redundant outputs and multiplexed redundant inputs for CDR I/Os allow for implementation of eight channels
with redundancy on a single device.

Lattice Semiconductor

ORCA ORT8850 Data Sheet

FPGA Features
• High-performance platform design µm 7-level metal technology. Internal performance of >250 MHz. Over 600K FPGA system gates ORT8850H . Meets multiple I/O interface standards. V operation 30% less power than V operation translates to greater performance.
• Traditional I/O selections LVTTL 3.3V and LVCMOS V and V I/Os. Per pin-selectable I/O clamping diodes provide V PCI compliance. Individually programmable drive capability 24 mA sink/12 mA source, 12 mA sink/6 mA source, or 6 mA sink/3 mA source. Two slew rates supported fast and slew-limited . Fast-capture input latch and input for reduced input setup time and zero hold time. Fast open-drain drive capability. Capability to register 3-state enable signal. Off-chip clock drive capability. Two-input function generator in output path.
• New programmable high-speed I/O Single-ended GTL, GTL+, PECL, SSTL3/2 class I & II , HSTL Class I, III, IV , ZBT, and DDR. Double-ended LVDS, bused-LVDS, LVPECL. LVDS include optional on-chip termination resistor per I/O and on-chip reference generation.
• New capability to de multiplex I/O signals New Double-Data Rate DDR on both input and output at rates up to 350 MHz 700 Mbits/s effective rate . New 2x and 4x downlink and uplink capability per I/O i.e., 50 MHz internal to 200 MHz I/O .
• Enhanced twin-quad Programmable Function Unit PFU Eight 16-bit Look-Up Tables LUTs per PFU. Nine user registers per PFU, one following each LUT, and organized to allow two nibbles to act independently, plus one extra for arithmetic operations. New register control in each PFU has two independent programmable clocks, clock enables, local SET/RESET, and data selects. New LUT structure allows combinations of LUT4, LUT5, new LUT6, 4 1 MUX, new 8 1 MUX, and ripple mode arithmetic functions in the same PFU. 32 x 4 RAM per PFU, as single- or dual-port. Create large, fast RAM/ROM blocks 128 x 8 in only eight PFUs using the SLIC decoders as bank drivers. Soft-Wired LUTs SWL allow fast cascading of up to three levels of LUT logic in a single PFU through fast internal routing, which reduces routing congestion and improves speed. Flexible fast access to PFU inputs from routing. Fast-carry logic and routing to all four adjacent PFUs for nibble-wide, byte-wide, or longer arithmetic functions, with the option to register the PFU carry-out.
• Abundant high-speed buffered and nonbuffered routing resources provide 2x average speed improvements over previous architectures.
• Hierarchical routing optimized for both local and global routing with dedicated routing resources. This results in faster routing times with predictable and performance.
• SLIC provides eight 3-State Buffers, up to 10-bit decoder, and-OR-INVERT AOI in each programmable logic cell.
• Improved built-in clock management with dual-output Programmable Phase-Locked Loops PPLLs provide optimum clock and conditioning for phase, frequency, and duty cycle from 15 MHz up to 420 MHz. Multiplication of the input frequency up to 64x, and division of the input frequency down to 1/64x possible.

Lattice Semiconductor

ORCA ORT8850 Data Sheet
• New 200 MHz embedded quad-port RAM blocks, two read ports, two write ports, and two sets of byte lane enables. Each embedded RAM block can be as x 18 quad-port, two read/two write with optional built-in arbitration. x 36 dual-port, one read/one write . x 9 dual-port, one read/one write . x 9 dual-port, one read/one write for each . Two RAM with arbitrary number of words whose sum is 512 or less by 18 dual-port, one read/one write . Supports joining of RAM blocks. Two 16 x 8-bit Content Addressable Memory CAM support. FIFO 512 x 18, 256 x 36, 1K x 9, or dual 512 x Constant multiply 8 x 16 or 16 x Dual variable multiply 8 x
• Embedded 32-bit internal system bus plus 4-bit parity interconnects FPGA logic, MicroProcessor Interface MPI , embedded RAM blocks, and embedded backplane transceiver blocks with 100 MHz bus performance. Included are built-in system registers that act as the control and status center for the device.
• Built-in testability Full boundary scan IEEE and Draft JTAG . Programming and readback through boundary scan port compliant to IEEE Draft 1532:D1.7. TS_ALL testability function to 3-state all I/O pins. New temperature-sensing diode.
• Cycle stealing capability allows a typical 15% to 40% internal speed improvement after place and route. This feature also supports compliance with many setup/hold and clock to out I/O and may provide reduced ground bounce for output buses by allowing delays of switching output buffers.

Programmable Logic System Features
• PCI local bus compliant for FPGA I/Os.
• Improved PowerPC/Power QUICC MPC860 and PowerPC II MPC8260 high-speed synchronous MicroProcessor Interface can be used for readback, device control, and device status, as well as for a general-purpose interface to the FPGA logic, RAMs, and embedded backplane transceiver blocks. Glueless interface to synchronous PowerPC processors with address space provided.
• New embedded AMBA AHB system bus ARM processor facilitates communication among the MicroProcessor Interface, logic, embedded block RAM, FPGA logic, and backplane transceiver logic.
• New network PLLs meet ITU-T G.811 and provide clock conditioning for DS-1/E-1 and STS3/STM-1 applications.
• Variable size bused readback of data capability with the built-in MicroProcessor Interface and system bus.
• Internal, 3-state, and bidirectional buses with simple control provided by the SLIC.
• New clock routing structures for global and local clocking increases speed and reduces skew <200 ps for OR4E04 .
• New local clock routing structures allow creation of localized clock trees.
Byte Ordering in SONET Frames The ORT8850 expects byte ordering in the SONET frames to be in the standard byte interleaved format per the GR-253 SONET standard. Byte ordering is the same in both the transmit and receive direction and treats the data as multiple STS-1 frames. When using the ORT8850 in STS-3 format both the transmitter and receiver device must be framed, based on STS-3 format. Likewise for the STS-12 format, both must operate in STS-12 format.
Table Byte Ordering, STS-3 Format

STS-3 A --> 3 2 1 STS-3 B --> 3 2 1 STS-3 C --> 3 2 1 STS-3 D --> 3 2 1
Table Byte Ordering, STS-12 Format

STS-12 A --> 12 9 6 3 11 8 5 2 10 7 4 1 STS-12 B --> 12 9 6 3 11 8 5 2 10 7 4 1 STS-12 C --> 12 9 6 3 11 8 5 2 10 7 4 1 STS-12 D --> 12 9 6 3 11 8 5 2 10 7 4 1

Lattice Semiconductor

ORCA ORT8850 Data Sheet
Table Byte Ordering, Quad STS-12 OC-48 Format

STS-12 A --> 12 9 6 3 11 8 5 2 10 7 4 1 STS-12 B --> 24 21 18 15 23 20 17 14 22 19 16 13 STS-12 C --> 36 33 30 27 35 32 29 26 34 31 28 25 STS-12 D --> 48 45 42 39 47 44 41 38 46 43 40 37

All internal framing is based on the system frame pulse SYS_FP which is a one-cycle pulse at an 8kHz rate. There is one system frame pulse for all 8 channels or both quads. When the framer receives the system frame pulse the individual overhead bytes are

HSI Macrocell The ORT8850 High-Speed Interface HSI provides a physical medium for high-speed asynchronous serial data transfer between ASIC devices. The devices can be mounted on the same PC board or mounted on different boards and connected through the shelf back-plane. The ORT8850 CDR macro is an eight-channel Clock-Phase Select CPS and data retime function with serial-to-parallel demultiplexing for the incoming data stream and parallel-to-serial multiplexing for outgoing data. The ORT8850 uses an eight-channel HSI macro cell. The HSI macro consists of three functionally independent blocks receiver, transmitter, and PLL synthesizer.

The PLL synthesizer block generates the necessary 850 MHz clock for operation from a MHz, reference. The PLL synthesizer block is a common asset shared by all eight receive and transmit channels. The PLL reference clock must match the interface frequency.

The HSI_RX block receives differential 850 Mbits/s serial data without clock at its LVDS receiver input. Based on data transitions, the receiver selects an appropriate 850 MHz clock phase for each channel to retime the data. The retimed data and clock are then passed to the deMUX deserializer module. DeMUX module performs serial-toparallel conversion and provides the 106 Mbits/s data and clock.

The HSI_TX block receives 106 Mbits/s parallel data at its input. MUX serializer module performs a parallel-toserial conversion using an 850 MHz clock provided by the PLL/synthesizer block. The resulting 850 Mbits/s serial data stream is then transmitted through the LVDS driver.

The loopback feature built into the HSI macro provides looping of the transmitter data output into the receiver input when desired.

All rate examples described here are the maximum rates possible. The actual HSI internal clock rate is determined by the provided reference clock rate. For example, if a MHz reference clock is provided, the HSI macro will operate at 622 Mbits/s.

Transmit Path Logic In the transmit direction each STM quad will receive frame aligned streams of STS-12 data maximum of four streams per quad from the FPGA logic. The transmitter receives data interface in a parallel 8-bit format. A common frame pulse for all 8 channels is provided as an input from the FPGA logic to the transmit SONET block.

The system frame pulse is a single pulse at the reference clock rate every 9720 clock cycles. For a MHz reference clock this creates an 8KHz pulse rate. The system frame pulse SYS_FP is used to generate the A1/A2 in the transmit direction. It is also used by the Pointer Mover Block to perform the line side loopback, which otherwise uses the LINE_FP frame pulse also provided by the user from the FPGA to the Embeddded ASIC Block. The Function of the LINE_FP is mentioned in the Pointer Mover bypass description.

The system frame pulse is common to all channels in the transmit direction. Once it is received from the FPGA logic, the data to be transmitted goes through the following processing steps:
• A parity check is performed on the data
• The Transport Overhead TOH data is optional

Lattice Semiconductor

ORCA ORT8850 Data Sheet
• A1 and A2 framing bits are inserted errored bits may optionally be inserted
• The bit interleaved parity bit B1 for the previously transmitted frame is inserted
• The data is scrambled using the standard STS-12 polynomial optional
• A parallel to serial conversion is performed on the data
• The serial data is broadcast to the work and protect LVDS buffers These processing steps are described in more detail in the following sections. A block diagram of the transmit path logic is shown in Figure All processing except the parallel to serial conversion is optional. If all processing except the SERDES is deselected, the device is said to be operating in the "bypass" mode.

Figure Basic Logic Blocks, Transmit Path, Single Channel

FPGA Logic

TX_TOH_CK_EN TOH_Inxx

DINxx [7:0] 8 DINxx _PAR Note xx=[AA,

Embedded Core

SONET Logic

TOH Serial

To Parallel Convert
from control registers

Insert A1A2 Error

Insert B1

Error

Prev. B1 Hold

B1 Calc.

Parity TOH A1A2 B1 Repeater Check Insert for
opt. opt. opt. STS 3

Odd or Even from control
register

Scrambler optional

Parallel To

Serial Convert
622 MHz

I/O MUXs And LVDS

Buffers
This table is constructed to show the correct values when read and written via the system bus MPI interface. When using this table while interfacing with the system bus user logic master interface, the data values will need to be byte This is due to the opposite orientation of the MPI and master interface bus ordering. More information on this can be found in the MPI/System Bus Application Note TN1017 .

Lattice Semiconductor

ORCA ORT8850 Data Sheet

Table Memory Map Descriptions
0x Absolute Address
30000
30001
30002

Bit Type
[0:7]
[0:7]
[0:7]

Name -
30003
[0:7] R/W
scratch pad
30004
[0:7] R/W
lockreg MSB
30005
[0:7] R/W
lockreg LSB
30006
[0] R/W
[1-7]
30007
[0:7]

Device Register Blocks
global reset

Not Used Not Used

LVDS loopback control
30008

Not Used Not Used

LVDS Protection Switch enable

TOH RX serial enable
[5-7]

Not Used

Reset Value 0x
05 80 00
00 0 00

The scratch pad has no function and is not used anywhere in the core. However, this register can be written to and read from for debugging purposes.
Ordering Information

Figure Part Number Description

ORT8850X - X XXX X

Device Family ORT8850L ORT8850H Speed Grade

Package Type BM = Fine-Pitch Plastic Ball Grid Array PBGAM BMN = Lead-Free Fine-Pitch Plastic Ball Grid Array PBGAM

Grade C = Commercial I = Industrial

Ball Count

Table Device Type Options

Device ORT8850L ORT8850H

Voltage

V internal V/2.5 V/1.8 V/1.5 V I/O

V internal V/2.5 V/1.8 V/1.5 V I/O

Table Temperature Range

Symbol C I

Description Commercial

Industrial

Ambient Temperature 0 to +70
to +85

Junction Temperature 0 to +85
to +100
Table Conventional Packaging Commercial Ordering Information1

Device Family ORT8850L

ORT8850H

Part Number ORT8850L-3BM680C ORT8850L-2BM680C ORT8850L-1BM680C ORT8850H-2BM680C ORT8850H-1BM680C

Speed Grade
3 2 1 2 1

Package Type PBGAM fpBGA PBGAM fpBGA PBGAM fpBGA PBGAM fpBGA PBGAM fpBGA

Ball Count

Grade C
Table Conventional Packaging Industrial Ordering Information1

Device Family ORT8850L

ORT8850H

Part Number ORT8850L-2BM680I ORT8850L-1BM680I ORT8850H-1BM680I

Speed Grade

Package Type PBGAM fpBGA PBGAM fpBGA PBGAM fpBGA

Ball Count

Grade I
1.For all but the slowest commercial speed grade, the speed grades on these devices are dual marked. For example, the commercial speed grade is also marked with the industrial grade The commercial grade is always one speed grade faster than the associated dual mark industrial grade. The slowest commercial speed grade is marked as commercial grade only.

Lattice Semiconductor

ORCA ORT8850 Data Sheet
Table Lead-Free Packaging Commercial Ordering Information1

Device Family ORT8850L

ORT8850H

Part Number ORT8850L-3BMN680C ORT8850L-2BMN680C ORT8850L-1BMN680C ORT8850H-2BMN680C ORT8850H-1BMN680C

Speed Grade
3 2 1 2 1

Package Type Lead-Free PBGAM fpBGA Lead-Free PBGAM fpBGA Lead-Free PBGAM fpBGA Lead-Free PBGAM fpBGA Lead-Free PBGAM fpBGA

Ball Count

Grade C
Table Lead-Free Packaging Industrial Ordering Information1

Device Family ORT8850L

ORT8850H

Part Number ORT8850L-2BMN680I ORT8850L-1BMN680I ORT8850H-1BMN680I

Speed Grade

Package Type Lead-Free PBGAM fpBGA Lead-Free PBGAM fpBGA Lead-Free PBGAM fpBGA

Ball Count

Grade I
1.For all but the slowest commercial speed grade, the speed grades on these devices are dual marked. For example, the commercial speed grade is also marked with the industrial grade The commercial grade is always one speed grade faster than the associated dual mark industrial grade. The slowest commercial speed grade is marked as commercial grade only.

January 2004 August 2004 October 2005

April 2006

February 2008

Version 8 9 10
Change Summary Previous Lattice releases. Added lead-free package designator. Added lead-free package ordering part numbers OPNs . Added to the STM Pointer Mover bypass. Added to the signal description for LINE_FP. Added to the B1, section bit interleavered parity BIP-8 byte. Added to B1 processing. Corrected name of Register 30009, Bits 5 & 6 in Memory Map Description table.

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Datasheet ID: ORT8850H-1BM680C 645496