NDP7050L / NDB7050L N-Channel Logic Level Enhancement Mode Field Effect Transistor
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March 1996 NDP7050L / NDB7050L N-Channel Logic Level Enhancement Mode Field Effect Transistor These logic level N-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulses in the avalanche and commutation modes. These devices are particularly suited for low voltage applications such as automotive, DC/DC converters, PWM motor controls, and other battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed. 75A, 50V, RDS ON = VGS = 5V Low drive requirements allowing operation directly from logic drivers. VGS TH < 2.0V. Critical DC electrical parameters specified at elevated temperature. Rugged internal source-drain diode can eliminate the need for an external Zener diode transient suppressor. 175°C maximum junction temperature rating. High density cell design for extremely low RDS ON . TO-220 and TO-263 D2PAK package for both through hole and surface mount applications. Absolute Maximum Ratings Symbol Parameter TC = 25°C unless otherwise noted NDP7050L VDSS Drain-Source Voltage VDGR Drain-Gate Voltage RGS < 1 VGSS Gate-Source Voltage - Continuous - Nonrepetitive tP < 50 µs Drain Current - Continuous - Pulsed Total Power Dissipation TC = 25°C Derate above 25°C TJ,TSTG Operating and Storage Temperature Range 50 ± 20 ± 40 75 225 150 1 -65 to 175 NDB7050L Units V W/°C 1997 Fairchild Semiconductor Corporation NDP7050L.SAM Electrical Characteristics TC = 25°C unless otherwise noted Symbol Parameter Conditions DRAIN-SOURCE AVALANCHE RATINGS Note 1 W DSS Single Pulse Drain-Source Avalanche Energy VDD = 25 V, ID = 75 A Maximum Drain-Source Avalanche Current OFF CHARACTERISTICS BVDSS IDSS Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current |
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