84321AYLFT

84321AYLFT Datasheet

ICS84321

Part	Datasheet
84321AYLFT	84321AYLFT (pdf)

Related Parts	Information
84321AYLF	84321AYLF

PDF Datasheet Preview
ICS84321 260MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER The ICS84321 is a general purpose, dual output Crystal-to3.3V Differential LVPECL High Frequency Synthesizer. The ICS84321 has a selectable TEST_CLK or crystal inputs. The VCO operates at a frequency range of 620MHz to 780MHz. The VCO frequency is programmed in steps equal to the value of the input reference or crystal frequency. The VCO and output frequency can be programmed using the serial or parallel interfaces to the logic. • Dual differential 3.3V LVPECL outputs • Selectable crystal oscillator interface or LVCMOS/LVTTL TEST_CLK • Output frequency range 103.3MHz to 260MHz • Crystal input frequency range 14MHz to 40MHz • VCO range 620MHz to 780MHz • Parallel or serial interface for programming counter and output dividers • RMS period jitter 3ps typical • RMS phase jitter at 155.52MHz, using a 38.88MHz crystal 12kHz to 20MHz 2.5ps typical Phase noise 155.52MHz Offset Noise Power 100Hz dBc/Hz 1kHz dBc/Hz 10kHz dBc/Hz 100kHz dBc/Hz • 3.3V supply voltage • 0°C to 70°C ambient operating temperature • Lead-Free package RoHS compliant • Use replacement part 8T49N004-dddNLGI BLOCK DIAGRAM PIN ASSIGNMENT 84321AY FUNCTIONAL DESCRIPTION NOTE The functional description that follows describes operation using a 25MHz crystal. Valid PLL loop divider values for different crystal or input frequencies are in the Input Frequency Characteristics, Table 5, NOTE The ICS84321 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A fundamental crystal is used as the input to the on-chip oscillator. The output of the oscillator is fed into the phase detector. A 25MHz crystal provides a 25MHz phase detector reference frequency. The VCO of the PLL operates over a range of 620MHz to 780MHz. The output of the M divider is also applied to the phase detector. The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M either too high or too low , the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle. The programmable features of the ICS84321 support two input modes to program the M divider and N output divider. The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel mode, the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 and N1 is passed directly to the M divider and N output divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW transition on nP_LOAD or until a serial event occurs. As a result, the M and N bits can be hardwired to set ICS84321 260MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER the M divider and N output divider to a default state that will automatically occur during power-up. The TEST output is LOW when operating in the parallel input mode. The relationship between the VCO frequency, the crystal frequency and the M divider is as follows: fVCO = fxtal x M The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table. Valid M values for which the PLL will achieve lock for a 25MHz reference are as 25 M The frequency out is as follows: FOUT = fVCO = fxtal x M Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output divider on each rising edge of S_CLOCK. The serial mode can be used to program the M and N bits and test bits T1 and T0. The internal registers T0 and T1 determine the state of the TEST output as follows: TABLE ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 84321AYLF ICS84321AYLF 32 Lead “Lead-Free” LQFP tray 0°C to 70°C 84321AYLFT ICS84321AYLF 32 Lead “Lead-Free” LQFP tape & reel 0°C to 70°C NOTE Parts that are ordered with an “LF” to the part number are the Pb-Free and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc. IDT assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. 84321AY ICS84321 260MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER Description of Change 1 Features section - RMS period jitter bullet, corrected typo from 2.5ps to 3ps. 10/8/03 1 Features section - add Lead-Free bullet. 10 Updated LVPECL Output Termination drawings. 17 Ordering Information table - added Lead-Free part number. 2/11/05 1 2 7 17 Removed sentence from General Description. Updated Figure Crystal Characteristics Table - added Drive Level. Ordering Information Table - added Lead-Free note. Rename XTAL1/2 to XTAL_IN/XTAL_OUT throughout the datasheet. 6/9/05 LVPECL DC Characteristics Table -corrected VOH max. from VCCO - 1.0V to VCCO 13 - 14 - 0.9V. Power Considerations - corrected power dissipation to VOH max in Table 4/10/07 Updated datasheet’s header/footer with IDT from ICS. 17 Removed ICS from Part/Order Number column. Added LF marking. 19 Added Contact Page. 7/27/10 Product Discontinuation Notice - Last Time Buy Expires OCTOBER 28, 2014 PDN# CQ-13-03 11/6/13 17 Ordering Information - removed leaded devices per PDN CQ-13-03 2/25/15 84321AY ICS84321 260MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER We’ve Got Your Timing Solution. 6024 Silver Creek Valley Road San Jose, CA 95138 Sales 800-345-7015 inside USA +408-284-8200 outside USA Fax 408-284-2775 Tech Support 2015 Integrated Device Technology, Inc. All rights reserved. Product subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA 84321AY

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ICS84321
260MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

The ICS84321 is a general purpose, dual output Crystal-to3.3V Differential LVPECL High Frequency Synthesizer. The ICS84321 has a selectable TEST_CLK or crystal inputs. The VCO operates at a frequency range of 620MHz to 780MHz. The VCO frequency is programmed in steps equal to the value of the input reference or crystal frequency. The VCO and output frequency can be programmed using the serial or parallel interfaces to the logic.
• Dual differential 3.3V LVPECL outputs
• Selectable crystal oscillator interface or LVCMOS/LVTTL TEST_CLK
• Output frequency range 103.3MHz to 260MHz
• Crystal input frequency range 14MHz to 40MHz
• VCO range 620MHz to 780MHz
• Parallel or serial interface for programming counter and output dividers
• RMS period jitter 3ps typical
• RMS phase jitter at 155.52MHz, using a 38.88MHz crystal 12kHz to 20MHz 2.5ps typical

Phase noise 155.52MHz

Offset

Noise Power
100Hz dBc/Hz
1kHz dBc/Hz
10kHz dBc/Hz
100kHz dBc/Hz
• 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
• Lead-Free package RoHS compliant
• Use replacement part 8T49N004-dddNLGI

BLOCK DIAGRAM

PIN ASSIGNMENT
84321AY

FUNCTIONAL DESCRIPTION

NOTE The functional description that follows describes operation using a 25MHz crystal. Valid PLL loop divider values for different crystal or input frequencies are in the Input Frequency Characteristics, Table 5, NOTE

The ICS84321 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A fundamental crystal is used as the input to the on-chip oscillator. The output of the oscillator is fed into the phase detector. A 25MHz crystal provides a 25MHz phase detector reference frequency. The VCO of the PLL operates over a range of 620MHz to 780MHz. The output of the M divider is also applied to the phase detector.

The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M either too high or too low , the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle.

The programmable features of the ICS84321 support two input modes to program the M divider and N output divider. The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel mode, the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 and N1 is passed directly to the M divider and N output divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW transition on nP_LOAD or until a serial event occurs. As a result, the M and N bits can be hardwired to set

ICS84321
260MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
the M divider and N output divider to a default state that will automatically occur during power-up. The TEST output is LOW when operating in the parallel input mode. The relationship between the VCO frequency, the crystal frequency and the M divider is as follows:
fVCO = fxtal x M

The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function

Table. Valid M values for which the PLL will achieve lock for a
25MHz reference are as 25 M The frequency
out is as follows:

FOUT = fVCO = fxtal x M

Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output divider on each rising edge of S_CLOCK. The serial mode can be used to program the M and N bits and test bits T1 and T0. The internal registers T0 and T1 determine the state of the TEST output as follows:
TABLE ORDERING INFORMATION

Part/Order Number

Marking

Package

Shipping Packaging Temperature
84321AYLF

ICS84321AYLF
32 Lead “Lead-Free” LQFP
tray
0°C to 70°C
84321AYLFT

ICS84321AYLF
32 Lead “Lead-Free” LQFP
tape & reel
0°C to 70°C

NOTE Parts that are ordered with an “LF” to the part number are the Pb-Free and are RoHS compliant.

While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc. IDT assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
84321AY

ICS84321
260MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

Description of Change
1 Features section - RMS period jitter bullet, corrected typo from 2.5ps to 3ps.
10/8/03
1 Features section - add Lead-Free bullet. 10 Updated LVPECL Output Termination drawings. 17 Ordering Information table - added Lead-Free part number.
2/11/05
1 2 7 17
Removed sentence from General Description. Updated Figure Crystal Characteristics Table - added Drive Level. Ordering Information Table - added Lead-Free note. Rename XTAL1/2 to XTAL_IN/XTAL_OUT throughout the datasheet.
6/9/05

LVPECL DC Characteristics Table -corrected VOH max. from VCCO - 1.0V to VCCO
13 - 14 - 0.9V.

Power Considerations - corrected power dissipation to VOH max in Table 4/10/07

Updated datasheet’s header/footer with IDT from ICS. 17 Removed ICS from Part/Order Number column. Added LF marking. 19 Added Contact Page.
7/27/10

Product Discontinuation Notice - Last Time Buy Expires OCTOBER 28, 2014 PDN# CQ-13-03
11/6/13
17 Ordering Information - removed leaded devices per PDN CQ-13-03
2/25/15
84321AY

ICS84321
260MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

We’ve Got Your Timing Solution.
6024 Silver Creek Valley Road San Jose, CA 95138

Sales 800-345-7015 inside USA +408-284-8200 outside USA Fax 408-284-2775

Tech Support
2015 Integrated Device Technology, Inc. All rights reserved. Product subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA
84321AY

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived 84321AYLFT Datasheet file may be downloaded here without warranties.

Datasheet ID: 84321AYLFT 637115