NDH8304P

NDH8304P Datasheet

NDH8304P Dual P-Channel Enhancement Mode Field Effect Transistor

Part	Datasheet
NDH8304P	NDH8304P (pdf)

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NDH8304P Dual P-Channel Enhancement Mode Field Effect Transistor May 1997 SuperSOTTM-8 P-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as notebook computer power management and other battery powered circuits where fast high-side switching, and low in-line power loss are needed in a very small outline surface mount package. A, -20 V. RDS ON = VGS = V RDS ON = VGS = V. Proprietary SuperSOTTM-8 package design using copper lead frame for superior thermal and electrical capabilities. High density cell design for extremely low RDS ON . Exceptional on-resistance and maximum DC current capability. Absolute Maximum Ratings TA = 25°C unless otherwise noted Symbol Parameter VDSS Drain-Source Voltage VGSS Gate-Source Voltage Drain Current - Continuous - Pulsed Note 1 Maximum Power Dissipation Note 1 TJ,TSTG Operating and Storage Temperature Range THERMAL CHARACTERISTICS Thermal Resistance, Junction-to-Ambient Note 1 Thermal Resistance, Junction-to-Case Note 1 1997 Fairchild Semiconductor Corporation NDH8304P -20 ±8 -10 -55 to 150 156 40 Units V A W °C °C/W °C/W ELECTRICAL CHARACTERISTICS TA = 25°C unless otherwise noted Symbol Parameter Conditions OFF CHARACTERISTICS BVDSS IDSS Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current VGS = 0 V, ID = -250 µA VDS = -16 V, VGS = 0 V IGSSF Gate - Body Leakage, Forward IGSSR ON CHARACTERISTICS Note 2 VGS th Gate Threshold Voltage VGS = 8 V, VDS = 0 V VGS = -8 V, VDS= 0 V

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NDH8304P Dual P-Channel Enhancement Mode Field Effect Transistor

May 1997

SuperSOTTM-8 P-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as notebook computer power management and other battery powered circuits where fast high-side switching, and low in-line power loss are needed in a very small outline surface mount package.

A, -20 V. RDS ON = VGS = V RDS ON = VGS = V.

Proprietary SuperSOTTM-8 package design using copper lead frame for superior thermal and electrical capabilities.

High density cell design for extremely low RDS ON .

Exceptional on-resistance and maximum DC current capability.

Absolute Maximum Ratings TA = 25°C unless otherwise noted Symbol Parameter

VDSS

Drain-Source Voltage

VGSS

Gate-Source Voltage

Drain Current - Continuous
- Pulsed

Note 1

Maximum Power Dissipation

Note 1

TJ,TSTG Operating and Storage Temperature Range THERMAL CHARACTERISTICS

Thermal Resistance, Junction-to-Ambient Note 1

Thermal Resistance, Junction-to-Case Note 1
1997 Fairchild Semiconductor Corporation

NDH8304P -20 ±8 -10
-55 to 150
156 40

Units V A

W °C
°C/W °C/W

ELECTRICAL CHARACTERISTICS TA = 25°C unless otherwise noted

Symbol Parameter

Conditions

OFF CHARACTERISTICS

BVDSS IDSS

Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current

VGS = 0 V, ID = -250 µA VDS = -16 V, VGS = 0 V

IGSSF

Gate - Body Leakage, Forward

IGSSR

ON CHARACTERISTICS Note 2

VGS th

Gate Threshold Voltage

VGS = 8 V, VDS = 0 V VGS = -8 V, VDS= 0 V

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Datasheet ID: NDH8304P 634594