MM74C922N

MM74C922N Datasheet

MM74C922<br>• MM74C923 16-Key Encoder<br>• 20-Key Encoder

Part	Datasheet
MM74C922N	MM74C922N (pdf)

Related Parts	Information
MM74C923N	MM74C923N
MM74C922WM	MM74C922WM
MM74C923WMX	MM74C923WMX
MM74C922WMX	MM74C922WMX
MM74C923WM	MM74C923WM

PDF Datasheet Preview
MM74C922 • MM74C923 16-Key Encoder • 20-Key Encoder MM74C922 • MM74C923 16-Key Encoder • 20-Key Encoder The MM74C922 and MM74C923 CMOS key encoders provide all the necessary logic to fully encode an array of SPST switches. The keyboard scan can be implemented by either an external clock or external capacitor. These encoders also have on-chip pull-up devices which permit switches with up to 50 on resistance to be used. No diodes in the switch array are needed to eliminate ghost switches. The internal debounce circuit needs only a single external capacitor and can be defeated by omitting the capacitor. A Data Available output goes to a high level when a valid keyboard entry has been made. The Data Available output returns to a low level when the entered key is released, even if another key is depressed. The Data Available will return high to indicate acceptance of the new key after a normal debounce period this two-key roll-over is provided between any two switches. An internal register remembers the last key pressed even after the key is released. The 3-STATE outputs provide for easy expansion and bus operation and are LPTTL compatible. s 50 maximum switch on resistance s On or off chip clock s On-chip row pull-up devices s 2 key roll-over s Keybounce elimination with single capacitor s Last key register at outputs s 3-STATE output LPTTL compatible s Wide supply range 3V to 15V s Low power consumption Ordering Code: Order Number Package Number Package Description MM74C922WM M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide MM74C922N N18B 18-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide MM74C923WM M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide MM74C923N N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagrams Pin Assignment for DIP Pin Assignment for SOIC Top View MM74C922 2001 Fairchild Semiconductor Corporation DS006037 Top View MM74C922 MM74C922 • MM74C923 Connection Diagrams Continued Pin Assignment for DIP and SOIC Package Top View MM74C923 Truth Tables Pins 0 through 11 Switch Position Y1, X1 Y1, X2 Y1, X3 Y1, X4 Y2, X1 Y2, X2 Y2, X3 Y2, X4 8 Y3, X1 9 Y3, X2 10 Y3, X3 11 Y3, X4 TB AC OD U E Note 1 0 Pins 12 through 19 Switch Position Y4, X1 13 Y4, X2 14 Y4, X3 15 Y4, X4 Y5 Note 1 , X1 Y5 Note 1 , X2 Y5 Note 1 , X3 Y5 Note 1 , X4 U E Note 1 0 Note 1 Omit for MM74C922 MM74C922 • MM74C923 Block Diagram MM74C922 • MM74C923 Absolute Maximum Ratings Note 2 Voltage at Any Pin VCC − 0.3V to V CC + 0.3V Operating Temperature Range MM74C922, MM74C923

PDF Datasheet Preview

MM74C922
• MM74C923 16-Key Encoder
• 20-Key Encoder

MM74C922
• MM74C923 16-Key Encoder
• 20-Key Encoder

The MM74C922 and MM74C923 CMOS key encoders provide all the necessary logic to fully encode an array of SPST switches. The keyboard scan can be implemented by either an external clock or external capacitor. These encoders also have on-chip pull-up devices which permit switches with up to 50 on resistance to be used. No diodes in the switch array are needed to eliminate ghost switches. The internal debounce circuit needs only a single external capacitor and can be defeated by omitting the capacitor. A Data Available output goes to a high level when a valid keyboard entry has been made. The Data Available output returns to a low level when the entered key is released, even if another key is depressed. The Data Available will return high to indicate acceptance of the new key after a normal debounce period this two-key roll-over is provided between any two switches.

An internal register remembers the last key pressed even after the key is released. The 3-STATE outputs provide for easy expansion and bus operation and are LPTTL compatible.
s 50 maximum switch on resistance s On or off chip clock s On-chip row pull-up devices s 2 key roll-over s Keybounce elimination with single capacitor s Last key register at outputs s 3-STATE output LPTTL compatible s Wide supply range 3V to 15V s Low power consumption
Ordering Code:

Order Number Package Number

Package Description

MM74C922WM

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide

MM74C922N

N18B
18-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide

MM74C923WM

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide

MM74C923N

N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagrams

Pin Assignment for DIP

Pin Assignment for SOIC

Top View MM74C922
2001 Fairchild Semiconductor Corporation DS006037

Top View MM74C922

MM74C922
• MM74C923

Connection Diagrams Continued

Pin Assignment for DIP and SOIC Package

Top View MM74C923

Truth Tables

Pins 0 through 11

Switch

Position

Y1, X1 Y1, X2 Y1, X3 Y1, X4 Y2, X1 Y2, X2

Y2, X3 Y2, X4
8 Y3, X1
9 Y3, X2
10 Y3, X3
11 Y3, X4

TB AC OD

U E Note 1 0

Pins 12 through 19

Switch

Position

Y4, X1
13 Y4, X2
14 Y4, X3
15 Y4, X4

Y5 Note 1 , X1 Y5 Note 1 , X2 Y5 Note 1 , X3 Y5 Note 1 , X4

U E Note 1 0

Note 1 Omit for MM74C922

MM74C922
• MM74C923

Block Diagram

MM74C922
• MM74C923

Absolute Maximum Ratings Note 2

Voltage at Any Pin

VCC − 0.3V to V CC + 0.3V

Operating Temperature Range

MM74C922, MM74C923

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Datasheet ID: MM74C922N 634367