ML6554 3A Bus Termination Regulator
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ML6554CUX (pdf) |
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ML6554IU |
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ML6554CU |
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ML6554IUX |
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ML6554 3A Bus Termination Regulator February 2005 ML6554 3A Bus Termination Regulator • Can source and sink up to 3A, no heat sink required • Integrated Power MOSFETs • Generates termination voltages for DDR SDRAM, SSTL-2 SDRAM, SGRAM, or equivalent memories • Generates termination voltages for active termination schemes for DDR SDRAM, GTL+, Rambus, VME, LV-TTL, HSTL, PECL and other high speed logic • VREF input available for external voltage divider • Separate voltages for VCCQ and PVDD • Buffered VREF output • VOUT of ±3% or less at 3A • Minimum external components • Shutdown for standby or suspend mode operation • 0° to +70°C and -40° to +85°C temperature ranges available • Thermal Shutdown 130°C Block Diagram The ML6554 switching regulator is designed to convert voltage supplies ranging from 2.3V to 4V into a desired output voltage or termination voltage for various applications. The ML6554 can be implemented to produce regulated output voltages in two different modes. In the default mode, when the VREF pin is open, the ML6554 output voltage is 50% of the voltage applied to VCCQ. The ML6554 can also be used to produce various voltages by forcing a voltage on the VREFIN pin. In this case, the output voltage follows the input VREFIN voltage. The switching regulator is capable of sourcing or sinking up to 3A of current while regulating an output VTT voltage to within 3% or less. The ML6554, used in conjunction with series termination resisitors, provides an excellent voltage source for active termination schemes of high speed transmission lines as those seen in high speed memory buses and distributed backplane designs. The voltage output of the regulator can be used as a termination voltage for other bus interface standards such as DDR SDRAM, SSTL, CMOS, Rambus , GTL+, VME, LV-CMOS, LV-TTL, HSTL and PECL. VCCQ AVCC VREFOUT VREFIN 11 AGND 13 + VREF BUFFER OSCILLATOR/ RAMP GENERATOR ERROR AMP + VFB 10 1 VDD 9 VDD 12 SHDN PVDD1 PVDD2 VL1 VOUT RAMP COMPARATOR 6 VL2 VOUT DGND 8 PGND1 PGND2 2005 Fairchild Semiconductor Corporation ML6554 3A Bus Termination Regulator ML6554 16-Pin PSOP U16 VDD PVDD1 VL1 PGND1 PGND2 VL2 PVDD2 DGND TOP VIEW AVCC VCCQ VREFOUT AGND SHDN VREFIN VFB VDD Pin Description Pin Name Function Digital supply voltage PVDD1 Voltage supply for internal power transistors Output voltage/ inductor connection PGND1 Ground for output power transistors Ordering Information ML6554CU ML6554IU Temperature Range 0°C to 70°C -40°C to +85°C Package 16-Pin PSOP U16 16-Pin PSOP U16 ML6554 3A Bus Termination Regulator TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx IntelliMAX ActiveArray FASTr ISOPLANAR Power247 Stealth Bottomless FPS LittleFET PowerEdge SuperFET CoolFET FRFET MICROCOUPLER PowerSaver SuperSOT -3 CROSSVOLT GlobalOptoisolator MicroFET SuperSOT -6 DOME MicroPak SuperSOT -8 EcoSPARK HiSeC MICROWIRE SyncFET E2CMOS QT Optoelectronics EnSigna i-Lo MSXPro Quiet Series TINYOPTO FACT ImpliedDisconnect OCX RapidConfigure |
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