GTLP6C817MTC

GTLP6C817MTC Datasheet

GTLP6C817 Low Drive GTLP/LVTTL 1:6 Clock Driver

Part	Datasheet
GTLP6C817MTC	GTLP6C817MTC (pdf)

Related Parts	Information
GTLP6C817MTCX	GTLP6C817MTCX

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GTLP6C817 Low Drive GTLP/LVTTL 1:6 Clock Driver GTLP6C817 Low Drive GTLP/LVTTL 1:6 Clock Driver The GTLP6C817 is a low drive clock driver that provides TTL to GTLP signal level translation and vice versa . The device provides a high speed interface between cards operating at TTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP’s reduced output swing <1V , reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transceiver logic GTL JEDEC standard JESD8-3. Fairchild’s GTLP has internal edge-rate control and is process, voltage, and temperature PVT compensated. Its function is similar to BTL and GTL but with different output levels and receiver threshold. GTLP output LOW level is typically less than 0.5V, the output level HIGH is 1.5V and the receiver threshold is 1.0V. s Interface between LVTTL and GTLP logic levels s Designed with edge rate control circuitry to reduce out- put noise on the GTLP port s VREF pin provides external supply reference voltage for receiver threshold adjustibility s Special PVT compensation circuitry to provide consis- tent performance over variations of process, supply voltage and temperature s TTL compatible driver and control inputs s Designed using Fairchild advanced CMOS technology s Bushold data inputs on A port to eliminate the need for external pull-up resistors for unused inputs s Power up/down and power off high impedance for live insertion s 5V over voltage tolerance on LVTTL ports s Open drain on GTLP to support wired-or connection s A Port source/sink −12mA/+12mA s B Port sink +40mA s 1:6 fanout clock driver for TTL port s 1:2 fanout clock driver for GTLP port Ordering Code: Order Number Package Number Package Description GTLP6C817MTC MTC24 24-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide Device is also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pin Descriptions Connection Diagram Pin Names TTLIN, GTLPIN Clock Inputs TTL and GTLP respectively Output Enable Active LOW GTLP Port TTL Levels VCCT.GNDT VCC GNDG VREF Output Enable Active LOW TTL Port TTL Levels LVTTL Output Supplies 3V Internal Circuitry VCC 5V OBn GTLP Output Grounds Voltage Reference Input TTL Buffered Clock Outputs GTLP Buffered Clock Outputs 2000 Fairchild Semiconductor Corporation DS500246 GTLP6C817 Functional Description The GTLP6C817 is a low drive clock driver providing LVTTL-to-GTLP clock translation, and GTLP-to-LVTTL clock translation in the same package. The LVTTL-to-GTLP direction is a 1:2 clock driver path with a single Enable pin OEB . For the GTLP-to-LVTTL direction the clock receiver path is a 1:6 buffer with a single Enable control OEA . Data polarity is inverting for both directions. Truth Tables Inputs TTLIN H L X OEB L H Outputs OBn L H High Z Logic Diagram Inputs GTLPIN H L X OEA L H Outputs OAn L H High Z GTLP6C817 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Voltage VI DC Output Voltage VO Outputs 3-STATE Outputs Active Note 2 DC Output Sink Current into OA Port IOL DC Output Source Current from OA Port IOH DC Output Sink Current into OB Port in the LOW State IOL DC Input Diode Current IIK VI < 0V DC Output Diode Current IOK VO < 0V VO > VCC ESD Rating Storage Temperature TSTG −0.5V to +7.0V −0.5V to +7.0V −0.5V to +7.0V −0.5V to +7.0V 24 mA −24 mA 80 mA −50 mA −50 mA +50 mA > 2000V −65°C to +150°C

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GTLP6C817 Low Drive GTLP/LVTTL 1:6 Clock Driver

GTLP6C817 Low Drive GTLP/LVTTL 1:6 Clock Driver

The GTLP6C817 is a low drive clock driver that provides TTL to GTLP signal level translation and vice versa . The device provides a high speed interface between cards operating at TTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP’s reduced output swing <1V , reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transceiver logic GTL JEDEC standard JESD8-3.

Fairchild’s GTLP has internal edge-rate control and is process, voltage, and temperature PVT compensated. Its function is similar to BTL and GTL but with different output levels and receiver threshold. GTLP output LOW level is typically less than 0.5V, the output level HIGH is 1.5V and the receiver threshold is 1.0V.
s Interface between LVTTL and GTLP logic levels s Designed with edge rate control circuitry to reduce out-
put noise on the GTLP port s VREF pin provides external supply reference voltage for
receiver threshold adjustibility s Special PVT compensation circuitry to provide consis-
tent performance over variations of process, supply voltage and temperature s TTL compatible driver and control inputs s Designed using Fairchild advanced CMOS technology s Bushold data inputs on A port to eliminate the need for external pull-up resistors for unused inputs s Power up/down and power off high impedance for live insertion s 5V over voltage tolerance on LVTTL ports s Open drain on GTLP to support wired-or connection s A Port source/sink −12mA/+12mA s B Port sink +40mA s 1:6 fanout clock driver for TTL port s 1:2 fanout clock driver for GTLP port
Ordering Code:

Order Number Package Number

Package Description

GTLP6C817MTC

MTC24
24-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
Device is also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Pin Descriptions

Connection Diagram

Pin Names

TTLIN, GTLPIN Clock Inputs TTL and GTLP respectively

Output Enable Active LOW GTLP Port TTL Levels

VCCT.GNDT VCC GNDG VREF

Output Enable Active LOW TTL Port TTL Levels LVTTL Output Supplies 3V Internal Circuitry VCC 5V OBn GTLP Output Grounds Voltage Reference Input TTL Buffered Clock Outputs GTLP Buffered Clock Outputs
2000 Fairchild Semiconductor Corporation DS500246

GTLP6C817

Functional Description

The GTLP6C817 is a low drive clock driver providing LVTTL-to-GTLP clock translation, and GTLP-to-LVTTL clock translation in the same package. The LVTTL-to-GTLP direction is a 1:2 clock driver path with a single Enable pin OEB . For the GTLP-to-LVTTL direction the clock receiver path is a 1:6 buffer with a single Enable control OEA . Data polarity is inverting for both directions.

Truth Tables

Inputs

TTLIN H L X

OEB L H

Outputs OBn L H High Z

Logic Diagram

Inputs

GTLPIN H L X

OEA L H

Outputs OAn L H High Z

GTLP6C817

Absolute Maximum Ratings Note 1

Supply Voltage VCC DC Input Voltage VI DC Output Voltage VO

Outputs 3-STATE

Outputs Active Note 2

DC Output Sink Current into

OA Port IOL DC Output Source Current
from OA Port IOH DC Output Sink Current into

OB Port in the LOW State IOL DC Input Diode Current IIK

VI < 0V DC Output Diode Current IOK

VO < 0V VO > VCC ESD Rating

Storage Temperature TSTG
−0.5V to +7.0V −0.5V to +7.0V
−0.5V to +7.0V −0.5V to +7.0V
24 mA
−24 mA
80 mA
−50 mA
−50 mA +50 mA > 2000V −65°C to +150°C

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Datasheet ID: GTLP6C817MTC 633863