ADP3193AJCPZ-RL

ADP3193AJCPZ-RL Datasheet

8-Bit, Programmable, 2- to 3-Phase, Synchronous Buck Controller ADP3193A

Part	Datasheet
ADP3193AJCPZ-RL	ADP3193AJCPZ-RL (pdf)

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8-Bit, Programmable, 2- to 3-Phase, Synchronous Buck Controller ADP3193A Selectable 2- or 3-phase operation at up to 1 MHz per phase mV worst-case differential sensing error over temperature Logic-level PWM outputs for interface to external high power drivers Fast enhanced PWM FEPWM flex mode for excellent load transient performance Active current balancing between all output phases Built-in power-good/crowbar blanking supports on-the-fly VID code changes Digitally programmable V to V output supports both VR10.x and VR11 specifications Programmable short-circuit protection with programmable latch-off delay Desktop PC power supplies for Next generation processors VRM modules The ADP3193A1 is a highly efficient, multiphase, synchronous buck switching regulator controller optimized for converting a 12 V main supply into the core supply voltage required by high performance Intel processors. It uses an internal 8-bit DAC to read a voltage identification VID code directly from the processor, which is used to set the output voltage between V and V. This device uses a multimode PWM architecture to drive the logic-level outputs at a programmable switching frequency that can be optimized for VR size and efficiency. The phase relationship of the output signals can be programmed to provide 2- or 3-phase operation, allowing for the construction of up to three complementary buck switching stages. The ADP3193A also includes programmable no load offset and slope functions to adjust the output voltage as a function of the load current, optimally positioning it for a system transient. The ADP3193A also provides accurate and reliable short-circuit protection, adjustable current limiting, and delayed power-good output that accommodates on-the-fly output voltage changes requested by the CPU. FUNCTIONAL BLOCK DIAGRAM GND 14 VCC 23 SHUNT REGULATOR UVLO SHUTDOWN 850mV +150mV CSREF + PWRGD 2 DELAY ILIMIT 8 DELAY 7 RT RAMPADJ OSCILLATOR + CMP SET EN RESET 15 OD 22 PWM1 CURRENT BALANCING CIRCUIT + CMP + CMP 21 PWM2 RESET 20 PWM3 2-/3-PHASE DRIVER LOGIC RESET CROWBAR CURRENT LIMIT CURRENT MEASUREMENT AND LIMIT 19 SW1 18 SW2 17 SW3 13 CSCOMP 11 CSREF 12 CSSUM Dynamic VID 12 Power-Good 12 Output Crowbar 12 Output Enable and UVLO 13 Application 19 Setting the Clock 19 Soft Start Delay 19 Current-Limit Latch-Off Delay Times 19 Inductor Selection 19 Current Sense 20 Inductor DCR Temperature Correction 21 Output Offset 21 COUT Selection 22 Power 23 Ramp Resistor 24 COMP Pin Ramp 24 Current-Limit 24 Feedback Loop Compensation 25 CIN Selection and Input Current di/dt Reduction.................. 26 Shunt Resistor 26 Tuning Procedure for 27 Layout and Component Placement 29 Outline Dimensions 30 Ordering Guide 30 ADP3193A SPECIFICATIONS VCC = 5 V, FBRTN = GND, TA = 0°C to 85°C, unless otherwise noted.1 Table Parameter REFERENCE CURRENT Reference Bias Voltage Reference Bias Current ERROR AMPLIFIER Output Voltage Range2 Accuracy Differential Nonlinearity Input Bias Current FBRTN Current Output Current Gain Bandwidth Product Slew Rate Boot Voltage Hold Time VID INPUTS Input Low Voltage Input High Voltage Input Current VID Transition Delay Time2 No CPU Detection Turn-Off Delay Time2 OSCILLATOR Frequency Range2 Frequency Variation Output Voltage RAMPADJ Output Voltage RAMPADJ Input Current Range CURRENT SENSE AMPLIFIER Offset Voltage Input Bias Current Gain Bandwidth Product Slew Rate Input Common-Mode Range Output Voltage Range Output Current Limit Latch-Off Delay Time CURRENT BALANCE AMPLIFIER Common-Mode Range Input Resistance Input Current Input Current Matching Symbol Conditions Min Typ Max Unit VIREF IIREF RIREF = 100 kΩ VCOMP VFB VFB BOOT IFB IFBRTN ICOMP GBW ERR tBOOT Relative to nominal DAC output, referenced to FBRTN see Figure 4 In startup −1 IFB = IIREF FB forced to VOUT − 3% COMP = FB COMP = FB CDELAY = 10 nF V +1 LSB uA 200 uA uA MHz V/us ms VIL VID VIH VID IIN VID VID x , VIDSEL VID x , VIDSEL VID code change to FB change VID code change to PWM going low −1 fOSC fPHASE VRT VRAMPADJ IRAMPADJ TA = 25°C, RT = 210 kΩ, 3-phase TA = 25°C, RT = 100 kΩ, 3-phase TA = 25°C, RT = 40 kΩ, 3-phase RT = 243 kΩ to GND RAMPADJ − FB 240 260 293 kHz 1000 −50 +50 mV VOS CSA IBIAS CSSUM GBW CSA CSSUM − CSREF see Figure 4 CSSUM = CSCOMP CCSCOMP = 10 pF CSSUM and CSREF ICSCOMP tOC DELAY ORDERING GUIDE Model Temperature Range ADP3193AJCPZ-RL1 0°C to 85°C Package Description 32-Lead Frame Chip Scale Package [LFCSP_VQ] Package Option CP-32-2 Ordering Quantity 2,500 1 Z = RoHS Compliant Part. NOTES ADP3193A ADP3193A NOTES 2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06652-0-5/07 0

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8-Bit, Programmable, 2- to 3-Phase, Synchronous Buck Controller ADP3193A

Selectable 2- or 3-phase operation at up to 1 MHz per phase mV worst-case differential sensing error over
temperature Logic-level PWM outputs for interface to external high
power drivers Fast enhanced PWM FEPWM flex mode for excellent load
transient performance Active current balancing between all output phases Built-in power-good/crowbar blanking supports on-the-fly

VID code changes Digitally programmable V to V output supports both

VR10.x and VR11 specifications Programmable short-circuit protection with programmable
latch-off delay

Desktop PC power supplies for Next generation processors VRM modules

The ADP3193A1 is a highly efficient, multiphase, synchronous buck switching regulator controller optimized for converting a 12 V main supply into the core supply voltage required by high performance Intel processors. It uses an internal 8-bit DAC to read a voltage identification VID code directly from the processor, which is used to set the output voltage between V and V.

This device uses a multimode PWM architecture to drive the logic-level outputs at a programmable switching frequency that can be optimized for VR size and efficiency. The phase relationship of the output signals can be programmed to provide 2- or 3-phase operation, allowing for the construction of up to three complementary buck switching stages.

The ADP3193A also includes programmable no load offset and slope functions to adjust the output voltage as a function of the load current, optimally positioning it for a system transient. The ADP3193A also provides accurate and reliable short-circuit protection, adjustable current limiting, and delayed power-good output that accommodates on-the-fly output voltage changes requested by the CPU.

FUNCTIONAL BLOCK DIAGRAM

GND 14

VCC 23

SHUNT REGULATOR

UVLO SHUTDOWN
850mV
+150mV

CSREF +

PWRGD 2

DELAY

ILIMIT 8 DELAY 7

RT RAMPADJ

OSCILLATOR
+ CMP

SET EN RESET
15 OD 22 PWM1

CURRENT BALANCING CIRCUIT
+ CMP
+ CMP
21 PWM2

RESET 20 PWM3
2-/3-PHASE DRIVER LOGIC

RESET

CROWBAR

CURRENT LIMIT

CURRENT MEASUREMENT

AND LIMIT
19 SW1 18 SW2 17 SW3 13 CSCOMP 11 CSREF
12 CSSUM
Dynamic VID 12 Power-Good 12 Output Crowbar 12 Output Enable and UVLO 13 Application 19 Setting the Clock 19 Soft Start Delay 19 Current-Limit Latch-Off Delay Times 19 Inductor Selection 19 Current Sense 20 Inductor DCR Temperature Correction 21 Output Offset 21 COUT Selection 22 Power 23 Ramp Resistor 24 COMP Pin Ramp 24 Current-Limit 24 Feedback Loop Compensation 25 CIN Selection and Input Current di/dt Reduction.................. 26 Shunt Resistor 26 Tuning Procedure for 27 Layout and Component Placement 29 Outline Dimensions 30 Ordering Guide 30

ADP3193A

SPECIFICATIONS

VCC = 5 V, FBRTN = GND, TA = 0°C to 85°C, unless otherwise noted.1

Table Parameter REFERENCE CURRENT

Reference Bias Voltage Reference Bias Current ERROR AMPLIFIER Output Voltage Range2 Accuracy

Differential Nonlinearity Input Bias Current FBRTN Current Output Current Gain Bandwidth Product Slew Rate Boot Voltage Hold Time VID INPUTS Input Low Voltage Input High Voltage Input Current VID Transition Delay Time2 No CPU Detection Turn-Off Delay Time2 OSCILLATOR Frequency Range2 Frequency Variation

Output Voltage RAMPADJ Output Voltage RAMPADJ Input Current Range CURRENT SENSE AMPLIFIER Offset Voltage Input Bias Current Gain Bandwidth Product Slew Rate Input Common-Mode Range Output Voltage Range Output Current Limit Latch-Off Delay Time CURRENT BALANCE AMPLIFIER Common-Mode Range Input Resistance Input Current Input Current Matching

Symbol Conditions

Min Typ Max Unit

VIREF IIREF

RIREF = 100 kΩ

VCOMP VFB

VFB BOOT

IFB IFBRTN ICOMP GBW ERR
tBOOT

Relative to nominal DAC output, referenced to FBRTN see Figure 4

In startup
−1

IFB = IIREF

FB forced to VOUT − 3%

COMP = FB

COMP = FB

CDELAY = 10 nF

V +1 LSB uA 200 uA
uA MHz V/us ms

VIL VID VIH VID IIN VID

VID x , VIDSEL VID x , VIDSEL

VID code change to FB change VID code change to PWM going low
−1
fOSC fPHASE

VRT VRAMPADJ IRAMPADJ

TA = 25°C, RT = 210 kΩ, 3-phase TA = 25°C, RT = 100 kΩ, 3-phase TA = 25°C, RT = 40 kΩ, 3-phase RT = 243 kΩ to GND RAMPADJ − FB
240 260 293 kHz
1000
−50
+50 mV

VOS CSA IBIAS CSSUM GBW CSA

CSSUM − CSREF see Figure 4

CSSUM = CSCOMP CCSCOMP = 10 pF CSSUM and CSREF

ICSCOMP tOC DELAY
ORDERING GUIDE

Model

Temperature Range

ADP3193AJCPZ-RL1 0°C to 85°C

Package Description 32-Lead Frame Chip Scale Package [LFCSP_VQ]

Package Option CP-32-2
Ordering Quantity 2,500
1 Z = RoHS Compliant Part.

NOTES

ADP3193A

ADP3193A NOTES
2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.

D06652-0-5/07 0

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Datasheet ID: ADP3193AJCPZ-RL 517859