FIN210ACMLX

FIN210ACMLX Datasheet

µSerDes FIN210AC 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz

Part	Datasheet
FIN210ACMLX	FIN210ACMLX (pdf)

Related Parts	Information
FIN210ACGFX	FIN210ACGFX

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µSerDes FIN210AC 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz 120-Bit Serializer 120-Bit Des erializer December 2009 FIN210AC 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz Data & Control Bits Frequency Capability Interface µController Usage Selectable Edge Rates Standby Current Core Voltage VDDA/S I/O Voltage VDDP ESD I/O to GND Package Ordering Information Baseband 10-bit 48MHz Camera or LCD Microcontroller, RGB, YUV m68 & i86 Yes <10µA to 3.6V to 3.6V 15kV 32-Terminal MLP 42-Ball USS-BGA FIN210ACMLX FIN210ACGFX The FIN210AC µSerDes is a low-power serializer / deserializer optimized for use in cell phone displays and camera paths. The device reduces a 10-bit data path to four wires. For camera applications, an additional master clock can be passed in the opposite direction of data flow. The device utilizes Fairchild’s proprietary ultra-low power, lowEMI technology. Slider, Folder, & Clamshell Mobile Handsets Printers Security Cameras Related Resources For samples and questions, please contact: FIN210AC Internal Termination Built-in voltage translation FIN210AC Camera Module Isolates interface for signal integrity Up to 48MHz Camera Module Figure Mobile Phone Example µSerDes FIN210AC 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz FIN210AC Serializer DIRI=1 Pin Descriptions Pin Name DIRI CTL_ADJ Control to determine serializer or deserializer configuration. Adjusts CTL drive to compensate for environmental conditions and length. 0 Deserializer 1 Serializer 0 Low drive low power 1 High drive high power Configure frequency range for the PLL. See Table 1 Serializer DIRI=1 Control Pin. Configure frequency range for the PLL. See Table 1 Serializer DIRI=1 Control Pin. PLL0 Divide or adjust the serial frequency. See Table 1 Serializer DIRI=1 Control Pin. PLL1 Divide or adjust the serial frequency. See Table 1 Serializer DIRI=1 Control Pin. CKREF LV-CMOS clock input and PLL reference. STROBE LV-CMOS strobe input for latching data DP [1:12] into the serializer on the rising edge. DP[1:10]

PDF Datasheet Preview

µSerDes FIN210AC 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz
120-Bit Serializer
120-Bit Des erializer

December 2009

FIN210AC 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz
Data & Control Bits Frequency Capability Interface µController Usage Selectable Edge Rates Standby Current Core Voltage VDDA/S I/O Voltage VDDP ESD I/O to GND Package Ordering Information

Baseband
10-bit 48MHz Camera or LCD Microcontroller, RGB, YUV m68 & i86

Yes <10µA to 3.6V to 3.6V
15kV 32-Terminal MLP 42-Ball USS-BGA

FIN210ACMLX FIN210ACGFX

The FIN210AC µSerDes is a low-power serializer / deserializer optimized for use in cell phone displays and camera paths. The device reduces a 10-bit data path to four wires. For camera applications, an additional master clock can be passed in the opposite direction of data flow. The device utilizes Fairchild’s proprietary ultra-low power, lowEMI technology.

Slider, Folder, & Clamshell Mobile Handsets Printers Security Cameras

Related Resources

For samples and questions, please contact:

FIN210AC

Internal Termination

Built-in voltage translation

FIN210AC

Camera Module

Isolates interface for signal integrity

Up to 48MHz

Camera Module

Figure Mobile Phone Example
µSerDes FIN210AC 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz

FIN210AC Serializer DIRI=1 Pin Descriptions

Pin Name

DIRI CTL_ADJ

Control to determine serializer or deserializer configuration.

Adjusts CTL drive to compensate for environmental conditions and length.
0 Deserializer 1 Serializer 0 Low drive low power 1 High drive high power

Configure frequency range for the PLL.

See Table 1 Serializer DIRI=1 Control Pin.

Configure frequency range for the PLL.

See Table 1 Serializer DIRI=1 Control Pin.

PLL0

Divide or adjust the serial frequency.

See Table 1 Serializer DIRI=1 Control Pin.

PLL1

Divide or adjust the serial frequency.

See Table 1 Serializer DIRI=1 Control Pin.

CKREF

LV-CMOS clock input and PLL reference.

STROBE

LV-CMOS strobe input for latching data DP [1:12] into the serializer on the rising edge.

DP[1:10]

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Datasheet ID: FIN210ACMLX 514680