AT91SAM9G45B-CU-999

AT91SAM9G45B-CU-999 Datasheet


AT91SAM ARM-based Embedded MPU

Part Datasheet
AT91SAM9G45B-CU-999 AT91SAM9G45B-CU-999 AT91SAM9G45B-CU-999 (pdf)
Related Parts Information
AT91SAM9G45B-CU AT91SAM9G45B-CU AT91SAM9G45B-CU
AT91SAM9G45C-CU AT91SAM9G45C-CU AT91SAM9G45C-CU
AT91SAM9G45C-CU-999 AT91SAM9G45C-CU-999 AT91SAM9G45C-CU-999
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AT91SAM ARM-based Embedded MPU

SAM9G45

The ARM926EJ-S based SAM9G45 features the frequently demanded combination of user interface functionality and high data rate connectivity, including LCD Controller, resistive touch-screen, camera interface, audio, Ethernet 10/100 and high speed USB and SDIO. With the processor running at 400 MHz and multiple 100+ Mbps data rate peripherals, the SAM9G45 has the performance and bandwidth to the network or local storage media to provide an adequate user experience.

The SAM9G45 supports DDR2 and NAND Flash memory interfaces for program and data storage. An internal 133 MHz multi-layer bus architecture associated with 37 DMA channels, a dual external bus interface and distributed memory including a 64-Kbyte SRAM which can be configured as a tightly coupled memory TCM sustains the high bandwidth required by the processor and the high speed peripherals.

The I/Os support 1.8V or 3.3V operation, which are independently configurable for the memory interface and peripheral I/Os. This feature completely eliminates the need for any external level shifters. In addition it supports ball pitch package for low cost PCB manufacturing.

The SAM9G45 power management controller features efficient clock gating and a battery backup section minimizing power consumption in active and standby modes.

This is a summary document. The complete document is available on the Atmel website at
• 400 MHz ARM926EJ-S Processor 32 Kbytes Data Cache, 32 Kbytes Instruction Cache, MMU
• Memories DDR2 Controller 4-bank DDR2/LPDDR, SDRAM/LPSDR External Bus Interface supporting 4-bank DDR2/LPDDR, SDRAM/LPSDR, Static Memories, CompactFlash, SLC NAND Flash with ECC One 64-Kbyte internal SRAM, single-cycle access at system speed or processor speed through TCM interface One 64-Kbyte internal ROM, embedding bootstrap routine
• Peripherals LCD Controller supporting STN and TFT displays up to 1280*860 ITU-R BT. 601/656 Image Sensor Interface USB Device High Speed, USB Host High Speed and USB Host Full Speed with On-Chip Transceiver 10/100 Mbps Ethernet MAC Controller Two High Speed Memory Card Hosts SDIO, SDCard, MMC AC'97 controller Two Master/Slave Serial Peripheral Interfaces Two Three-channel 16-bit Timer/Counters Two Synchronous Serial Controllers I2S mode Four-channel 16-bit PWM Controller Two-wire Interfaces Four USARTs with ISO7816, IrDA, Manchester and SPI modes 8-channel 10-bit ADC with 4-wire Touch Screen support Write Protected Registers
• System 133 MHz twelve 32-bit layer AHB Bus Matrix 37 DMA Channels Boot from NAND Flash, SDCard, or serial DataFlash Reset Controller with on-chip Power-on Reset Selectable 32768 Hz Low-power and 12 MHz Crystal Oscillators Internal Low-power 32 kHz RC Oscillator One PLL for the system and one 480 MHz PLL optimized for USB High Speed Two Programmable External Clock Signals Advanced Interrupt Controller and Debug Unit Periodic Interval Timer, Watchdog Timer, Real Time Timer and Real Time Clock
• I/O Five 32-bit Parallel Input/Output Controllers 160 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os with Schmitt trigger input
• Package 324-ball TFBGA, pitch mm

SAM9G45 [Summary]

NTRST TTTTCDDMIKSO RTCK JTAGSEL BMS VHHFBHSGSDDPPAA,,HHFHSSDDMMAA

Block Diagram

Figure SAM9G45 Block Diagram

TST PCK0-PCK1

FI IR DR D DT D

IN OUT

IN32 OUT32 SHDN WKUP VDDBU

NRST VDDCORE

System Controller

JTAG / Boundary Scan

HS Transceiver

HS Transceiver

DBGU

PLLA PLLUTMI OSC12M

RC OSC 32K SHDC
4 GPBR RTT

RSTC

PIOA PIOB PIOC

PIOD PIOE

In-Circuit Emulator

ARM926EJ-S

ICache

DCache
32 Kbytes MMU 32 Kbytes

ITCM DTCM Bus Interface

PA PB

HS EHCI USB HOST
SAM9G45 Ordering Information
Table AT91SAM9G45 Ordering Information
Ordering Code

Package

AT91SAM9G45C-CU

TFBGA324

AT91SAM9G45B-CU

TFBGA324

AT91SAM9G45-CU

TFBGA324

Package Type Green

Temperature Operating Range

Industrial -40°C to 85°C

Industrial -40°C to 85°C

Industrial -40°C to 85°C

SAM9G45 [Summary] 50

In the table that follows, the initials “rfo” indicate changes requested by product experts, or made during proof reading as part of the approval process.
6438CS
6438DS 6438ES 6438FS

Comments

First issue

Section “Signal Description”, Table 3-1 in “Reset/Test” description, NRST pin updated with note concerning NRST configuration. Section “Package and Pinout”, Table 4-1, updated.

Introduction “Features” part was edited.

LFBGA replaced by TFBGA in “Features” part and Section “Mechanical Overview of the 324-ball TFBGA Package”

Section “Signal Description”, Table 3-1, Touch Screen Analog-to-Digital Converter on page 9 part was edited. VDDCORE removed from “Ground pins GND are common to...” sentence in Section “Power Supplies”

Figure was removed. changed into in Section “Internal ROM”.
“Two Three-channel 16-bit Timer/Counters” peripheral feature changed into “Two Three-channel 16-bit Timer/Counters”

ECC row added to Figure 7-1 “SAM9G45 Memory Mapping”

Section “Bus Matrix”, Figure 6-1 “DDR Multi-port”, and text above and below added. 1 row and 1 column added to Table 6-3 and Table

Typos corrected in Table 6-6, Table 6-7, Table 9-1 and Figure 2-1 RNG --> TRNG, PWMC --> PWM, AC97 --> AC97C, TSDAC --> TSADCC.

Section “External Memories” reorganized.

New Figure 11-1 “324-ball TFBGA Package Drawing”.
‘11-layer’ --> ‘12-layer’ in Section “Bus Matrix”.

Section “True Random Number Generator TRNG ” added.
1st Page/headers & footers text where found Product Line/Product naming convention changed - AT91SAM ARM-based MPU / SAM9G45

Section “Power Supplies”, replaced ground pin names by GNDIOM, GNDCORE, GNDANA, GNDIOP, GNDBU, GNDOSC, GNDUTMI. Reorganized text describing GND association to power supply pins.

Section “Description”, updated 2nd paragraph, 1st sentence. “...SAM9G45 supports DDR2...”

Change Request Ref.
6600 6669
6715 RFO
6647
6715
6828 6842 6797
Section “SAM9G45 Ordering Information”, fixed error in ordering information table.
7953
Section “SAM9G45 Ordering Information”, a second ordering code added AT91SAM9G45B-CU. An MRL column added too.
7979
Section “SAM9G45 Ordering Information”, added AT91SAM9G45C-CU and MLR C to Table 12-1, “AT91SAM9G45 Ordering Information”

Section “Features”, added Write Protected Registers to “Peripherals”
8551 8213

SAM9G45 [Summary] 52

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Datasheet ID: AT91SAM9G45B-CU-999 519374