FIN1019M

FIN1019M Datasheet

FIN1019 3.3V LVDS High Speed Differential Driver/Receiver

Part	Datasheet
FIN1019M	FIN1019M (pdf)

Related Parts	Information
FIN1019MTCX	FIN1019MTCX
FIN1019MX	FIN1019MX
FIN1019MTC	FIN1019MTC

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FIN1019 3.3V LVDS High Speed Differential Driver/Receiver FIN1019 3.3V LVDS High Speed Differential Driver/Receiver This driver and receiver pair are designed for high speed interconnects utilizing Low Voltage Differential Signaling LVDS technology. The driver translates LVTTL signals to LVDS levels with a typical differential output swing of 350mV and the receiver translates LVDS signals, with a typical differential input threshold of 100mV, into LVTTL levels. LVDS technology provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed clock or data transfer. s Greater than 400Mbs data rate s 3.3V power supply operation s 0.5ns maximum differential pulse skew s 2.5ns maximum propagation delay s Low power dissipation s Power-Off protection s 100mV receiver input sensitivity s Fail safe protection open-circuit, shorted and terminated conditions s Meets or exceeds the TIA/EIA-644 LVDS standard s Flow-through pinout simplifies PCB layout s 14-Lead SOIC and TSSOP packages save space Ordering Code: Order Number Package Number Package Description FIN1019M M14A 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow FIN1019MTC MTC14 14-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Function Table Connection Diagram Inputs Outputs RIN+ RIN− ROUT L Fail Safe Condition DOUT+ DOUT− Open−Circuit or Z H = HIGH Logic Level Z = High Impedance L = LOW Logic Level X = Don’t Care Fail Safe = Open, Shorted, Terminated Pin Descriptions Pin Name DIN DOUT+ DOUT− RIN+ RIN− ROUT VCC GND NC Description LVTTL Data Input Non-inverting LVDS Output Inverting LVDS Output Driver Enable LVTTL, Active HIGH Non-Inverting LVDS Input Inverting LVDS Input LVTTL Receiver Output Receiver Enable LVTTL, Active LOW Power Supply Ground No Connect 2001 Fairchild Semiconductor Corporation DS500506 FIN1019 Absolute Maximum Ratings Note 1 Supply Voltage VCC −0.5V to +4.6V LVTTL DC Input Voltage DIN, DE, RE −0.5V to +6V LVDS DC Input Voltage RIN+, RIN− −0.5V to 4.7V LVTTL DC Output Voltage ROUT −0.5V to +6V LVDS DC Output Voltage DOUT+, DOUT− −0.5V to 4.7V LVDS Driver Short Circuit Current IOSD Continuous LVTTL DC Output Current IO 16 mA Storage Temperature Range TSTG −65°C to +150°C

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FIN1019 3.3V LVDS High Speed Differential Driver/Receiver

FIN1019 3.3V LVDS High Speed Differential Driver/Receiver

This driver and receiver pair are designed for high speed interconnects utilizing Low Voltage Differential Signaling LVDS technology. The driver translates LVTTL signals to LVDS levels with a typical differential output swing of 350mV and the receiver translates LVDS signals, with a typical differential input threshold of 100mV, into LVTTL levels. LVDS technology provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed clock or data transfer.
s Greater than 400Mbs data rate s 3.3V power supply operation s 0.5ns maximum differential pulse skew s 2.5ns maximum propagation delay s Low power dissipation s Power-Off protection s 100mV receiver input sensitivity s Fail safe protection open-circuit, shorted and terminated
conditions s Meets or exceeds the TIA/EIA-644 LVDS standard s Flow-through pinout simplifies PCB layout s 14-Lead SOIC and TSSOP packages save space
Ordering Code:

Order Number Package Number

Package Description

FIN1019M

M14A
14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow

FIN1019MTC

MTC14
14-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Function Table

Connection Diagram

Inputs

Outputs

RIN+

RIN−

ROUT L

Fail Safe Condition

DOUT+

DOUT−

Open−Circuit or Z

H = HIGH Logic Level Z = High Impedance

L = LOW Logic Level

X = Don’t Care

Fail Safe = Open, Shorted, Terminated

Pin Descriptions

Pin Name

DIN DOUT+ DOUT−

RIN+ RIN− ROUT

VCC GND NC

Description LVTTL Data Input Non-inverting LVDS Output Inverting LVDS Output Driver Enable LVTTL, Active HIGH Non-Inverting LVDS Input Inverting LVDS Input LVTTL Receiver Output

Receiver Enable LVTTL, Active LOW Power Supply Ground No Connect
2001 Fairchild Semiconductor Corporation DS500506

FIN1019

Absolute Maximum Ratings Note 1

Supply Voltage VCC
−0.5V to +4.6V

LVTTL DC Input Voltage DIN, DE, RE
−0.5V to +6V

LVDS DC Input Voltage RIN+, RIN−
−0.5V to 4.7V

LVTTL DC Output Voltage ROUT
−0.5V to +6V

LVDS DC Output Voltage DOUT+, DOUT− −0.5V to 4.7V

LVDS Driver Short Circuit Current IOSD

Continuous

LVTTL DC Output Current IO
16 mA

Storage Temperature Range TSTG
−65°C to +150°C

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Datasheet ID: FIN1019M 514662