FIN1215MTD

FIN1215MTD Datasheet

FIN1215 /FIN1216 / FIN1217 / FIN1218 LVDS 21-Bit Serializers / De-Serializers

Part	Datasheet
FIN1215MTD	FIN1215MTD (pdf)

Related Parts	Information
FIN1218MTDX	FIN1218MTDX
FIN1217MTD	FIN1217MTD

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FIN1215 /FIN1216 / FIN1217 / FIN1218 LVDS 21-Bit Serializers / De-Serializers March 2008 FIN1215 / FIN1216 / FIN1217 FIN1218 LVDS 21-Bit Serializers / De-Serializers Low Power Consumption 20MHz to 85MHz Shift Clock Support 50% Duty Cycle on the Clock Output of Receiver ±1V Common-mode Range ~1.2V Narrow Bus Reduces Cable Size and Cost High Throughput 1.785Gbps Up to 595Mbps per Channel Internal PLL with No External Components Compatible with TIA/EIA-644 Specification Offered in 48-lead TSSOP Packages The FIN1217 and FIN1215 transform 21-bit wide parallel LVTTL Low-Voltage TTL data into three serial LVDS Low-Voltage Differential Signaling data streams. A phase-locked transmit clock is transmitted in parallel with the data stream over a separate LVDS link. Every cycle of transmit clock, 21 bits of input LVTTL data are sampled and transmitted. The FIN1218 and FIN1216 receive and convert the three serial LVDS data streams back into 21 bits of LVTTL data. Table 1 provides a matrix summary of the serializers and de-serializers available. For the FIN1217, at a transmit clock frequency of 85MHz, 21 bits of LVTTL data are transmitted at a rate of 595Mbps per LVDS channel. These chipsets solve EMI and cable size problems associated with wide and high-speed TTL interfaces. Ordering Information Operating Temperature Range Package FIN1215MTDX FIN1216MTDX FIN1217MTD FIN1217MTDX FIN1218MTDX -40 to + 85°C -40 to + 85°C -40 to + 85°C -40 to + 85°C -40 to + 85°C 48-Lead Thin Shrink Small Outline Package TSSOP 48-Lead Thin Shrink Small Outline Package TSSOP 48-Lead Thin Shrink Small Outline Package TSSOP 48-Lead Thin Shrink Small Outline Package TSSOP 48-Lead Thin Shrink Small Outline Package TSSOP All packages are lead free per JEDEC J-STD-020B standard. Packing Method Tape and Reel Tape and Reel Trays Tape and Reel Tape and Reel FIN1215 /FIN1216 / FIN1217 / FIN1218 LVDS 21-Bit Serializers / De-Serializers Block Diagrams Figure FIN1217 / FIN1215 Transmitter Functional Diagram Figure FIN1218 / FIN1216 Transmitter Functional Diagram Table Serializers / De-Serializers Chip Matrix Part FIN1215 FIN1216 FIN1217 FIN1218 CLK Frequency 66 85 LVTTL IN 21 LVDS OUT 3 LVDS IN 3 LVTTL OUT Package 48-Lead TSSOP 48-Lead TSSOP 48-Lead TSSOP 48-Lead TSSOP 2003 Fairchild Semiconductor Corporation FIN1215 /FIN1216 / FIN1217 / FIN1218 LVDS 21-Bit Serializers / De-Serializers Transmitters Pin Configuration Figure FIN1217 / FIN1215 21:3 Transmitter Pin Definitions Pin Names TxIn TxCKLIn TxOut+ TxOut TxCLKOut+ TxCLKOut- /PwrDn PLL VCC PLL GND LVDS VCC LVDS GND VCC GND NC I/O Type # of Pins 21 1 3 1 1 2 1 3 4 5 Description of Signals

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FIN1215 /FIN1216 / FIN1217 / FIN1218 LVDS 21-Bit Serializers / De-Serializers

March 2008

FIN1215 / FIN1216 / FIN1217 FIN1218 LVDS 21-Bit Serializers / De-Serializers

Low Power Consumption 20MHz to 85MHz Shift Clock Support 50% Duty Cycle on the Clock Output of Receiver ±1V Common-mode Range ~1.2V Narrow Bus Reduces Cable Size and Cost High Throughput 1.785Gbps Up to 595Mbps per Channel Internal PLL with No External Components Compatible with TIA/EIA-644 Specification Offered in 48-lead TSSOP Packages

The FIN1217 and FIN1215 transform 21-bit wide parallel LVTTL Low-Voltage TTL data into three serial LVDS Low-Voltage Differential Signaling data streams. A phase-locked transmit clock is transmitted in parallel with the data stream over a separate LVDS link. Every cycle of transmit clock, 21 bits of input LVTTL data are sampled and transmitted.

The FIN1218 and FIN1216 receive and convert the three serial LVDS data streams back into 21 bits of LVTTL data. Table 1 provides a matrix summary of the serializers and de-serializers available. For the FIN1217, at a transmit clock frequency of 85MHz, 21 bits of LVTTL data are transmitted at a rate of 595Mbps per LVDS channel.

These chipsets solve EMI and cable size problems associated with wide and high-speed TTL interfaces.
Ordering Information

Operating Temperature Range

Package

FIN1215MTDX FIN1216MTDX FIN1217MTD FIN1217MTDX FIN1218MTDX
-40 to + 85°C -40 to + 85°C -40 to + 85°C -40 to + 85°C -40 to + 85°C
48-Lead Thin Shrink Small Outline Package TSSOP 48-Lead Thin Shrink Small Outline Package TSSOP 48-Lead Thin Shrink Small Outline Package TSSOP 48-Lead Thin Shrink Small Outline Package TSSOP 48-Lead Thin Shrink Small Outline Package TSSOP

All packages are lead free per JEDEC J-STD-020B standard.

Packing Method

Tape and Reel Tape and Reel

Trays Tape and Reel Tape and Reel

FIN1215 /FIN1216 / FIN1217 / FIN1218 LVDS 21-Bit Serializers / De-Serializers

Block Diagrams

Figure FIN1217 / FIN1215 Transmitter Functional Diagram

Figure FIN1218 / FIN1216 Transmitter Functional Diagram

Table Serializers / De-Serializers Chip Matrix

Part

FIN1215 FIN1216 FIN1217 FIN1218

CLK Frequency
66 85

LVTTL IN 21

LVDS OUT 3

LVDS IN 3

LVTTL OUT

Package
48-Lead TSSOP 48-Lead TSSOP 48-Lead TSSOP 48-Lead TSSOP
2003 Fairchild Semiconductor Corporation

FIN1215 /FIN1216 / FIN1217 / FIN1218 LVDS 21-Bit Serializers / De-Serializers

Transmitters Pin Configuration

Figure FIN1217 / FIN1215 21:3 Transmitter

Pin Definitions

Pin Names

TxIn TxCKLIn TxOut+

TxOut TxCLKOut+ TxCLKOut-
/PwrDn

PLL VCC PLL GND LVDS VCC LVDS GND

VCC GND NC

I/O Type
# of Pins
21 1 3 1
1 2 1 3 4 5

Description of Signals

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Datasheet ID: FIN1215MTD 514675