FDS6812A

FDS6812A Datasheet

FDS6812A

Part	Datasheet
FDS6812A	FDS6812A (pdf)

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FDS6812A November 2001 FDS6812A Dual N-Channel Logic Level PWM Optimized MOSFET These N-Channel Logic Level MOSFETs are produced using Fairchild Semiconductor’s advanced PowerTrench process that has been especially tailored to minimize the on-state resistance and yet maintain superior switching performance. These devices are well suited for low voltage and battery powered applications where low in-line power loss and fast switching are required. • A, 20 V. RDS ON = 22 VGS = V RDS ON = 35 VGS = V • Low gate charge 12 nC typical • High performance trench technology for extremely low RDS ON • High power and current handling capability DD1 DD2 SO-8 Pin 1 SO-8 SS2GS2SS1GG1 Absolute Maximum Ratings TA=25oC unless otherwise noted VDSS VGSS ID Parameter Drain-Source Voltage Gate-Source Voltage Drain Current Continuous Pulsed Power Dissipation for Dual Operation Power Dissipation for Single Operation Note 1a Note 1a Note 1b Note 1c TJ, TSTG Operating and Storage Junction Temperature Range Thermal Characteristics Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case Note 1a Note 1 Package Marking and Ordering Information Device Marking Device Reel Size FDS6812A FDS6812A 13’’ Ratings 20 ± 12 35 2 1 to +150 78 40 Tape width 12mm Units °C/W °C/W Quantity 2500 units 2001 Fairchild Semiconductor Corporation FDS6812A Electrical Characteristics Parameter TA = 25°C unless otherwise noted Test Conditions Min Typ Max Units Off Characteristics BVDSS IDSS IGSSF Breakdown Voltage Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current Leakage, Forward VGS = 0 V, ID = 250 µA ID = 250 µA, Referenced to 25°C VDS = 16 V, VGS = 0 V VDS = 16 V, VGS = 0 V, TJ = 55°C VGS = 12 V, VDS = 0 V IGSSR VGS = V, VDS = 0 V mV/°C On Characteristics Note 2 VGS th RDS on Gate Threshold Voltage Gate Threshold Voltage Temperature Coefficient Static

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FDS6812A

November 2001

FDS6812A

Dual N-Channel Logic Level PWM Optimized MOSFET

These N-Channel Logic Level MOSFETs are produced using Fairchild Semiconductor’s advanced PowerTrench process that has been especially tailored to minimize the on-state resistance and yet maintain superior switching performance.

These devices are well suited for low voltage and battery powered applications where low in-line power loss and fast switching are required.
• A, 20 V.

RDS ON = 22 VGS = V RDS ON = 35 VGS = V
• Low gate charge 12 nC typical
• High performance trench technology for extremely low RDS ON
• High power and current handling capability

DD1 DD2

SO-8

Pin 1 SO-8

SS2GS2SS1GG1

Absolute Maximum Ratings TA=25oC unless otherwise noted

VDSS VGSS ID

Parameter

Drain-Source Voltage Gate-Source Voltage Drain Current Continuous

Pulsed Power Dissipation for Dual Operation Power Dissipation for Single Operation

Note 1a Note 1a

Note 1b

Note 1c

TJ, TSTG

Operating and Storage Junction Temperature Range

Thermal Characteristics

Thermal Resistance, Junction-to-Ambient

Thermal Resistance, Junction-to-Case

Note 1a Note 1
Package Marking and Ordering Information

Device Marking

Device

Reel Size

FDS6812A

FDS6812A
13’’

Ratings
20 ± 12 35
2 1 to +150
78 40

Tape width 12mm

Units
°C/W °C/W

Quantity 2500 units
2001 Fairchild Semiconductor Corporation

FDS6812A

Electrical Characteristics

Parameter

TA = 25°C unless otherwise noted

Test Conditions

Min Typ Max Units

Off Characteristics

BVDSS

IDSS

IGSSF

Breakdown Voltage Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current

Leakage, Forward

VGS = 0 V, ID = 250 µA

ID = 250 µA, Referenced to 25°C

VDS = 16 V, VGS = 0 V VDS = 16 V, VGS = 0 V, TJ = 55°C

VGS = 12 V, VDS = 0 V

IGSSR

VGS = V, VDS = 0 V
mV/°C

On Characteristics Note 2

VGS th

RDS on

Gate Threshold Voltage

Gate Threshold Voltage Temperature Coefficient

Static

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Datasheet ID: FDS6812A 514344