DM74LS73AN

DM74LS73AN Datasheet

DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

Part	Datasheet
DM74LS73AN	DM74LS73AN (pdf)

PDF Datasheet Preview
DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the transition time of the negative going edge of the clock pulse. The data on the J and K inputs is allowed to change while the clock is HIGH or LOW without affecting the outputs as long as setup and hold times are not violated. A low logic level on the clear input will reset the outputs regardless of the levels of the other inputs. Ordering Code: Order Number Package Number Package Description DM74LS73AM M14A 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-120, Narrow DM74LS73AN N14A 14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Inputs Outputs CLR CLK Toggle H = HIGH Logic Level L = LOW Logic Level X = Either LOW or HIGH Logic Level = Negative going edge of pulse. Q0 = The output logic level before the indicated input conditions were established. Toggle = Each output changes to the complement of its previous level on each falling edge of the clock pulse. 2000 Fairchild Semiconductor Corporation DS006372 DM74LS73A Absolute Maximum Ratings Note 1 Supply Voltage Input Voltage Operating Free Air Temperature Range 0°C to +70°C Storage Temperature Range −65°C to +150°C Note 1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Recommended Operating Conditions Parameter Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current fCLK Clock Frequency Note 2 fCLK Clock Frequency Note 3 Pulse Width Clock HIGH Note 2 Preset LOW Clear LOW Pulse Width Clock HIGH Note 3 Preset LOW Clear LOW Setup Time Note 2 Note 4

PDF Datasheet Preview

DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

DM74LS73A

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the transition time of the negative going edge of the clock pulse. The data on the J and K inputs is allowed to change while the clock is HIGH or LOW without affecting the outputs as long as setup and hold times are not violated. A low logic level on the clear input will reset the outputs regardless of the levels of the other inputs.
Ordering Code:

Order Number Package Number

Package Description

DM74LS73AM

M14A
14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-120, Narrow

DM74LS73AN

N14A
14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Function Table

Inputs

Outputs

CLR CLK

Toggle

H = HIGH Logic Level L = LOW Logic Level X = Either LOW or HIGH Logic Level = Negative going edge of pulse. Q0 = The output logic level before the indicated input conditions were established.

Toggle = Each output changes to the complement of its previous level on each falling edge of the clock pulse.
2000 Fairchild Semiconductor Corporation DS006372

DM74LS73A

Absolute Maximum Ratings Note 1

Supply Voltage

Input Voltage

Operating Free Air Temperature Range
0°C to +70°C

Storage Temperature Range
−65°C to +150°C

Note 1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

Recommended Operating Conditions

Parameter

Supply Voltage

HIGH Level Input Voltage

LOW Level Input Voltage

HIGH Level Output Current

LOW Level Output Current
fCLK

Clock Frequency Note 2
fCLK

Clock Frequency Note 3

Pulse Width

Clock HIGH

Note 2

Preset LOW

Clear LOW

Pulse Width

Clock HIGH

Note 3

Preset LOW

Clear LOW

Setup Time Note 2 Note 4

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived DM74LS73AN Datasheet file may be downloaded here without warranties.

Datasheet ID: DM74LS73AN 513810