DM74LS503N

DM74LS503N Datasheet

DM74LS503 8-Bit Successive Approximation Register

Part	Datasheet
DM74LS503N	DM74LS503N (pdf)

PDF Datasheet Preview
DM74LS503 8-Bit Successive Approximation Register DM74LS503 8-Bit Successive Approximation Register with Expansion Control The DM74LS503 register has an active LOW Enable E input that is used in cascading two or more packages for longer word lengths. A HIGH signal on E, after a START operation, forces Q7 HIGH and prevents the device from accepting serial data. With the E input of an DM74LS503 connected to the CC output of a preceding more significant device, the DM74LS503 will be inhibited until the preceding device is filled, causing its CC output to go LOW. This LOW signal then enables the DM74LS503 to accept the serial data on subsequent clocks. s Performs serial-to-parallel conversion s Expansion control for longer words s Storage and control for successive approximation A to D conversion s Low power Schottky version of 2503 Ordering Code: Order Number Package Number Package Description DM74LS503N N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Connection Diagram Logic Symbol VCC = Pin 16 GND = Pin 8 Pin Descriptions Pin Names D S CP E CC Q7 Description Serial Data Input Start Input Active LOW Clock Pulse Input Active Rising Edge Conversion Enable Input Active LOW Conversion Complete Output Active LOW Parallel Register Outputs Complement of Q7 Output 2000 Fairchild Semiconductor Corporation DS010190 DM74LS503 Logic Diagrams Note Cell logic is repeated for register stages Q5 to Q1. Connection for Longer Word Lengths DM74LS503 Absolute Maximum Ratings Note 1 Supply Voltage Input Voltage Operating Free Air Temperature Range 0°C to +70°C Storage Temperature Range −65°C to +150°C Note 1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Recommended Operating Conditions VCC VIH VIL IOH IOL TA tS H tS L tH H tH L tS H tS L tH H tH L tW H tW L Parameter Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage LOW Level Output Current Free Air Operating Temperature Setup Time HIGH or LOW S to CP Hold Time HIGH or LOW S to CP Setup Time HIGH or LOW D to CP Hold Time HIGH or LOW D to CP Pulse Width HIGH or LOW Units 16 ns 10 ns 46 ns Electrical Characteristics Over recommended operating free air temperature range unless otherwise noted Parameter Conditions Input Clamp Voltage VCC = Min, II = −18 mA HIGH Level Output Voltage VCC = Min, IOH = Max,

PDF Datasheet Preview

DM74LS503 8-Bit Successive Approximation Register

DM74LS503 8-Bit Successive Approximation Register with Expansion Control

The DM74LS503 register has an active LOW Enable E input that is used in cascading two or more packages for longer word lengths. A HIGH signal on E, after a START operation, forces Q7 HIGH and prevents the device from accepting serial data. With the E input of an DM74LS503 connected to the CC output of a preceding more significant device, the DM74LS503 will be inhibited until the preceding device is filled, causing its CC output to go LOW. This LOW signal then enables the DM74LS503 to accept the serial data on subsequent clocks.
s Performs serial-to-parallel conversion s Expansion control for longer words s Storage and control for successive approximation A to D
conversion s Low power Schottky version of 2503
Ordering Code:

Order Number Package Number

Package Description

DM74LS503N

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide

Connection Diagram

Logic Symbol

VCC = Pin 16 GND = Pin 8

Pin Descriptions

Pin Names D S CP E CC Q7

Description Serial Data Input Start Input Active LOW Clock Pulse Input Active Rising Edge Conversion Enable Input Active LOW Conversion Complete Output Active LOW Parallel Register Outputs Complement of Q7 Output
2000 Fairchild Semiconductor Corporation DS010190

DM74LS503

Logic Diagrams

Note Cell logic is repeated for register stages Q5 to Q1.

Connection for Longer Word Lengths

DM74LS503

Absolute Maximum Ratings Note 1

Supply Voltage

Input Voltage

Operating Free Air Temperature Range 0°C to +70°C

Storage Temperature Range
−65°C to +150°C

Note 1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

Recommended Operating Conditions

VCC VIH VIL IOH IOL TA tS H tS L tH H tH L tS H tS L tH H tH L tW H tW L

Parameter Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage LOW Level Output Current Free Air Operating Temperature Setup Time HIGH or LOW S to CP Hold Time HIGH or LOW S to CP Setup Time HIGH or LOW D to CP Hold Time HIGH or LOW D to CP Pulse Width HIGH or LOW

Units
16 ns
10 ns
46 ns

Electrical Characteristics

Over recommended operating free air temperature range unless otherwise noted

Parameter

Conditions

Input Clamp Voltage

VCC = Min, II = −18 mA

HIGH Level

Output Voltage

VCC = Min, IOH = Max,

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived DM74LS503N Datasheet file may be downloaded here without warranties.

Datasheet ID: DM74LS503N 513802